GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / lpc32xx.dtsi
1 /*
2  * NXP LPC32xx SoC
3  *
4  * Copyright 2012 Roland Stigge <stigge@antcom.de>
5  *
6  * The code contained herein is licensed under the GNU General Public
7  * License. You may obtain a copy of the GNU General Public License
8  * Version 2 or later at the following locations:
9  *
10  * http://www.opensource.org/licenses/gpl-license.html
11  * http://www.gnu.org/copyleft/gpl.html
12  */
13
14 #include "skeleton.dtsi"
15
16 #include <dt-bindings/clock/lpc32xx-clock.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18
19 / {
20         compatible = "nxp,lpc3220";
21         interrupt-parent = <&mic>;
22
23         cpus {
24                 #address-cells = <1>;
25                 #size-cells = <0>;
26
27                 cpu@0 {
28                         compatible = "arm,arm926ej-s";
29                         device_type = "cpu";
30                         reg = <0x0>;
31                 };
32         };
33
34         clocks {
35                 xtal_32k: xtal_32k {
36                         compatible = "fixed-clock";
37                         #clock-cells = <0>;
38                         clock-frequency = <32768>;
39                         clock-output-names = "xtal_32k";
40                 };
41
42                 xtal: xtal {
43                         compatible = "fixed-clock";
44                         #clock-cells = <0>;
45                         clock-frequency = <13000000>;
46                         clock-output-names = "xtal";
47                 };
48         };
49
50         ahb {
51                 #address-cells = <1>;
52                 #size-cells = <1>;
53                 compatible = "simple-bus";
54                 ranges = <0x00000000 0x00000000 0x10000000>,
55                          <0x20000000 0x20000000 0x30000000>,
56                          <0xe0000000 0xe0000000 0x04000000>;
57
58                 iram: sram@8000000 {
59                         compatible = "mmio-sram";
60                         reg = <0x08000000 0x20000>;
61
62                         #address-cells = <1>;
63                         #size-cells = <1>;
64                         ranges = <0x00000000 0x08000000 0x20000>;
65                 };
66
67                 /*
68                  * Enable either SLC or MLC
69                  */
70                 slc: flash@20020000 {
71                         compatible = "nxp,lpc3220-slc";
72                         reg = <0x20020000 0x1000>;
73                         clocks = <&clk LPC32XX_CLK_SLC>;
74                         status = "disabled";
75                 };
76
77                 mlc: flash@200a8000 {
78                         compatible = "nxp,lpc3220-mlc";
79                         reg = <0x200a8000 0x11000>;
80                         interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
81                         clocks = <&clk LPC32XX_CLK_MLC>;
82                         status = "disabled";
83                 };
84
85                 dma: dma@31000000 {
86                         compatible = "arm,pl080", "arm,primecell";
87                         reg = <0x31000000 0x1000>;
88                         interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
89                         clocks = <&clk LPC32XX_CLK_DMA>;
90                         clock-names = "apb_pclk";
91                 };
92
93                 usb {
94                         #address-cells = <1>;
95                         #size-cells = <1>;
96                         compatible = "simple-bus";
97                         ranges = <0x0 0x31020000 0x00001000>;
98
99                         /*
100                          * Enable either ohci or usbd (gadget)!
101                          */
102                         ohci: ohci@0 {
103                                 compatible = "nxp,ohci-nxp", "usb-ohci";
104                                 reg = <0x0 0x300>;
105                                 interrupt-parent = <&sic1>;
106                                 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
107                                 clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
108                                 status = "disabled";
109                         };
110
111                         usbd: usbd@0 {
112                                 compatible = "nxp,lpc3220-udc";
113                                 reg = <0x0 0x300>;
114                                 interrupt-parent = <&sic1>;
115                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
116                                              <30 IRQ_TYPE_LEVEL_HIGH>,
117                                              <28 IRQ_TYPE_LEVEL_HIGH>,
118                                              <26 IRQ_TYPE_LEVEL_LOW>;
119                                 clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
120                                 status = "disabled";
121                         };
122
123                         i2cusb: i2c@300 {
124                                 compatible = "nxp,pnx-i2c";
125                                 reg = <0x300 0x100>;
126                                 interrupt-parent = <&sic1>;
127                                 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
128                                 clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
129                                 #address-cells = <1>;
130                                 #size-cells = <0>;
131                                 pnx,timeout = <0x64>;
132                         };
133
134                         usbclk: clock-controller@f00 {
135                                 compatible = "nxp,lpc3220-usb-clk";
136                                 reg = <0xf00 0x100>;
137                                 #clock-cells = <1>;
138                         };
139                 };
140
141                 clcd: clcd@31040000 {
142                         compatible = "arm,pl111", "arm,primecell";
143                         reg = <0x31040000 0x1000>;
144                         interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
145                         clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
146                         clock-names = "clcdclk", "apb_pclk";
147                         status = "disabled";
148                 };
149
150                 mac: ethernet@31060000 {
151                         compatible = "nxp,lpc-eth";
152                         reg = <0x31060000 0x1000>;
153                         interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
154                         clocks = <&clk LPC32XX_CLK_MAC>;
155                 };
156
157                 emc: memory-controller@31080000 {
158                         compatible = "arm,pl175", "arm,primecell";
159                         reg = <0x31080000 0x1000>;
160                         clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
161                         clock-names = "mpmcclk", "apb_pclk";
162                         #address-cells = <1>;
163                         #size-cells = <1>;
164
165                         ranges = <0 0xe0000000 0x01000000>,
166                                  <1 0xe1000000 0x01000000>,
167                                  <2 0xe2000000 0x01000000>,
168                                  <3 0xe3000000 0x01000000>;
169                         status = "disabled";
170                 };
171
172                 apb {
173                         #address-cells = <1>;
174                         #size-cells = <1>;
175                         compatible = "simple-bus";
176                         ranges = <0x20000000 0x20000000 0x30000000>;
177
178                         /*
179                          * ssp0 and spi1 are shared pins;
180                          * enable one in your board dts, as needed.
181                          */
182                         ssp0: spi@20084000 {
183                                 compatible = "arm,pl022", "arm,primecell";
184                                 reg = <0x20084000 0x1000>;
185                                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
186                                 clocks = <&clk LPC32XX_CLK_SSP0>;
187                                 clock-names = "apb_pclk";
188                                 status = "disabled";
189                         };
190
191                         spi1: spi@20088000 {
192                                 compatible = "nxp,lpc3220-spi";
193                                 reg = <0x20088000 0x1000>;
194                                 clocks = <&clk LPC32XX_CLK_SPI1>;
195                                 status = "disabled";
196                         };
197
198                         /*
199                          * ssp1 and spi2 are shared pins;
200                          * enable one in your board dts, as needed.
201                          */
202                         ssp1: spi@2008c000 {
203                                 compatible = "arm,pl022", "arm,primecell";
204                                 reg = <0x2008c000 0x1000>;
205                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
206                                 clocks = <&clk LPC32XX_CLK_SSP1>;
207                                 clock-names = "apb_pclk";
208                                 status = "disabled";
209                         };
210
211                         spi2: spi@20090000 {
212                                 compatible = "nxp,lpc3220-spi";
213                                 reg = <0x20090000 0x1000>;
214                                 clocks = <&clk LPC32XX_CLK_SPI2>;
215                                 status = "disabled";
216                         };
217
218                         i2s0: i2s@20094000 {
219                                 compatible = "nxp,lpc3220-i2s";
220                                 reg = <0x20094000 0x1000>;
221                         };
222
223                         sd: sd@20098000 {
224                                 compatible = "arm,pl18x", "arm,primecell";
225                                 reg = <0x20098000 0x1000>;
226                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
227                                              <13 IRQ_TYPE_LEVEL_HIGH>;
228                                 clocks = <&clk LPC32XX_CLK_SD>;
229                                 clock-names = "apb_pclk";
230                                 status = "disabled";
231                         };
232
233                         i2s1: i2s@2009c000 {
234                                 compatible = "nxp,lpc3220-i2s";
235                                 reg = <0x2009C000 0x1000>;
236                         };
237
238                         /* UART5 first since it is the default console, ttyS0 */
239                         uart5: serial@40090000 {
240                                 /* actually, ns16550a w/ 64 byte fifos! */
241                                 compatible = "nxp,lpc3220-uart";
242                                 reg = <0x40090000 0x1000>;
243                                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
244                                 reg-shift = <2>;
245                                 clocks = <&clk LPC32XX_CLK_UART5>;
246                                 status = "disabled";
247                         };
248
249                         uart3: serial@40080000 {
250                                 compatible = "nxp,lpc3220-uart";
251                                 reg = <0x40080000 0x1000>;
252                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
253                                 reg-shift = <2>;
254                                 clocks = <&clk LPC32XX_CLK_UART3>;
255                                 status = "disabled";
256                         };
257
258                         uart4: serial@40088000 {
259                                 compatible = "nxp,lpc3220-uart";
260                                 reg = <0x40088000 0x1000>;
261                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
262                                 reg-shift = <2>;
263                                 clocks = <&clk LPC32XX_CLK_UART4>;
264                                 status = "disabled";
265                         };
266
267                         uart6: serial@40098000 {
268                                 compatible = "nxp,lpc3220-uart";
269                                 reg = <0x40098000 0x1000>;
270                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
271                                 reg-shift = <2>;
272                                 clocks = <&clk LPC32XX_CLK_UART6>;
273                                 status = "disabled";
274                         };
275
276                         i2c1: i2c@400a0000 {
277                                 compatible = "nxp,pnx-i2c";
278                                 reg = <0x400A0000 0x100>;
279                                 interrupt-parent = <&sic1>;
280                                 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
281                                 #address-cells = <1>;
282                                 #size-cells = <0>;
283                                 pnx,timeout = <0x64>;
284                                 clocks = <&clk LPC32XX_CLK_I2C1>;
285                         };
286
287                         i2c2: i2c@400a8000 {
288                                 compatible = "nxp,pnx-i2c";
289                                 reg = <0x400A8000 0x100>;
290                                 interrupt-parent = <&sic1>;
291                                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
292                                 #address-cells = <1>;
293                                 #size-cells = <0>;
294                                 pnx,timeout = <0x64>;
295                                 clocks = <&clk LPC32XX_CLK_I2C2>;
296                         };
297
298                         mpwm: mpwm@400e8000 {
299                                 compatible = "nxp,lpc3220-motor-pwm";
300                                 reg = <0x400E8000 0x78>;
301                                 status = "disabled";
302                                 #pwm-cells = <2>;
303                         };
304                 };
305
306                 fab {
307                         #address-cells = <1>;
308                         #size-cells = <1>;
309                         compatible = "simple-bus";
310                         ranges = <0x20000000 0x20000000 0x30000000>;
311
312                         /* System Control Block */
313                         scb {
314                                 compatible = "simple-bus";
315                                 ranges = <0x0 0x040004000 0x00001000>;
316                                 #address-cells = <1>;
317                                 #size-cells = <1>;
318
319                                 clk: clock-controller@0 {
320                                         compatible = "nxp,lpc3220-clk";
321                                         reg = <0x00 0x114>;
322                                         #clock-cells = <1>;
323
324                                         clocks = <&xtal_32k>, <&xtal>;
325                                         clock-names = "xtal_32k", "xtal";
326                                 };
327                         };
328
329                         mic: interrupt-controller@40008000 {
330                                 compatible = "nxp,lpc3220-mic";
331                                 reg = <0x40008000 0x4000>;
332                                 interrupt-controller;
333                                 #interrupt-cells = <2>;
334                         };
335
336                         sic1: interrupt-controller@4000c000 {
337                                 compatible = "nxp,lpc3220-sic";
338                                 reg = <0x4000c000 0x4000>;
339                                 interrupt-controller;
340                                 #interrupt-cells = <2>;
341
342                                 interrupt-parent = <&mic>;
343                                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
344                                              <30 IRQ_TYPE_LEVEL_LOW>;
345                                 };
346
347                         sic2: interrupt-controller@40010000 {
348                                 compatible = "nxp,lpc3220-sic";
349                                 reg = <0x40010000 0x4000>;
350                                 interrupt-controller;
351                                 #interrupt-cells = <2>;
352
353                                 interrupt-parent = <&mic>;
354                                 interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
355                                              <31 IRQ_TYPE_LEVEL_LOW>;
356                         };
357
358                         uart1: serial@40014000 {
359                                 compatible = "nxp,lpc3220-hsuart";
360                                 reg = <0x40014000 0x1000>;
361                                 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
362                                 status = "disabled";
363                         };
364
365                         uart2: serial@40018000 {
366                                 compatible = "nxp,lpc3220-hsuart";
367                                 reg = <0x40018000 0x1000>;
368                                 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
369                                 status = "disabled";
370                         };
371
372                         uart7: serial@4001c000 {
373                                 compatible = "nxp,lpc3220-hsuart";
374                                 reg = <0x4001c000 0x1000>;
375                                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
376                                 status = "disabled";
377                         };
378
379                         rtc: rtc@40024000 {
380                                 compatible = "nxp,lpc3220-rtc";
381                                 reg = <0x40024000 0x1000>;
382                                 interrupt-parent = <&sic1>;
383                                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
384                                 clocks = <&clk LPC32XX_CLK_RTC>;
385                         };
386
387                         gpio: gpio@40028000 {
388                                 compatible = "nxp,lpc3220-gpio";
389                                 reg = <0x40028000 0x1000>;
390                                 gpio-controller;
391                                 #gpio-cells = <3>; /* bank, pin, flags */
392                         };
393
394                         timer4: timer@4002c000 {
395                                 compatible = "nxp,lpc3220-timer";
396                                 reg = <0x4002C000 0x1000>;
397                                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
398                                 clocks = <&clk LPC32XX_CLK_TIMER4>;
399                                 clock-names = "timerclk";
400                                 status = "disabled";
401                         };
402
403                         timer5: timer@40030000 {
404                                 compatible = "nxp,lpc3220-timer";
405                                 reg = <0x40030000 0x1000>;
406                                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
407                                 clocks = <&clk LPC32XX_CLK_TIMER5>;
408                                 clock-names = "timerclk";
409                                 status = "disabled";
410                         };
411
412                         watchdog: watchdog@4003c000 {
413                                 compatible = "nxp,pnx4008-wdt";
414                                 reg = <0x4003C000 0x1000>;
415                                 clocks = <&clk LPC32XX_CLK_WDOG>;
416                         };
417
418                         timer0: timer@40044000 {
419                                 compatible = "nxp,lpc3220-timer";
420                                 reg = <0x40044000 0x1000>;
421                                 clocks = <&clk LPC32XX_CLK_TIMER0>;
422                                 clock-names = "timerclk";
423                                 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
424                         };
425
426                         /*
427                          * TSC vs. ADC: Since those two share the same
428                          * hardware, you need to choose from one of the
429                          * following two and do 'status = "okay";' for one of
430                          * them
431                          */
432
433                         adc: adc@40048000 {
434                                 compatible = "nxp,lpc3220-adc";
435                                 reg = <0x40048000 0x1000>;
436                                 interrupt-parent = <&sic1>;
437                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
438                                 clocks = <&clk LPC32XX_CLK_ADC>;
439                                 status = "disabled";
440                         };
441
442                         tsc: tsc@40048000 {
443                                 compatible = "nxp,lpc3220-tsc";
444                                 reg = <0x40048000 0x1000>;
445                                 interrupt-parent = <&sic1>;
446                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
447                                 clocks = <&clk LPC32XX_CLK_ADC>;
448                                 status = "disabled";
449                         };
450
451                         timer1: timer@4004c000 {
452                                 compatible = "nxp,lpc3220-timer";
453                                 reg = <0x4004C000 0x1000>;
454                                 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
455                                 clocks = <&clk LPC32XX_CLK_TIMER1>;
456                                 clock-names = "timerclk";
457                         };
458
459                         key: key@40050000 {
460                                 compatible = "nxp,lpc3220-key";
461                                 reg = <0x40050000 0x1000>;
462                                 clocks = <&clk LPC32XX_CLK_KEY>;
463                                 interrupt-parent = <&sic1>;
464                                 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
465                                 status = "disabled";
466                         };
467
468                         timer2: timer@40058000 {
469                                 compatible = "nxp,lpc3220-timer";
470                                 reg = <0x40058000 0x1000>;
471                                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
472                                 clocks = <&clk LPC32XX_CLK_TIMER2>;
473                                 clock-names = "timerclk";
474                                 status = "disabled";
475                         };
476
477                         pwm1: pwm@4005c000 {
478                                 compatible = "nxp,lpc3220-pwm";
479                                 reg = <0x4005C000 0x4>;
480                                 clocks = <&clk LPC32XX_CLK_PWM1>;
481                                 assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
482                                 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
483                                 status = "disabled";
484                         };
485
486                         pwm2: pwm@4005c004 {
487                                 compatible = "nxp,lpc3220-pwm";
488                                 reg = <0x4005C004 0x4>;
489                                 clocks = <&clk LPC32XX_CLK_PWM2>;
490                                 assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
491                                 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
492                                 status = "disabled";
493                         };
494
495                         timer3: timer@40060000 {
496                                 compatible = "nxp,lpc3220-timer";
497                                 reg = <0x40060000 0x1000>;
498                                 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
499                                 clocks = <&clk LPC32XX_CLK_TIMER3>;
500                                 clock-names = "timerclk";
501                                 status = "disabled";
502                         };
503                 };
504         };
505 };