1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
5 * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
7 * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
19 model = "Microchip LAN966 family SoC";
20 compatible = "microchip,lan966";
21 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a7";
32 clock-frequency = <600000000>;
39 compatible = "fixed-clock";
41 clock-frequency = <165625000>;
45 compatible = "fixed-clock";
47 clock-frequency = <600000000>;
51 compatible = "fixed-clock";
53 clock-frequency = <300000000>;
57 compatible = "fixed-clock";
59 clock-frequency = <200000000>;
63 clks: clock-controller@e00c00a8 {
64 compatible = "microchip,lan966x-gck";
66 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
67 clock-names = "cpu", "ddr", "sys";
68 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
72 compatible = "arm,armv7-timer";
73 interrupt-parent = <&gic>;
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <37500000>;
82 compatible = "simple-bus";
88 compatible = "microchip,lan9662-udc",
90 reg = <0x00200000 0x80000>,
92 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
93 clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>;
94 clock-names = "pclk", "hclk";
98 switch: switch@e0000000 {
99 compatible = "microchip,lan966x-switch";
100 reg = <0xe0000000 0x0100000>,
101 <0xe2000000 0x0800000>;
102 reg-names = "cpu", "gcb";
103 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "xtr", "fdma", "ana", "ptp",
111 reset-names = "switch";
115 #address-cells = <1>;
160 flx0: flexcom@e0040000 {
161 compatible = "atmel,sama5d2-flexcom";
162 reg = <0xe0040000 0x100>;
163 clocks = <&clks GCK_ID_FLEXCOM0>;
164 #address-cells = <1>;
166 ranges = <0x0 0xe0040000 0x800>;
170 compatible = "atmel,at91sam9260-usart";
172 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
173 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
174 <&dma0 AT91_XDMAC_DT_PERID(2)>;
175 dma-names = "tx", "rx";
177 clock-names = "usart";
178 atmel,fifo-size = <32>;
183 compatible = "atmel,at91rm9200-spi";
185 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
186 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
187 <&dma0 AT91_XDMAC_DT_PERID(2)>;
188 dma-names = "tx", "rx";
190 clock-names = "spi_clk";
191 atmel,fifo-size = <32>;
192 #address-cells = <1>;
198 compatible = "microchip,sam9x60-i2c";
200 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
201 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
202 <&dma0 AT91_XDMAC_DT_PERID(2)>;
203 dma-names = "tx", "rx";
205 #address-cells = <1>;
211 flx1: flexcom@e0044000 {
212 compatible = "atmel,sama5d2-flexcom";
213 reg = <0xe0044000 0x100>;
214 clocks = <&clks GCK_ID_FLEXCOM1>;
215 #address-cells = <1>;
217 ranges = <0x0 0xe0044000 0x800>;
221 compatible = "atmel,at91sam9260-usart";
223 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
224 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
225 <&dma0 AT91_XDMAC_DT_PERID(4)>;
226 dma-names = "tx", "rx";
228 clock-names = "usart";
229 atmel,fifo-size = <32>;
234 compatible = "atmel,at91rm9200-spi";
236 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
237 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
238 <&dma0 AT91_XDMAC_DT_PERID(4)>;
239 dma-names = "tx", "rx";
241 clock-names = "spi_clk";
242 atmel,fifo-size = <32>;
243 #address-cells = <1>;
249 compatible = "microchip,sam9x60-i2c";
251 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
252 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
253 <&dma0 AT91_XDMAC_DT_PERID(4)>;
254 dma-names = "tx", "rx";
256 #address-cells = <1>;
263 compatible = "atmel,at91sam9g45-trng";
264 reg = <0xe0048000 0x100>;
268 aes: crypto@e004c000 {
269 compatible = "atmel,at91sam9g46-aes";
270 reg = <0xe004c000 0x100>;
271 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
272 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
273 <&dma0 AT91_XDMAC_DT_PERID(13)>;
274 dma-names = "tx", "rx";
276 clock-names = "aes_clk";
279 flx2: flexcom@e0060000 {
280 compatible = "atmel,sama5d2-flexcom";
281 reg = <0xe0060000 0x100>;
282 clocks = <&clks GCK_ID_FLEXCOM2>;
283 #address-cells = <1>;
285 ranges = <0x0 0xe0060000 0x800>;
289 compatible = "atmel,at91sam9260-usart";
291 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
292 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
293 <&dma0 AT91_XDMAC_DT_PERID(6)>;
294 dma-names = "tx", "rx";
296 clock-names = "usart";
297 atmel,fifo-size = <32>;
302 compatible = "atmel,at91rm9200-spi";
304 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
305 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
306 <&dma0 AT91_XDMAC_DT_PERID(6)>;
307 dma-names = "tx", "rx";
309 clock-names = "spi_clk";
310 atmel,fifo-size = <32>;
311 #address-cells = <1>;
317 compatible = "microchip,sam9x60-i2c";
319 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
320 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
321 <&dma0 AT91_XDMAC_DT_PERID(6)>;
322 dma-names = "tx", "rx";
324 #address-cells = <1>;
330 flx3: flexcom@e0064000 {
331 compatible = "atmel,sama5d2-flexcom";
332 reg = <0xe0064000 0x100>;
333 clocks = <&clks GCK_ID_FLEXCOM3>;
334 #address-cells = <1>;
336 ranges = <0x0 0xe0064000 0x800>;
340 compatible = "atmel,at91sam9260-usart";
342 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
343 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
344 <&dma0 AT91_XDMAC_DT_PERID(8)>;
345 dma-names = "tx", "rx";
347 clock-names = "usart";
348 atmel,fifo-size = <32>;
353 compatible = "atmel,at91rm9200-spi";
355 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
356 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
357 <&dma0 AT91_XDMAC_DT_PERID(8)>;
358 dma-names = "tx", "rx";
360 clock-names = "spi_clk";
361 atmel,fifo-size = <32>;
362 #address-cells = <1>;
368 compatible = "microchip,sam9x60-i2c";
370 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
371 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
372 <&dma0 AT91_XDMAC_DT_PERID(8)>;
373 dma-names = "tx", "rx";
375 #address-cells = <1>;
381 dma0: dma-controller@e0068000 {
382 compatible = "microchip,sama7g5-dma";
383 reg = <0xe0068000 0x1000>;
384 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
387 clock-names = "dma_clk";
390 sha: crypto@e006c000 {
391 compatible = "atmel,at91sam9g46-sha";
392 reg = <0xe006c000 0xec>;
393 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
397 clock-names = "sha_clk";
400 flx4: flexcom@e0070000 {
401 compatible = "atmel,sama5d2-flexcom";
402 reg = <0xe0070000 0x100>;
403 clocks = <&clks GCK_ID_FLEXCOM4>;
404 #address-cells = <1>;
406 ranges = <0x0 0xe0070000 0x800>;
410 compatible = "atmel,at91sam9260-usart";
412 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
413 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
414 <&dma0 AT91_XDMAC_DT_PERID(10)>;
415 dma-names = "tx", "rx";
417 clock-names = "usart";
418 atmel,fifo-size = <32>;
423 compatible = "atmel,at91rm9200-spi";
425 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
427 <&dma0 AT91_XDMAC_DT_PERID(10)>;
428 dma-names = "tx", "rx";
430 clock-names = "spi_clk";
431 atmel,fifo-size = <32>;
432 #address-cells = <1>;
438 compatible = "microchip,sam9x60-i2c";
440 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
441 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
442 <&dma0 AT91_XDMAC_DT_PERID(10)>;
443 dma-names = "tx", "rx";
445 #address-cells = <1>;
451 timer0: timer@e008c000 {
452 compatible = "snps,dw-apb-timer";
453 reg = <0xe008c000 0x400>;
455 clock-names = "timer";
456 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
459 watchdog: watchdog@e0090000 {
460 compatible = "snps,dw-wdt";
461 reg = <0xe0090000 0x1000>;
462 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
467 cpu_ctrl: syscon@e00c0000 {
468 compatible = "microchip,lan966x-cpu-syscon", "syscon";
469 reg = <0xe00c0000 0x350>;
473 compatible = "bosch,m_can";
474 reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
475 reg-names = "m_can", "message_ram";
476 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
478 interrupt-names = "int0", "int1";
479 clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
480 clock-names = "hclk", "cclk";
481 assigned-clocks = <&clks GCK_ID_MCAN0>;
482 assigned-clock-rates = <40000000>;
483 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
488 compatible = "bosch,m_can";
489 reg = <0xe0820000 0xfc>, <0x00100000 0x8000>;
490 reg-names = "m_can", "message_ram";
491 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-names = "int0", "int1";
494 clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>;
495 clock-names = "hclk", "cclk";
496 assigned-clocks = <&clks GCK_ID_MCAN1>;
497 assigned-clock-rates = <40000000>;
498 bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>;
502 reset: reset-controller@e200400c {
503 compatible = "microchip,lan966x-switch-reset";
504 reg = <0xe200400c 0x4>;
507 cpu-syscon = <&cpu_ctrl>;
510 gpio: pinctrl@e2004064 {
511 compatible = "microchip,lan966x-pinctrl";
512 reg = <0xe2004064 0xb4>,
515 reset-names = "switch";
518 gpio-ranges = <&gpio 0 0 78>;
519 interrupt-controller;
520 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
521 #interrupt-cells = <2>;
524 mdio0: mdio@e2004118 {
525 compatible = "microchip,lan966x-miim";
526 #address-cells = <1>;
528 reg = <0xe2004118 0x24>;
533 mdio1: mdio@e200413c {
534 compatible = "microchip,lan966x-miim";
535 #address-cells = <1>;
537 reg = <0xe200413c 0x24>,
542 phy0: ethernet-phy@1 {
544 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
548 phy1: ethernet-phy@2 {
550 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
555 sgpio: gpio@e2004190 {
556 compatible = "microchip,sparx5-sgpio";
557 reg = <0xe2004190 0x118>;
560 reset-names = "switch";
561 #address-cells = <1>;
566 compatible = "microchip,sparx5-sgpio-bank";
570 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
571 interrupt-controller;
572 #interrupt-cells = <3>;
576 compatible = "microchip,sparx5-sgpio-bank";
583 hwmon: hwmon@e2010180 {
584 compatible = "microchip,lan9668-hwmon";
585 reg = <0xe2010180 0xc>,
587 reg-names = "pvt", "fan";
591 serdes: serdes@e202c000 {
592 compatible = "microchip,lan966x-serdes";
593 reg = <0xe202c000 0x9c>,
599 gic: interrupt-controller@e8c11000 {
600 compatible = "arm,gic-400", "arm,cortex-a7-gic";
601 #interrupt-cells = <3>;
602 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
603 interrupt-controller;
604 reg = <0xe8c11000 0x1000>,