1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "marvell,kirkwood-pcie";
12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
25 #interrupt-cells = <1>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
29 interrupt-names = "intx", "error";
30 interrupts = <9>, <44>;
31 interrupt-map-mask = <0 0 0 7>;
32 interrupt-map = <0 0 0 1 &pcie_intc 0>,
33 <0 0 0 2 &pcie_intc 1>,
34 <0 0 0 3 &pcie_intc 2>,
35 <0 0 0 4 &pcie_intc 3>;
36 marvell,pcie-port = <0>;
37 marvell,pcie-lane = <0>;
38 clocks = <&gate_clk 2>;
41 pcie_intc: interrupt-controller {
43 #interrupt-cells = <1>;
50 pinctrl: pin-controller@10000 {
51 compatible = "marvell,88f6281-pinctrl";
53 pmx_sata0: pmx-sata0 {
54 marvell,pins = "mpp5", "mpp21", "mpp23";
55 marvell,function = "sata0";
57 pmx_sata1: pmx-sata1 {
58 marvell,pins = "mpp4", "mpp20", "mpp22";
59 marvell,function = "sata1";
62 marvell,pins = "mpp12", "mpp13", "mpp14",
63 "mpp15", "mpp16", "mpp17";
64 marvell,function = "sdio";
69 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
72 clocks = <&gate_clk 7>;
76 compatible = "marvell,orion-sata";
77 reg = <0x80000 0x5000>;
79 clocks = <&gate_clk 14>, <&gate_clk 15>;
80 clock-names = "0", "1";
81 phys = <&sata_phy0>, <&sata_phy1>;
82 phy-names = "port0", "port1";
87 compatible = "marvell,orion-sdio";
88 reg = <0x90000 0x200>;
90 clocks = <&gate_clk 4>;
91 pinctrl-0 = <&pmx_sdio>;
92 pinctrl-names = "default";