1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "marvell,kirkwood-pcie";
12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
25 #interrupt-cells = <1>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &intc 9>;
31 marvell,pcie-port = <0>;
32 marvell,pcie-lane = <0>;
33 clocks = <&gate_clk 2>;
40 pinctrl: pin-controller@10000 {
41 compatible = "marvell,88f6281-pinctrl";
43 pmx_sata0: pmx-sata0 {
44 marvell,pins = "mpp5", "mpp21", "mpp23";
45 marvell,function = "sata0";
47 pmx_sata1: pmx-sata1 {
48 marvell,pins = "mpp4", "mpp20", "mpp22";
49 marvell,function = "sata1";
52 marvell,pins = "mpp12", "mpp13", "mpp14",
53 "mpp15", "mpp16", "mpp17";
54 marvell,function = "sdio";
59 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
62 clocks = <&gate_clk 7>;
66 compatible = "marvell,orion-sata";
67 reg = <0x80000 0x5000>;
69 clocks = <&gate_clk 14>, <&gate_clk 15>;
70 clock-names = "0", "1";
71 phys = <&sata_phy0>, <&sata_phy1>;
72 phy-names = "port0", "port1";
77 compatible = "marvell,orion-sdio";
78 reg = <0x90000 0x200>;
80 clocks = <&gate_clk 4>;
81 pinctrl-0 = <&pmx_sdio>;
82 pinctrl-names = "default";