3 pciec: pcie-controller@82000000 {
4 compatible = "marvell,kirkwood-pcie";
11 bus-range = <0x00 0xff>;
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
16 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
20 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
21 reg = <0x0800 0 0 0 0>;
24 #interrupt-cells = <1>;
25 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
26 0x81000000 0 0 0x81000000 0x1 0 1 0>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &intc 9>;
29 marvell,pcie-port = <0>;
30 marvell,pcie-lane = <0>;
31 clocks = <&gate_clk 2>;
38 pinctrl: pin-controller@10000 {
39 compatible = "marvell,88f6281-pinctrl";
41 pmx_sata0: pmx-sata0 {
42 marvell,pins = "mpp5", "mpp21", "mpp23";
43 marvell,function = "sata0";
45 pmx_sata1: pmx-sata1 {
46 marvell,pins = "mpp4", "mpp20", "mpp22";
47 marvell,function = "sata1";
50 marvell,pins = "mpp12", "mpp13", "mpp14",
51 "mpp15", "mpp16", "mpp17";
52 marvell,function = "sdio";
57 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
60 clocks = <&gate_clk 7>;
64 compatible = "marvell,orion-sata";
65 reg = <0x80000 0x5000>;
67 clocks = <&gate_clk 14>, <&gate_clk 15>;
68 clock-names = "0", "1";
69 phys = <&sata_phy0>, <&sata_phy1>;
70 phy-names = "port0", "port1";
75 compatible = "marvell,orion-sdio";
76 reg = <0x90000 0x200>;
78 clocks = <&gate_clk 4>;
79 pinctrl-0 = <&pmx_sdio>;
80 pinctrl-names = "default";