arch/arm/boot/dts/keystone.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8
   9 / {
  10         compatible = "ti,keystone";
  11         model = "Texas Instruments Keystone 2 SoC";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 spi0 = &spi0;
  19                 spi1 = &spi1;
  20                 spi2 = &spi2;
  21         };
  22
  23         chosen { };
  24
  25         memory: memory@80000000 {
  26                 device_type = "memory";
  27                 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
  28         };
  29
  30         gic: interrupt-controller@2561000 {
  31                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  32                 #interrupt-cells = <3>;
  33                 interrupt-controller;
  34                 reg = <0x0 0x02561000 0x0 0x1000>,
  35                       <0x0 0x02562000 0x0 0x2000>,
  36                       <0x0 0x02564000 0x0 0x2000>,
  37                       <0x0 0x02566000 0x0 0x2000>;
  38                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
  39                                 IRQ_TYPE_LEVEL_HIGH)>;
  40         };
  41
  42         timer {
  43                 compatible = "arm,armv7-timer";
  44                 interrupts =
  45                         <GIC_PPI 13
  46                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  47                         <GIC_PPI 14
  48                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  49                         <GIC_PPI 11
  50                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  51                         <GIC_PPI 10
  52                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  53         };
  54
  55         pmu {
  56                 compatible = "arm,cortex-a15-pmu";
  57                 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
  58                              <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
  59                              <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
  60                              <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
  61         };
  62
  63         psci {
  64                 compatible      = "arm,psci";
  65                 method          = "smc";
  66                 cpu_suspend     = <0x84000001>;
  67                 cpu_off         = <0x84000002>;
  68                 cpu_on          = <0x84000003>;
  69         };
  70
  71         soc0: soc@0 {
  72                 #address-cells = <1>;
  73                 #size-cells = <1>;
  74                 compatible = "ti,keystone","simple-bus";
  75                 interrupt-parent = <&gic>;
  76                 ranges = <0x0 0x0 0x0 0xc0000000>;
  77                 dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
  78
  79                 pllctrl: pll-controller@2310000 {
  80                         compatible = "ti,keystone-pllctrl", "syscon";
  81                         reg = <0x02310000 0x200>;
  82                 };
  83
  84                 psc: power-sleep-controller@2350000 {
  85                         compatible = "syscon", "simple-mfd";
  86                         reg = <0x02350000 0x1000>;
  87                 };
  88
  89                 devctrl: device-state-control@2620000 {
  90                         compatible = "ti,keystone-devctrl", "syscon", "simple-mfd";
  91                         reg = <0x02620000 0x1000>;
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         ranges = <0x0 0x02620000 0x1000>;
  95
  96                         kirq0: keystone_irq@2a0 {
  97                                 compatible = "ti,keystone-irq";
  98                                 reg = <0x2a0 0x4>;
  99                                 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
 100                                 interrupt-controller;
 101                                 #interrupt-cells = <1>;
 102                                 ti,syscon-dev = <&devctrl 0x2a0>;
 103                         };
 104
 105                         rstctrl: reset-controller@328 {
 106                                 compatible = "ti,keystone-reset";
 107                                 reg = <0x328 0x10>;
 108                                 ti,syscon-pll = <&pllctrl 0xe4>;
 109                                 ti,syscon-dev = <&devctrl 0x328>;
 110                                 ti,wdt-list = <0>;
 111                         };
 112                 };
 113
 114                 /include/ "keystone-clocks.dtsi"
 115
 116                 uart0: serial@2530c00 {
 117                         compatible = "ti,da830-uart", "ns16550a";
 118                         current-speed = <115200>;
 119                         reg-shift = <2>;
 120                         reg-io-width = <4>;
 121                         reg = <0x02530c00 0x100>;
 122                         clocks  = <&clkuart0>;
 123                         interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
 124                 };
 125
 126                 uart1:  serial@2531000 {
 127                         compatible = "ti,da830-uart", "ns16550a";
 128                         current-speed = <115200>;
 129                         reg-shift = <2>;
 130                         reg-io-width = <4>;
 131                         reg = <0x02531000 0x100>;
 132                         clocks  = <&clkuart1>;
 133                         interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
 134                 };
 135
 136                 i2c0: i2c@2530000 {
 137                         compatible = "ti,davinci-i2c";
 138                         reg = <0x02530000 0x400>;
 139                         clock-frequency = <100000>;
 140                         clocks = <&clki2c>;
 141                         interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                 };
 145
 146                 i2c1: i2c@2530400 {
 147                         compatible = "ti,davinci-i2c";
 148                         reg = <0x02530400 0x400>;
 149                         clock-frequency = <100000>;
 150                         clocks = <&clki2c>;
 151                         interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                 };
 155
 156                 i2c2: i2c@2530800 {
 157                         compatible = "ti,davinci-i2c";
 158                         reg = <0x02530800 0x400>;
 159                         clock-frequency = <100000>;
 160                         clocks = <&clki2c>;
 161                         interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                 };
 165
 166                 spi0: spi@21000400 {
 167                         compatible = "ti,keystone-spi", "ti,dm6441-spi";
 168                         reg = <0x21000400 0x200>;
 169                         num-cs = <4>;
 170                         ti,davinci-spi-intr-line = <0>;
 171                         interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
 172                         clocks = <&clkspi>;
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                 };
 176
 177                 spi1: spi@21000600 {
 178                         compatible = "ti,keystone-spi", "ti,dm6441-spi";
 179                         reg = <0x21000600 0x200>;
 180                         num-cs = <4>;
 181                         ti,davinci-spi-intr-line = <0>;
 182                         interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
 183                         clocks = <&clkspi>;
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                 };
 187
 188                 spi2: spi@21000800 {
 189                         compatible = "ti,keystone-spi", "ti,dm6441-spi";
 190                         reg = <0x21000800 0x200>;
 191                         num-cs = <4>;
 192                         ti,davinci-spi-intr-line = <0>;
 193                         interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
 194                         clocks = <&clkspi>;
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                 };
 198
 199                 usb_phy: usb_phy@2620738 {
 200                         compatible = "ti,keystone-usbphy";
 201                         #address-cells = <1>;
 202                         #size-cells = <1>;
 203                         reg = <0x2620738 24>;
 204                         status = "disabled";
 205                 };
 206
 207                 keystone_usb0: usb@2680000 {
 208                         compatible = "ti,keystone-dwc3";
 209                         #address-cells = <1>;
 210                         #size-cells = <1>;
 211                         reg = <0x2680000 0x10000>;
 212                         clocks = <&clkusb>;
 213                         clock-names = "usb";
 214                         interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
 215                         ranges;
 216                         dma-coherent;
 217                         dma-ranges;
 218                         status = "disabled";
 219
 220                         usb0: dwc3@2690000 {
 221                                 compatible = "synopsys,dwc3";
 222                                 reg = <0x2690000 0x70000>;
 223                                 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
 224                                 usb-phy = <&usb_phy>, <&usb_phy>;
 225                         };
 226                 };
 227
 228                 wdt: wdt@22f0080 {
 229                         compatible = "ti,keystone-wdt","ti,davinci-wdt";
 230                         reg = <0x022f0080 0x80>;
 231                         clocks = <&clkwdtimer0>;
 232                 };
 233
 234                 clock_event: timer@22f0000 {
 235                         compatible = "ti,keystone-timer";
 236                         reg = <0x022f0000 0x80>;
 237                         interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
 238                         clocks = <&clktimer15>;
 239                 };
 240
 241                 gpio0: gpio@260bf00 {
 242                         compatible = "ti,keystone-gpio";
 243                         reg = <0x0260bf00 0x100>;
 244                         gpio-controller;
 245                         #gpio-cells = <2>;
 246                         /* HW Interrupts mapped to GPIO pins */
 247                         interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
 248                                         <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
 249                                         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
 250                                         <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
 251                                         <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
 252                                         <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
 253                                         <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
 254                                         <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
 255                                         <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
 256                                         <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
 257                                         <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
 258                                         <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
 259                                         <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
 260                                         <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
 261                                         <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
 262                                         <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
 263                                         <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 264                                         <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
 265                                         <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
 266                                         <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
 267                                         <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
 268                                         <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
 269                                         <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
 270                                         <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
 271                                         <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
 272                                         <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
 273                                         <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
 274                                         <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
 275                                         <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
 276                                         <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
 277                                         <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
 278                                         <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
 279                         clocks = <&clkgpio>;
 280                         clock-names = "gpio";
 281                         ti,ngpio = <32>;
 282                         ti,davinci-gpio-unbanked = <32>;
 283                 };
 284
 285                 aemif: aemif@21000A00 {
 286                         compatible = "ti,keystone-aemif", "ti,davinci-aemif";
 287                         #address-cells = <2>;
 288                         #size-cells = <1>;
 289                         clocks = <&clkaemif>;
 290                         clock-names = "aemif";
 291                         clock-ranges;
 292
 293                         reg = <0x21000A00 0x00000100>;
 294                         ranges = <0 0 0x30000000 0x10000000
 295                                   1 0 0x21000A00 0x00000100>;
 296                 };
 297
 298                 pcie0: pcie@21800000 {
 299                         compatible = "ti,keystone-pcie", "snps,dw-pcie";
 300                         clocks = <&clkpcie>;
 301                         clock-names = "pcie";
 302                         #address-cells = <3>;
 303                         #size-cells = <2>;
 304                         reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
 305                         ranges = <0x82000000 0 0x50000000 0x50000000
 306                                   0 0x10000000>;
 307
 308                         status = "disabled";
 309                         device_type = "pci";
 310                         num-lanes = <2>;
 311                         bus-range = <0x00 0xff>;
 312
 313                         /* error interrupt */
 314                         interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
 315                         #interrupt-cells = <1>;
 316                         interrupt-map-mask = <0 0 0 7>;
 317                         interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
 318                                         <0 0 0 2 &pcie_intc0 1>, /* INT B */
 319                                         <0 0 0 3 &pcie_intc0 2>, /* INT C */
 320                                         <0 0 0 4 &pcie_intc0 3>; /* INT D */
 321
 322                         pcie_msi_intc0: msi-interrupt-controller {
 323                                 interrupt-controller;
 324                                 #interrupt-cells = <1>;
 325                                 interrupt-parent = <&gic>;
 326                                 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
 327                                         <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
 328                                         <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
 329                                         <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
 330                                         <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 331                                         <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 332                                         <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 333                                         <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
 334                         };
 335
 336                         pcie_intc0: legacy-interrupt-controller {
 337                                 interrupt-controller;
 338                                 #interrupt-cells = <1>;
 339                                 interrupt-parent = <&gic>;
 340                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
 341                                         <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
 342                                         <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
 343                                         <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
 344                         };
 345                 };
 346
 347                 emif: emif@21010000 {
 348                         compatible = "ti,emif-keystone";
 349                         reg = <0x21010000 0x200>;
 350                         interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
 351                         interrupt-parent = <&gic>;
 352                 };
 353         };
 354 };