arch/arm/boot/dts/integratorap.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree for the ARM Integrator/AP platform
   4  */
   5
   6 /dts-v1/;
   7 #include "integrator.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10
  11 / {
  12         model = "ARM Integrator/AP";
  13         compatible = "arm,integrator-ap";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         /*
  22                          * Since the board has pluggable CPU modules, we
  23                          * cannot define a proper compatible here. Let the
  24                          * boot loader fill in the apropriate compatible
  25                          * string if necessary.
  26                          */
  27                         /* compatible = "arm,arm926ej-s"; */
  28                         reg = <0>;
  29                         /*
  30                          * The documentation in ARM DUI 0138E page 3-12 states
  31                          * that the maximum frequency for this clock is 200 MHz
  32                          * but painful trial-and-error has proved to me that it
  33                          * is actually just hanging the system above 71 MHz.
  34                          * Sad but true.
  35                          */
  36                                          /* kHz     uV   */
  37                         operating-points = <71000  0
  38                                             66000  0
  39                                             60000  0
  40                                             48000  0
  41                                             36000  0
  42                                             24000  0
  43                                             12000  0>;
  44                         clocks = <&cmosc>;
  45                         clock-names = "cpu";
  46                         clock-latency = <1000000>; /* 1 ms */
  47                 };
  48         };
  49
  50         aliases {
  51                 arm,timer-primary = &timer2;
  52                 arm,timer-secondary = &timer1;
  53         };
  54
  55         chosen {
  56                 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
  57         };
  58
  59         /* 24 MHz chrystal on the Integrator/AP development board */
  60         xtal24mhz: xtal24mhz@24M {
  61                 #clock-cells = <0>;
  62                 compatible = "fixed-clock";
  63                 clock-frequency = <24000000>;
  64         };
  65
  66         pclk: pclk@0 {
  67                 #clock-cells = <0>;
  68                 compatible = "fixed-factor-clock";
  69                 clock-div = <1>;
  70                 clock-mult = <1>;
  71                 clocks = <&xtal24mhz>;
  72         };
  73
  74         /* The UART clock is 14.74 MHz divided by an ICS525 */
  75         uartclk: uartclk@14.74M {
  76                 #clock-cells = <0>;
  77                 compatible = "fixed-clock";
  78                 clock-frequency = <14745600>;
  79                 clocks = <&xtal24mhz>;
  80         };
  81
  82         core-module@10000000 {
  83                 /* 24 MHz chrystal on the core module */
  84                 cm24mhz: cm24mhz@24M {
  85                         #clock-cells = <0>;
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <24000000>;
  88                 };
  89
  90                 /* Oscillator on the core module, clocks the CPU core */
  91                 cmosc: clock-controller@8 {
  92                         compatible = "arm,syscon-icst525-integratorap-cm";
  93                         reg = <0x08 0x04>;
  94                         #clock-cells = <0>;
  95                         lock-offset = <0x14>;
  96                         vco-offset = <0x08>;
  97                         clocks = <&cm24mhz>;
  98                 };
  99
 100                 /* Auxilary oscillator on the core module, 32.369MHz at boot */
 101                 auxosc: clock-controller@1c {
 102                         compatible = "arm,syscon-icst525";
 103                         reg = <0x1c 0x04>;
 104                         #clock-cells = <0>;
 105                         lock-offset = <0x14>;
 106                         vco-offset = <0x1c>;
 107                         clocks = <&cm24mhz>;
 108                 };
 109         };
 110
 111         syscon {
 112                 compatible = "arm,integrator-ap-syscon", "syscon";
 113                 reg = <0x11000000 0x100>;
 114                 ranges = <0x0 0x11000000 0x100>;
 115                 #size-cells = <1>;
 116                 #address-cells = <1>;
 117
 118                 /*
 119                  * SYSCLK clocks PCIv3 bridge, system controller and the
 120                  * logic modules.
 121                  */
 122                 sysclk: clock-controller@4 {
 123                         compatible = "arm,syscon-icst525-integratorap-sys";
 124                         reg = <0x04 0x04>;
 125                         #clock-cells = <0>;
 126                         lock-offset = <0x1c>;
 127                         vco-offset = <0x04>;
 128                         clocks = <&xtal24mhz>;
 129                 };
 130
 131                 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
 132                 pciclk: clock-controller@4,8 {
 133                         compatible = "arm,syscon-icst525-integratorap-pci";
 134                         reg = <0x04 0x04>;
 135                         #clock-cells = <0>;
 136                         lock-offset = <0x1c>;
 137                         vco-offset = <0x04>;
 138                         clocks = <&xtal24mhz>;
 139                 };
 140         };
 141
 142         timer0: timer@13000000 {
 143                 compatible = "arm,integrator-timer";
 144                 clocks = <&xtal24mhz>;
 145         };
 146
 147         timer1: timer@13000100 {
 148                 compatible = "arm,integrator-timer";
 149                 clocks = <&xtal24mhz>;
 150         };
 151
 152         timer2: timer@13000200 {
 153                 compatible = "arm,integrator-timer";
 154                 clocks = <&xtal24mhz>;
 155         };
 156
 157         pic: pic@14000000 {
 158                 valid-mask = <0x003fffff>;
 159         };
 160
 161         pci: pciv3@62000000 {
 162                 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
 163                 #interrupt-cells = <1>;
 164                 #size-cells = <2>;
 165                 #address-cells = <3>;
 166                 /* Bridge registers and config access space */
 167                 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
 168                 interrupt-parent = <&pic>;
 169                 interrupts = <17>; /* Bus error IRQ */
 170                 clocks = <&pciclk>;
 171                 bus-range = <0x00 0xff>;
 172                 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
 173                         0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
 174                         0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
 175                         0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
 176                         0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
 177                         0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
 178                 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
 179                         0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
 180                         0x02000000 0 0x80000000 /* Core module alias memory */
 181                         0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
 182                 interrupt-map-mask = <0xf800 0 0 0x7>;
 183                 interrupt-map = <
 184                 /* IDSEL 9 */
 185                 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
 186                 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
 187                 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
 188                 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
 189                 /* IDSEL 10 */
 190                 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
 191                 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
 192                 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
 193                 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
 194                 /* IDSEL 11 */
 195                 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
 196                 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
 197                 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
 198                 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
 199                 /* IDSEL 12 */
 200                 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
 201                 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
 202                 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
 203                 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
 204                 >;
 205         };
 206
 207         fpga {
 208                 /*
 209                  * The Integator/AP predates the idea to have magic numbers
 210                  * identifying the PrimeCell in hardware, thus we have to
 211                  * supply these from the device tree.
 212                  */
 213                 rtc: rtc@15000000 {
 214                         compatible = "arm,pl030", "arm,primecell";
 215                         arm,primecell-periphid = <0x00041030>;
 216                         clocks = <&pclk>;
 217                         clock-names = "apb_pclk";
 218                 };
 219
 220                 uart0: uart@16000000 {
 221                         compatible = "arm,pl010", "arm,primecell";
 222                         arm,primecell-periphid = <0x00041010>;
 223                         clocks = <&uartclk>, <&pclk>;
 224                         clock-names = "uartclk", "apb_pclk";
 225                 };
 226
 227                 uart1: uart@17000000 {
 228                         compatible = "arm,pl010", "arm,primecell";
 229                         arm,primecell-periphid = <0x00041010>;
 230                         clocks = <&uartclk>, <&pclk>;
 231                         clock-names = "uartclk", "apb_pclk";
 232                 };
 233
 234                 kmi0: kmi@18000000 {
 235                         compatible = "arm,pl050", "arm,primecell";
 236                         arm,primecell-periphid = <0x00041050>;
 237                         clocks = <&xtal24mhz>, <&pclk>;
 238                         clock-names = "KMIREFCLK", "apb_pclk";
 239                 };
 240
 241                 kmi1: kmi@19000000 {
 242                         compatible = "arm,pl050", "arm,primecell";
 243                         arm,primecell-periphid = <0x00041050>;
 244                         clocks = <&xtal24mhz>, <&pclk>;
 245                         clock-names = "KMIREFCLK", "apb_pclk";
 246                 };
 247         };
 248
 249         /*
 250          * Logic module bus, we support up to 4 logical modules
 251          * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
 252          * and use interrupts 9, 10, 11 and 12 respectively.
 253          */
 254         bus@c0000000 {
 255                 compatible = "arm,integrator-ap-lm";
 256                 #address-cells = <1>;
 257                 #size-cells = <1>;
 258                 ranges = <0xc0000000 0xc0000000 0x40000000>;
 259                 dma-ranges;
 260
 261                 lm0: bus@c0000000 {
 262                         compatible = "simple-bus";
 263                         ranges = <0x00000000 0xc0000000 0x10000000>;
 264                         dma-ranges = <0x00000000 0x80000000 0x10000000>;
 265                         reg = <0xc0000000 0x10000000>;
 266                         #address-cells = <1>;
 267                         #size-cells = <1>;
 268                 };
 269                 lm1: bus@d0000000 {
 270                         compatible = "simple-bus";
 271                         ranges = <0x00000000 0xd0000000 0x10000000>;
 272                         dma-ranges = <0x00000000 0x80000000 0x10000000>;
 273                         reg = <0xd0000000 0x10000000>;
 274                         #address-cells = <1>;
 275                         #size-cells = <1>;
 276                 };
 277                 lm2: bus@e0000000 {
 278                         compatible = "simple-bus";
 279                         ranges = <0x00000000 0xe0000000 0x10000000>;
 280                         dma-ranges = <0x00000000 0x80000000 0x10000000>;
 281                         reg = <0xe0000000 0x10000000>;
 282                         #address-cells = <1>;
 283                         #size-cells = <1>;
 284                 };
 285                 lm3: bus@f0000000 {
 286                         compatible = "simple-bus";
 287                         ranges = <0x00000000 0xf0000000 0x10000000>;
 288                         dma-ranges = <0x00000000 0x80000000 0x10000000>;
 289                         reg = <0xf0000000 0x10000000>;
 290                         #address-cells = <1>;
 291                         #size-cells = <1>;
 292                 };
 293         };
 294 };