2 * Device Tree for the ARM Integrator/AP platform
6 /include/ "integrator.dtsi"
9 model = "ARM Integrator/AP";
10 compatible = "arm,integrator-ap";
11 dma-ranges = <0x80000000 0x0 0x80000000>;
14 arm,timer-primary = &timer2;
15 arm,timer-secondary = &timer1;
19 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
22 /* 24 MHz chrystal on the Integrator/AP development board */
23 xtal24mhz: xtal24mhz@24M {
25 compatible = "fixed-clock";
26 clock-frequency = <24000000>;
31 compatible = "fixed-factor-clock";
34 clocks = <&xtal24mhz>;
37 /* The UART clock is 14.74 MHz divided by an ICS525 */
38 uartclk: uartclk@14.74M {
40 compatible = "fixed-clock";
41 clock-frequency = <14745600>;
42 clocks = <&xtal24mhz>;
45 core-module@10000000 {
46 /* 24 MHz chrystal on the core module */
47 cm24mhz: cm24mhz@24M {
49 compatible = "fixed-clock";
50 clock-frequency = <24000000>;
53 /* Oscillator on the core module, clocks the CPU core */
55 compatible = "arm,syscon-icst525-integratorap-cm";
62 /* Auxilary oscillator on the core module, 32.369MHz at boot */
64 compatible = "arm,syscon-icst525";
73 compatible = "arm,integrator-ap-syscon", "syscon";
74 reg = <0x11000000 0x100>;
75 interrupt-parent = <&pic>;
76 /* These are the logical module IRQs */
77 interrupts = <9>, <10>, <11>, <12>;
80 * SYSCLK clocks PCIv3 bridge, system controller and the
84 compatible = "arm,syscon-icst525-integratorap-sys";
88 clocks = <&xtal24mhz>;
91 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
93 compatible = "arm,syscon-icst525-integratorap-pci";
97 clocks = <&xtal24mhz>;
101 timer0: timer@13000000 {
102 compatible = "arm,integrator-timer";
103 clocks = <&xtal24mhz>;
106 timer1: timer@13000100 {
107 compatible = "arm,integrator-timer";
108 clocks = <&xtal24mhz>;
111 timer2: timer@13000200 {
112 compatible = "arm,integrator-timer";
113 clocks = <&xtal24mhz>;
117 valid-mask = <0x003fffff>;
120 pci: pciv3@62000000 {
121 compatible = "v3,v360epc-pci";
122 #interrupt-cells = <1>;
124 #address-cells = <3>;
125 reg = <0x62000000 0x10000>;
126 interrupt-parent = <&pic>;
127 interrupts = <17>; /* Bus error IRQ */
128 ranges = <0x00000000 0 0x61000000 /* config space */
129 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
130 0x01000000 0 0x0 /* I/O space */
131 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
132 0x02000000 0 0x00000000 /* non-prefectable memory */
133 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
134 0x42000000 0 0x10000000 /* prefetchable memory */
135 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
136 interrupt-map-mask = <0xf800 0 0 0x7>;
139 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
140 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
141 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
142 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
144 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
145 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
146 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
147 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
149 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
150 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
151 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
152 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
154 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
155 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
156 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
157 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
163 * The Integator/AP predates the idea to have magic numbers
164 * identifying the PrimeCell in hardware, thus we have to
165 * supply these from the device tree.
168 compatible = "arm,pl030", "arm,primecell";
169 arm,primecell-periphid = <0x00041030>;
171 clock-names = "apb_pclk";
174 uart0: uart@16000000 {
175 compatible = "arm,pl010", "arm,primecell";
176 arm,primecell-periphid = <0x00041010>;
177 clocks = <&uartclk>, <&pclk>;
178 clock-names = "uartclk", "apb_pclk";
181 uart1: uart@17000000 {
182 compatible = "arm,pl010", "arm,primecell";
183 arm,primecell-periphid = <0x00041010>;
184 clocks = <&uartclk>, <&pclk>;
185 clock-names = "uartclk", "apb_pclk";
189 compatible = "arm,pl050", "arm,primecell";
190 arm,primecell-periphid = <0x00041050>;
191 clocks = <&xtal24mhz>, <&pclk>;
192 clock-names = "KMIREFCLK", "apb_pclk";
196 compatible = "arm,pl050", "arm,primecell";
197 arm,primecell-periphid = <0x00041050>;
198 clocks = <&xtal24mhz>, <&pclk>;
199 clock-names = "KMIREFCLK", "apb_pclk";