1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
18 * The decompressor and also some bootloaders rely on a
19 * pre-existing /chosen node to be available to insert the
20 * command line and merge other ATAGS info.
59 entry-method = "psci";
61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x0010000>;
65 entry-latency-us = <100>;
66 exit-latency-us = <50>;
67 min-residency-us = <1000>;
72 compatible = "arm,cortex-a7";
75 clock-frequency = <792000000>;
76 clock-latency = <61036>; /* two CLK32 periods */
77 clocks = <&clks IMX7D_CLK_ARM>;
78 cpu-idle-states = <&cpu_sleep_wait>;
83 compatible = "fixed-clock";
85 clock-frequency = <32768>;
86 clock-output-names = "ckil";
90 compatible = "fixed-clock";
92 clock-frequency = <24000000>;
93 clock-output-names = "osc";
96 usbphynop1: usbphynop1 {
97 compatible = "usb-nop-xceiv";
98 clocks = <&clks IMX7D_USB_PHY1_CLK>;
99 clock-names = "main_clk";
103 usbphynop3: usbphynop3 {
104 compatible = "usb-nop-xceiv";
105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
106 clock-names = "main_clk";
111 compatible = "arm,cortex-a7-pmu";
112 interrupt-parent = <&gpc>;
113 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
114 interrupt-affinity = <&cpu0>;
119 * non-configurable replicators don't show up on the
120 * AMBA bus. As such no need to add "arm,primecell"
122 compatible = "arm,coresight-static-replicator";
125 #address-cells = <1>;
127 /* replicator output ports */
130 replicator_out_port0: endpoint {
131 remote-endpoint = <&tpiu_in_port>;
137 replicator_out_port1: endpoint {
138 remote-endpoint = <&etr_in_port>;
145 replicator_in_port0: endpoint {
146 remote-endpoint = <&etf_out_port>;
153 compatible = "fsl,imx7d-tempmon";
154 interrupt-parent = <&gpc>;
155 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
156 fsl,tempmon = <&anatop>;
157 nvmem-cells = <&tempmon_calib>,
158 <&tempmon_temp_grade>;
159 nvmem-cell-names = "calib", "temp_grade";
160 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
164 compatible = "arm,armv7-timer";
165 interrupt-parent = <&intc>;
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
173 #address-cells = <1>;
175 compatible = "simple-bus";
176 interrupt-parent = <&gpc>;
180 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
181 reg = <0x30041000 0x1000>;
182 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
183 clock-names = "apb_pclk";
185 ca_funnel_in_ports: in-ports {
186 #address-cells = <1>;
191 ca_funnel_in_port0: endpoint {
192 remote-endpoint = <&etm0_out_port>;
196 /* the other input ports are not connect to anything */
201 ca_funnel_out_port0: endpoint {
202 remote-endpoint = <&hugo_funnel_in_port0>;
210 compatible = "arm,coresight-etm3x", "arm,primecell";
211 reg = <0x3007c000 0x1000>;
213 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
214 clock-names = "apb_pclk";
218 etm0_out_port: endpoint {
219 remote-endpoint = <&ca_funnel_in_port0>;
226 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
227 reg = <0x30083000 0x1000>;
228 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
229 clock-names = "apb_pclk";
232 #address-cells = <1>;
237 hugo_funnel_in_port0: endpoint {
238 remote-endpoint = <&ca_funnel_out_port0>;
244 hugo_funnel_in_port1: endpoint {
248 /* the other input ports are not connect to anything */
253 hugo_funnel_out_port0: endpoint {
254 remote-endpoint = <&etf_in_port>;
261 compatible = "arm,coresight-tmc", "arm,primecell";
262 reg = <0x30084000 0x1000>;
263 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
264 clock-names = "apb_pclk";
268 etf_in_port: endpoint {
269 remote-endpoint = <&hugo_funnel_out_port0>;
276 etf_out_port: endpoint {
277 remote-endpoint = <&replicator_in_port0>;
284 compatible = "arm,coresight-tmc", "arm,primecell";
285 reg = <0x30086000 0x1000>;
286 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
287 clock-names = "apb_pclk";
291 etr_in_port: endpoint {
292 remote-endpoint = <&replicator_out_port1>;
299 compatible = "arm,coresight-tpiu", "arm,primecell";
300 reg = <0x30087000 0x1000>;
301 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
302 clock-names = "apb_pclk";
306 tpiu_in_port: endpoint {
307 remote-endpoint = <&replicator_out_port0>;
313 intc: interrupt-controller@31001000 {
314 compatible = "arm,cortex-a7-gic";
315 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
316 #interrupt-cells = <3>;
317 interrupt-controller;
318 interrupt-parent = <&intc>;
319 reg = <0x31001000 0x1000>,
325 aips1: aips-bus@30000000 {
326 compatible = "fsl,aips-bus", "simple-bus";
327 #address-cells = <1>;
329 reg = <0x30000000 0x400000>;
332 gpio1: gpio@30200000 {
333 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
334 reg = <0x30200000 0x10000>;
335 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
336 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
344 gpio2: gpio@30210000 {
345 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
346 reg = <0x30210000 0x10000>;
347 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 gpio-ranges = <&iomuxc 0 13 32>;
356 gpio3: gpio@30220000 {
357 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
358 reg = <0x30220000 0x10000>;
359 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
365 gpio-ranges = <&iomuxc 0 45 29>;
368 gpio4: gpio@30230000 {
369 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
370 reg = <0x30230000 0x10000>;
371 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
377 gpio-ranges = <&iomuxc 0 74 24>;
380 gpio5: gpio@30240000 {
381 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
382 reg = <0x30240000 0x10000>;
383 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
389 gpio-ranges = <&iomuxc 0 98 18>;
392 gpio6: gpio@30250000 {
393 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
394 reg = <0x30250000 0x10000>;
395 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-controller;
400 #interrupt-cells = <2>;
401 gpio-ranges = <&iomuxc 0 116 23>;
404 gpio7: gpio@30260000 {
405 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
406 reg = <0x30260000 0x10000>;
407 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
411 interrupt-controller;
412 #interrupt-cells = <2>;
413 gpio-ranges = <&iomuxc 0 139 16>;
416 wdog1: wdog@30280000 {
417 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
418 reg = <0x30280000 0x10000>;
419 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
423 wdog2: wdog@30290000 {
424 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
425 reg = <0x30290000 0x10000>;
426 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
431 wdog3: wdog@302a0000 {
432 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
433 reg = <0x302a0000 0x10000>;
434 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
439 wdog4: wdog@302b0000 {
440 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
441 reg = <0x302b0000 0x10000>;
442 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
447 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
448 compatible = "fsl,imx7d-iomuxc-lpsr";
449 reg = <0x302c0000 0x10000>;
450 fsl,input-sel = <&iomuxc>;
453 gpt1: timer@302d0000 {
454 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
455 reg = <0x302d0000 0x10000>;
456 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
458 <&clks IMX7D_GPT1_ROOT_CLK>;
459 clock-names = "ipg", "per";
462 gpt2: timer@302e0000 {
463 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
464 reg = <0x302e0000 0x10000>;
465 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
467 <&clks IMX7D_GPT2_ROOT_CLK>;
468 clock-names = "ipg", "per";
472 gpt3: timer@302f0000 {
473 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
474 reg = <0x302f0000 0x10000>;
475 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
477 <&clks IMX7D_GPT3_ROOT_CLK>;
478 clock-names = "ipg", "per";
482 gpt4: timer@30300000 {
483 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
484 reg = <0x30300000 0x10000>;
485 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
487 <&clks IMX7D_GPT4_ROOT_CLK>;
488 clock-names = "ipg", "per";
493 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
494 reg = <0x30320000 0x10000>;
495 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
500 iomuxc: iomuxc@30330000 {
501 compatible = "fsl,imx7d-iomuxc";
502 reg = <0x30330000 0x10000>;
505 gpr: iomuxc-gpr@30340000 {
506 compatible = "fsl,imx7d-iomuxc-gpr",
507 "fsl,imx6q-iomuxc-gpr", "syscon",
509 reg = <0x30340000 0x10000>;
511 mux: mux-controller {
512 compatible = "mmio-mux";
513 #mux-control-cells = <1>;
514 mux-reg-masks = <0x14 0x00000010>;
518 compatible = "video-mux";
519 mux-controls = <&mux 0>;
520 #address-cells = <1>;
531 csi_mux_from_mipi_vc0: endpoint {
532 remote-endpoint = <&mipi_vc0_to_csi_mux>;
539 csi_mux_to_csi: endpoint {
540 remote-endpoint = <&csi_from_csi_mux>;
546 ocotp: ocotp-ctrl@30350000 {
547 #address-cells = <1>;
549 compatible = "fsl,imx7d-ocotp", "syscon";
550 reg = <0x30350000 0x10000>;
551 clocks = <&clks IMX7D_OCOTP_CLK>;
553 tempmon_calib: calib@3c {
557 tempmon_temp_grade: temp-grade@10 {
561 cpu_speed_grade: speed-grade@10 {
566 anatop: anatop@30360000 {
567 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
568 "syscon", "simple-bus";
569 reg = <0x30360000 0x10000>;
570 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
573 reg_1p0d: regulator-vdd1p0d {
574 compatible = "fsl,anatop-regulator";
575 regulator-name = "vdd1p0d";
576 regulator-min-microvolt = <800000>;
577 regulator-max-microvolt = <1200000>;
578 anatop-reg-offset = <0x210>;
579 anatop-vol-bit-shift = <8>;
580 anatop-vol-bit-width = <5>;
581 anatop-min-bit-val = <8>;
582 anatop-min-voltage = <800000>;
583 anatop-max-voltage = <1200000>;
584 anatop-enable-bit = <0>;
587 reg_1p2: regulator-vdd1p2 {
588 compatible = "fsl,anatop-regulator";
589 regulator-name = "vdd1p2";
590 regulator-min-microvolt = <1100000>;
591 regulator-max-microvolt = <1300000>;
592 anatop-reg-offset = <0x220>;
593 anatop-vol-bit-shift = <8>;
594 anatop-vol-bit-width = <5>;
595 anatop-min-bit-val = <0x14>;
596 anatop-min-voltage = <1100000>;
597 anatop-max-voltage = <1300000>;
598 anatop-enable-bit = <0>;
602 snvs: snvs@30370000 {
603 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
604 reg = <0x30370000 0x10000>;
606 snvs_rtc: snvs-rtc-lp {
607 compatible = "fsl,sec-v4.0-mon-rtc-lp";
610 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clks IMX7D_SNVS_CLK>;
613 clock-names = "snvs-rtc";
616 snvs_pwrkey: snvs-powerkey {
617 compatible = "fsl,sec-v4.0-pwrkey";
619 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
620 linux,keycode = <KEY_POWER>;
627 compatible = "fsl,imx7d-ccm";
628 reg = <0x30380000 0x10000>;
629 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&ckil>, <&osc>;
633 clock-names = "ckil", "osc";
637 compatible = "fsl,imx7d-src", "syscon";
638 reg = <0x30390000 0x10000>;
639 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
644 compatible = "fsl,imx7d-gpc";
645 reg = <0x303a0000 0x10000>;
646 interrupt-controller;
647 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
648 #interrupt-cells = <3>;
649 interrupt-parent = <&intc>;
650 #power-domain-cells = <1>;
653 #address-cells = <1>;
656 pgc_mipi_phy: power-domain@0 {
657 #power-domain-cells = <0>;
659 power-supply = <®_1p0d>;
662 pgc_pcie_phy: power-domain@1 {
663 #power-domain-cells = <0>;
665 power-supply = <®_1p0d>;
671 aips2: aips-bus@30400000 {
672 compatible = "fsl,aips-bus", "simple-bus";
673 #address-cells = <1>;
675 reg = <0x30400000 0x400000>;
679 compatible = "fsl,imx7d-adc";
680 reg = <0x30610000 0x10000>;
681 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
684 #io-channel-cells = <1>;
689 compatible = "fsl,imx7d-adc";
690 reg = <0x30620000 0x10000>;
691 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
694 #io-channel-cells = <1>;
698 ecspi4: spi@30630000 {
699 #address-cells = <1>;
701 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
702 reg = <0x30630000 0x10000>;
703 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
705 <&clks IMX7D_ECSPI4_ROOT_CLK>;
706 clock-names = "ipg", "per";
711 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
712 reg = <0x30660000 0x10000>;
713 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
715 <&clks IMX7D_PWM1_ROOT_CLK>;
716 clock-names = "ipg", "per";
722 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
723 reg = <0x30670000 0x10000>;
724 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
726 <&clks IMX7D_PWM2_ROOT_CLK>;
727 clock-names = "ipg", "per";
733 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
734 reg = <0x30680000 0x10000>;
735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
737 <&clks IMX7D_PWM3_ROOT_CLK>;
738 clock-names = "ipg", "per";
744 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
745 reg = <0x30690000 0x10000>;
746 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
748 <&clks IMX7D_PWM4_ROOT_CLK>;
749 clock-names = "ipg", "per";
755 compatible = "fsl,imx7-csi";
756 reg = <0x30710000 0x10000>;
757 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&clks IMX7D_CLK_DUMMY>,
759 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
760 <&clks IMX7D_CLK_DUMMY>;
761 clock-names = "axi", "mclk", "dcic";
765 csi_from_csi_mux: endpoint {
766 remote-endpoint = <&csi_mux_to_csi>;
771 lcdif: lcdif@30730000 {
772 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
773 reg = <0x30730000 0x10000>;
774 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
776 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
777 clock-names = "pix", "axi";
781 mipi_csi: mipi-csi@30750000 {
782 compatible = "fsl,imx7-mipi-csi2";
783 reg = <0x30750000 0x10000>;
784 #address-cells = <1>;
786 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
788 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
789 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
790 clock-names = "pclk", "wrap", "phy";
791 power-domains = <&pgc_mipi_phy>;
792 phy-supply = <®_1p0d>;
793 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
794 reset-names = "mrst";
804 mipi_vc0_to_csi_mux: endpoint {
805 remote-endpoint = <&csi_mux_from_mipi_vc0>;
811 aips3: aips-bus@30800000 {
812 compatible = "fsl,aips-bus", "simple-bus";
813 #address-cells = <1>;
815 reg = <0x30800000 0x400000>;
819 compatible = "fsl,spba-bus", "simple-bus";
820 #address-cells = <1>;
822 reg = <0x30800000 0x100000>;
825 ecspi1: spi@30820000 {
826 #address-cells = <1>;
828 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
829 reg = <0x30820000 0x10000>;
830 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
832 <&clks IMX7D_ECSPI1_ROOT_CLK>;
833 clock-names = "ipg", "per";
837 ecspi2: spi@30830000 {
838 #address-cells = <1>;
840 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
841 reg = <0x30830000 0x10000>;
842 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
844 <&clks IMX7D_ECSPI2_ROOT_CLK>;
845 clock-names = "ipg", "per";
849 ecspi3: spi@30840000 {
850 #address-cells = <1>;
852 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
853 reg = <0x30840000 0x10000>;
854 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
856 <&clks IMX7D_ECSPI3_ROOT_CLK>;
857 clock-names = "ipg", "per";
861 uart1: serial@30860000 {
862 compatible = "fsl,imx7d-uart",
864 reg = <0x30860000 0x10000>;
865 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
867 <&clks IMX7D_UART1_ROOT_CLK>;
868 clock-names = "ipg", "per";
872 uart2: serial@30890000 {
873 compatible = "fsl,imx7d-uart",
875 reg = <0x30890000 0x10000>;
876 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
878 <&clks IMX7D_UART2_ROOT_CLK>;
879 clock-names = "ipg", "per";
883 uart3: serial@30880000 {
884 compatible = "fsl,imx7d-uart",
886 reg = <0x30880000 0x10000>;
887 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
889 <&clks IMX7D_UART3_ROOT_CLK>;
890 clock-names = "ipg", "per";
895 #sound-dai-cells = <0>;
896 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
897 reg = <0x308a0000 0x10000>;
898 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
900 <&clks IMX7D_SAI1_ROOT_CLK>,
901 <&clks IMX7D_CLK_DUMMY>,
902 <&clks IMX7D_CLK_DUMMY>;
903 clock-names = "bus", "mclk1", "mclk2", "mclk3";
904 dma-names = "rx", "tx";
905 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
910 #sound-dai-cells = <0>;
911 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
912 reg = <0x308b0000 0x10000>;
913 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
915 <&clks IMX7D_SAI2_ROOT_CLK>,
916 <&clks IMX7D_CLK_DUMMY>,
917 <&clks IMX7D_CLK_DUMMY>;
918 clock-names = "bus", "mclk1", "mclk2", "mclk3";
919 dma-names = "rx", "tx";
920 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
925 #sound-dai-cells = <0>;
926 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
927 reg = <0x308c0000 0x10000>;
928 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
930 <&clks IMX7D_SAI3_ROOT_CLK>,
931 <&clks IMX7D_CLK_DUMMY>,
932 <&clks IMX7D_CLK_DUMMY>;
933 clock-names = "bus", "mclk1", "mclk2", "mclk3";
934 dma-names = "rx", "tx";
935 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
940 crypto: caam@30900000 {
941 compatible = "fsl,sec-v4.0";
942 #address-cells = <1>;
944 reg = <0x30900000 0x40000>;
945 ranges = <0 0x30900000 0x40000>;
946 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clks IMX7D_CAAM_CLK>,
948 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
949 clock-names = "ipg", "aclk";
952 compatible = "fsl,sec-v4.0-job-ring";
953 reg = <0x1000 0x1000>;
954 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
958 compatible = "fsl,sec-v4.0-job-ring";
959 reg = <0x2000 0x1000>;
960 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
964 compatible = "fsl,sec-v4.0-job-ring";
965 reg = <0x3000 0x1000>;
966 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
970 flexcan1: can@30a00000 {
971 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
972 reg = <0x30a00000 0x10000>;
973 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&clks IMX7D_CLK_DUMMY>,
975 <&clks IMX7D_CAN1_ROOT_CLK>;
976 clock-names = "ipg", "per";
977 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
981 flexcan2: can@30a10000 {
982 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
983 reg = <0x30a10000 0x10000>;
984 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&clks IMX7D_CLK_DUMMY>,
986 <&clks IMX7D_CAN2_ROOT_CLK>;
987 clock-names = "ipg", "per";
988 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
993 #address-cells = <1>;
995 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
996 reg = <0x30a20000 0x10000>;
997 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1002 i2c2: i2c@30a30000 {
1003 #address-cells = <1>;
1005 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1006 reg = <0x30a30000 0x10000>;
1007 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1009 status = "disabled";
1012 i2c3: i2c@30a40000 {
1013 #address-cells = <1>;
1015 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1016 reg = <0x30a40000 0x10000>;
1017 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1019 status = "disabled";
1022 i2c4: i2c@30a50000 {
1023 #address-cells = <1>;
1025 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1026 reg = <0x30a50000 0x10000>;
1027 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1029 status = "disabled";
1032 uart4: serial@30a60000 {
1033 compatible = "fsl,imx7d-uart",
1035 reg = <0x30a60000 0x10000>;
1036 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1038 <&clks IMX7D_UART4_ROOT_CLK>;
1039 clock-names = "ipg", "per";
1040 status = "disabled";
1043 uart5: serial@30a70000 {
1044 compatible = "fsl,imx7d-uart",
1046 reg = <0x30a70000 0x10000>;
1047 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1049 <&clks IMX7D_UART5_ROOT_CLK>;
1050 clock-names = "ipg", "per";
1051 status = "disabled";
1054 uart6: serial@30a80000 {
1055 compatible = "fsl,imx7d-uart",
1057 reg = <0x30a80000 0x10000>;
1058 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1060 <&clks IMX7D_UART6_ROOT_CLK>;
1061 clock-names = "ipg", "per";
1062 status = "disabled";
1065 uart7: serial@30a90000 {
1066 compatible = "fsl,imx7d-uart",
1068 reg = <0x30a90000 0x10000>;
1069 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1071 <&clks IMX7D_UART7_ROOT_CLK>;
1072 clock-names = "ipg", "per";
1073 status = "disabled";
1076 mu0a: mailbox@30aa0000 {
1077 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1078 reg = <0x30aa0000 0x10000>;
1079 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1082 status = "disabled";
1085 mu0b: mailbox@30ab0000 {
1086 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1087 reg = <0x30ab0000 0x10000>;
1088 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1092 status = "disabled";
1095 usbotg1: usb@30b10000 {
1096 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1097 reg = <0x30b10000 0x200>;
1098 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1100 fsl,usbphy = <&usbphynop1>;
1101 fsl,usbmisc = <&usbmisc1 0>;
1102 phy-clkgate-delay-us = <400>;
1103 status = "disabled";
1106 usbh: usb@30b30000 {
1107 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1108 reg = <0x30b30000 0x200>;
1109 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1111 fsl,usbphy = <&usbphynop3>;
1112 fsl,usbmisc = <&usbmisc3 0>;
1115 phy-clkgate-delay-us = <400>;
1116 status = "disabled";
1119 usbmisc1: usbmisc@30b10200 {
1121 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1122 reg = <0x30b10200 0x200>;
1125 usbmisc3: usbmisc@30b30200 {
1127 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1128 reg = <0x30b30200 0x200>;
1131 usdhc1: usdhc@30b40000 {
1132 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1133 reg = <0x30b40000 0x10000>;
1134 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1135 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1136 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1137 <&clks IMX7D_USDHC1_ROOT_CLK>;
1138 clock-names = "ipg", "ahb", "per";
1140 fsl,tuning-step = <2>;
1141 fsl,tuning-start-tap = <20>;
1142 status = "disabled";
1145 usdhc2: usdhc@30b50000 {
1146 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1147 reg = <0x30b50000 0x10000>;
1148 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1150 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1151 <&clks IMX7D_USDHC2_ROOT_CLK>;
1152 clock-names = "ipg", "ahb", "per";
1154 fsl,tuning-step = <2>;
1155 fsl,tuning-start-tap = <20>;
1156 status = "disabled";
1159 usdhc3: usdhc@30b60000 {
1160 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1161 reg = <0x30b60000 0x10000>;
1162 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1163 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1164 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1165 <&clks IMX7D_USDHC3_ROOT_CLK>;
1166 clock-names = "ipg", "ahb", "per";
1168 fsl,tuning-step = <2>;
1169 fsl,tuning-start-tap = <20>;
1170 status = "disabled";
1173 sdma: sdma@30bd0000 {
1174 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1175 reg = <0x30bd0000 0x10000>;
1176 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1178 <&clks IMX7D_SDMA_CORE_CLK>;
1179 clock-names = "ipg", "ahb";
1181 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
1184 fec1: ethernet@30be0000 {
1185 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1186 reg = <0x30be0000 0x10000>;
1187 interrupt-names = "int0", "int1", "int2", "pps";
1188 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1193 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1194 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1195 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1196 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1197 clock-names = "ipg", "ahb", "ptp",
1198 "enet_clk_ref", "enet_out";
1199 fsl,num-tx-queues = <3>;
1200 fsl,num-rx-queues = <3>;
1201 status = "disabled";
1205 dma_apbh: dma-controller@33000000 {
1206 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1207 reg = <0x33000000 0x2000>;
1208 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1217 gpmi: gpmi-nand@33002000{
1218 compatible = "fsl,imx7d-gpmi-nand";
1219 #address-cells = <1>;
1221 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1222 reg-names = "gpmi-nand", "bch";
1223 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1224 interrupt-names = "bch";
1225 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1226 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1227 clock-names = "gpmi_io", "gpmi_bch_apb";
1228 dmas = <&dma_apbh 0>;
1229 dma-names = "rx-tx";
1230 status = "disabled";
1231 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1232 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;