1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
18 * The decompressor and also some bootloaders rely on a
19 * pre-existing /chosen node to be available to insert the
20 * command line and merge other ATAGS info.
59 entry-method = "psci";
61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x0010000>;
65 entry-latency-us = <100>;
66 exit-latency-us = <50>;
67 min-residency-us = <1000>;
72 compatible = "arm,cortex-a7";
75 clock-frequency = <792000000>;
76 clock-latency = <61036>; /* two CLK32 periods */
77 clocks = <&clks IMX7D_CLK_ARM>;
78 cpu-idle-states = <&cpu_sleep_wait>;
83 compatible = "fixed-clock";
85 clock-frequency = <32768>;
86 clock-output-names = "ckil";
90 compatible = "fixed-clock";
92 clock-frequency = <24000000>;
93 clock-output-names = "osc";
96 usbphynop1: usbphynop1 {
97 compatible = "usb-nop-xceiv";
98 clocks = <&clks IMX7D_USB_PHY1_CLK>;
99 clock-names = "main_clk";
103 usbphynop3: usbphynop3 {
104 compatible = "usb-nop-xceiv";
105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
106 clock-names = "main_clk";
111 compatible = "arm,cortex-a7-pmu";
112 interrupt-parent = <&gpc>;
113 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
114 interrupt-affinity = <&cpu0>;
119 * non-configurable replicators don't show up on the
120 * AMBA bus. As such no need to add "arm,primecell"
122 compatible = "arm,coresight-static-replicator";
125 #address-cells = <1>;
127 /* replicator output ports */
130 replicator_out_port0: endpoint {
131 remote-endpoint = <&tpiu_in_port>;
137 replicator_out_port1: endpoint {
138 remote-endpoint = <&etr_in_port>;
145 replicator_in_port0: endpoint {
146 remote-endpoint = <&etf_out_port>;
153 compatible = "arm,armv7-timer";
154 arm,cpu-registers-not-fw-configured;
155 interrupt-parent = <&intc>;
156 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
158 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
159 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
163 #address-cells = <1>;
165 compatible = "simple-bus";
166 interrupt-parent = <&gpc>;
170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
171 reg = <0x30041000 0x1000>;
172 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
173 clock-names = "apb_pclk";
175 ca_funnel_in_ports: in-ports {
177 ca_funnel_in_port0: endpoint {
178 remote-endpoint = <&etm0_out_port>;
182 /* the other input ports are not connect to anything */
187 ca_funnel_out_port0: endpoint {
188 remote-endpoint = <&hugo_funnel_in_port0>;
196 compatible = "arm,coresight-etm3x", "arm,primecell";
197 reg = <0x3007c000 0x1000>;
199 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
200 clock-names = "apb_pclk";
204 etm0_out_port: endpoint {
205 remote-endpoint = <&ca_funnel_in_port0>;
212 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
213 reg = <0x30083000 0x1000>;
214 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
215 clock-names = "apb_pclk";
218 #address-cells = <1>;
223 hugo_funnel_in_port0: endpoint {
224 remote-endpoint = <&ca_funnel_out_port0>;
230 hugo_funnel_in_port1: endpoint {
234 /* the other input ports are not connect to anything */
239 hugo_funnel_out_port0: endpoint {
240 remote-endpoint = <&etf_in_port>;
247 compatible = "arm,coresight-tmc", "arm,primecell";
248 reg = <0x30084000 0x1000>;
249 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
250 clock-names = "apb_pclk";
254 etf_in_port: endpoint {
255 remote-endpoint = <&hugo_funnel_out_port0>;
262 etf_out_port: endpoint {
263 remote-endpoint = <&replicator_in_port0>;
270 compatible = "arm,coresight-tmc", "arm,primecell";
271 reg = <0x30086000 0x1000>;
272 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
273 clock-names = "apb_pclk";
277 etr_in_port: endpoint {
278 remote-endpoint = <&replicator_out_port1>;
285 compatible = "arm,coresight-tpiu", "arm,primecell";
286 reg = <0x30087000 0x1000>;
287 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
288 clock-names = "apb_pclk";
292 tpiu_in_port: endpoint {
293 remote-endpoint = <&replicator_out_port0>;
299 intc: interrupt-controller@31001000 {
300 compatible = "arm,cortex-a7-gic";
301 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
302 #interrupt-cells = <3>;
303 interrupt-controller;
304 interrupt-parent = <&intc>;
305 reg = <0x31001000 0x1000>,
311 aips1: bus@30000000 {
312 compatible = "fsl,aips-bus", "simple-bus";
313 #address-cells = <1>;
315 reg = <0x30000000 0x400000>;
318 gpio1: gpio@30200000 {
319 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
320 reg = <0x30200000 0x10000>;
321 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
322 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
330 gpio2: gpio@30210000 {
331 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
332 reg = <0x30210000 0x10000>;
333 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 gpio-ranges = <&iomuxc 0 13 32>;
342 gpio3: gpio@30220000 {
343 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
344 reg = <0x30220000 0x10000>;
345 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 gpio-ranges = <&iomuxc 0 45 29>;
354 gpio4: gpio@30230000 {
355 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
356 reg = <0x30230000 0x10000>;
357 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 gpio-ranges = <&iomuxc 0 74 24>;
366 gpio5: gpio@30240000 {
367 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
368 reg = <0x30240000 0x10000>;
369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 gpio-ranges = <&iomuxc 0 98 18>;
378 gpio6: gpio@30250000 {
379 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
380 reg = <0x30250000 0x10000>;
381 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 gpio-ranges = <&iomuxc 0 116 23>;
390 gpio7: gpio@30260000 {
391 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
392 reg = <0x30260000 0x10000>;
393 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
399 gpio-ranges = <&iomuxc 0 139 16>;
402 wdog1: watchdog@30280000 {
403 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
404 reg = <0x30280000 0x10000>;
405 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
409 wdog2: watchdog@30290000 {
410 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
411 reg = <0x30290000 0x10000>;
412 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
417 wdog3: watchdog@302a0000 {
418 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
419 reg = <0x302a0000 0x10000>;
420 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
425 wdog4: watchdog@302b0000 {
426 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
427 reg = <0x302b0000 0x10000>;
428 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
433 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
434 compatible = "fsl,imx7d-iomuxc-lpsr";
435 reg = <0x302c0000 0x10000>;
436 fsl,input-sel = <&iomuxc>;
439 gpt1: timer@302d0000 {
440 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
441 reg = <0x302d0000 0x10000>;
442 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
444 <&clks IMX7D_GPT1_ROOT_CLK>;
445 clock-names = "ipg", "per";
448 gpt2: timer@302e0000 {
449 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
450 reg = <0x302e0000 0x10000>;
451 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
453 <&clks IMX7D_GPT2_ROOT_CLK>;
454 clock-names = "ipg", "per";
458 gpt3: timer@302f0000 {
459 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
460 reg = <0x302f0000 0x10000>;
461 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
463 <&clks IMX7D_GPT3_ROOT_CLK>;
464 clock-names = "ipg", "per";
468 gpt4: timer@30300000 {
469 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
470 reg = <0x30300000 0x10000>;
471 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
473 <&clks IMX7D_GPT4_ROOT_CLK>;
474 clock-names = "ipg", "per";
478 kpp: keypad@30320000 {
479 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
480 reg = <0x30320000 0x10000>;
481 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
486 iomuxc: pinctrl@30330000 {
487 compatible = "fsl,imx7d-iomuxc";
488 reg = <0x30330000 0x10000>;
491 gpr: iomuxc-gpr@30340000 {
492 compatible = "fsl,imx7d-iomuxc-gpr",
493 "fsl,imx6q-iomuxc-gpr", "syscon",
495 reg = <0x30340000 0x10000>;
497 mux: mux-controller {
498 compatible = "mmio-mux";
499 #mux-control-cells = <0>;
500 mux-reg-masks = <0x14 0x00000010>;
504 compatible = "video-mux";
505 mux-controls = <&mux 0>;
506 #address-cells = <1>;
517 csi_mux_from_mipi_vc0: endpoint {
518 remote-endpoint = <&mipi_vc0_to_csi_mux>;
525 csi_mux_to_csi: endpoint {
526 remote-endpoint = <&csi_from_csi_mux>;
532 ocotp: efuse@30350000 {
533 #address-cells = <1>;
535 compatible = "fsl,imx7d-ocotp", "syscon";
536 reg = <0x30350000 0x10000>;
537 clocks = <&clks IMX7D_OCOTP_CLK>;
539 tempmon_calib: calib@3c {
543 fuse_grade: fuse-grade@10 {
548 anatop: anatop@30360000 {
549 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
550 "syscon", "simple-mfd";
551 reg = <0x30360000 0x10000>;
552 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
555 reg_1p0d: regulator-vdd1p0d {
556 compatible = "fsl,anatop-regulator";
557 regulator-name = "vdd1p0d";
558 regulator-min-microvolt = <800000>;
559 regulator-max-microvolt = <1200000>;
560 anatop-reg-offset = <0x210>;
561 anatop-vol-bit-shift = <8>;
562 anatop-vol-bit-width = <5>;
563 anatop-min-bit-val = <8>;
564 anatop-min-voltage = <800000>;
565 anatop-max-voltage = <1200000>;
566 anatop-enable-bit = <0>;
569 reg_1p2: regulator-vdd1p2 {
570 compatible = "fsl,anatop-regulator";
571 regulator-name = "vdd1p2";
572 regulator-min-microvolt = <1100000>;
573 regulator-max-microvolt = <1300000>;
574 anatop-reg-offset = <0x220>;
575 anatop-vol-bit-shift = <8>;
576 anatop-vol-bit-width = <5>;
577 anatop-min-bit-val = <0x14>;
578 anatop-min-voltage = <1100000>;
579 anatop-max-voltage = <1300000>;
580 anatop-enable-bit = <0>;
584 compatible = "fsl,imx7d-tempmon";
585 interrupt-parent = <&gpc>;
586 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
587 fsl,tempmon = <&anatop>;
588 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
589 nvmem-cell-names = "calib", "temp_grade";
590 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
594 snvs: snvs@30370000 {
595 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
596 reg = <0x30370000 0x10000>;
598 snvs_rtc: snvs-rtc-lp {
599 compatible = "fsl,sec-v4.0-mon-rtc-lp";
602 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&clks IMX7D_SNVS_CLK>;
605 clock-names = "snvs-rtc";
608 snvs_pwrkey: snvs-powerkey {
609 compatible = "fsl,sec-v4.0-pwrkey";
611 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clks IMX7D_SNVS_CLK>;
613 clock-names = "snvs-pwrkey";
614 linux,keycode = <KEY_POWER>;
620 clks: clock-controller@30380000 {
621 compatible = "fsl,imx7d-ccm";
622 reg = <0x30380000 0x10000>;
623 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&ckil>, <&osc>;
627 clock-names = "ckil", "osc";
630 src: reset-controller@30390000 {
631 compatible = "fsl,imx7d-src", "syscon";
632 reg = <0x30390000 0x10000>;
633 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
638 compatible = "fsl,imx7d-gpc";
639 reg = <0x303a0000 0x10000>;
640 interrupt-controller;
641 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
642 #interrupt-cells = <3>;
643 interrupt-parent = <&intc>;
644 #power-domain-cells = <1>;
647 #address-cells = <1>;
650 pgc_mipi_phy: power-domain@0 {
651 #power-domain-cells = <0>;
653 power-supply = <®_1p0d>;
656 pgc_pcie_phy: power-domain@1 {
657 #power-domain-cells = <0>;
659 power-supply = <®_1p0d>;
662 pgc_hsic_phy: power-domain@2 {
663 #power-domain-cells = <0>;
665 power-supply = <®_1p2>;
671 aips2: bus@30400000 {
672 compatible = "fsl,aips-bus", "simple-bus";
673 #address-cells = <1>;
675 reg = <0x30400000 0x400000>;
679 compatible = "fsl,imx7d-adc";
680 reg = <0x30610000 0x10000>;
681 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
684 #io-channel-cells = <1>;
689 compatible = "fsl,imx7d-adc";
690 reg = <0x30620000 0x10000>;
691 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
694 #io-channel-cells = <1>;
698 ecspi4: spi@30630000 {
699 #address-cells = <1>;
701 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
702 reg = <0x30630000 0x10000>;
703 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
705 <&clks IMX7D_ECSPI4_ROOT_CLK>;
706 clock-names = "ipg", "per";
711 compatible = "fsl,vf610-ftm-pwm";
712 reg = <0x30640000 0x10000>;
714 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
715 clock-names = "ftm_sys", "ftm_ext",
716 "ftm_fix", "ftm_cnt_clk_en";
717 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
718 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
719 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
720 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
725 compatible = "fsl,vf610-ftm-pwm";
726 reg = <0x30650000 0x10000>;
728 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
729 clock-names = "ftm_sys", "ftm_ext",
730 "ftm_fix", "ftm_cnt_clk_en";
731 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
732 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
733 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
734 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
739 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
740 reg = <0x30660000 0x10000>;
741 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
743 <&clks IMX7D_PWM1_ROOT_CLK>;
744 clock-names = "ipg", "per";
750 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
751 reg = <0x30670000 0x10000>;
752 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
754 <&clks IMX7D_PWM2_ROOT_CLK>;
755 clock-names = "ipg", "per";
761 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
762 reg = <0x30680000 0x10000>;
763 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
765 <&clks IMX7D_PWM3_ROOT_CLK>;
766 clock-names = "ipg", "per";
772 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
773 reg = <0x30690000 0x10000>;
774 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
776 <&clks IMX7D_PWM4_ROOT_CLK>;
777 clock-names = "ipg", "per";
783 compatible = "fsl,imx7-csi";
784 reg = <0x30710000 0x10000>;
785 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clks IMX7D_CLK_DUMMY>,
787 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
788 <&clks IMX7D_CLK_DUMMY>;
789 clock-names = "axi", "mclk", "dcic";
793 csi_from_csi_mux: endpoint {
794 remote-endpoint = <&csi_mux_to_csi>;
799 lcdif: lcdif@30730000 {
800 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
801 reg = <0x30730000 0x10000>;
802 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
804 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
805 clock-names = "pix", "axi";
809 mipi_csi: mipi-csi@30750000 {
810 compatible = "fsl,imx7-mipi-csi2";
811 reg = <0x30750000 0x10000>;
812 #address-cells = <1>;
814 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
816 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
817 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
818 clock-names = "pclk", "wrap", "phy";
819 power-domains = <&pgc_mipi_phy>;
820 phy-supply = <®_1p0d>;
821 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
822 reset-names = "mrst";
832 mipi_vc0_to_csi_mux: endpoint {
833 remote-endpoint = <&csi_mux_from_mipi_vc0>;
839 aips3: bus@30800000 {
840 compatible = "fsl,aips-bus", "simple-bus";
841 #address-cells = <1>;
843 reg = <0x30800000 0x400000>;
847 compatible = "fsl,spba-bus", "simple-bus";
848 #address-cells = <1>;
850 reg = <0x30800000 0x100000>;
853 ecspi1: spi@30820000 {
854 #address-cells = <1>;
856 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
857 reg = <0x30820000 0x10000>;
858 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
860 <&clks IMX7D_ECSPI1_ROOT_CLK>;
861 clock-names = "ipg", "per";
865 ecspi2: spi@30830000 {
866 #address-cells = <1>;
868 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
869 reg = <0x30830000 0x10000>;
870 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
872 <&clks IMX7D_ECSPI2_ROOT_CLK>;
873 clock-names = "ipg", "per";
877 ecspi3: spi@30840000 {
878 #address-cells = <1>;
880 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
881 reg = <0x30840000 0x10000>;
882 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
884 <&clks IMX7D_ECSPI3_ROOT_CLK>;
885 clock-names = "ipg", "per";
889 uart1: serial@30860000 {
890 compatible = "fsl,imx7d-uart",
892 reg = <0x30860000 0x10000>;
893 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
895 <&clks IMX7D_UART1_ROOT_CLK>;
896 clock-names = "ipg", "per";
900 uart2: serial@30890000 {
901 compatible = "fsl,imx7d-uart",
903 reg = <0x30890000 0x10000>;
904 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
906 <&clks IMX7D_UART2_ROOT_CLK>;
907 clock-names = "ipg", "per";
911 uart3: serial@30880000 {
912 compatible = "fsl,imx7d-uart",
914 reg = <0x30880000 0x10000>;
915 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
917 <&clks IMX7D_UART3_ROOT_CLK>;
918 clock-names = "ipg", "per";
923 #sound-dai-cells = <0>;
924 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
925 reg = <0x308a0000 0x10000>;
926 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
928 <&clks IMX7D_SAI1_ROOT_CLK>,
929 <&clks IMX7D_CLK_DUMMY>,
930 <&clks IMX7D_CLK_DUMMY>;
931 clock-names = "bus", "mclk1", "mclk2", "mclk3";
932 dma-names = "rx", "tx";
933 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
938 #sound-dai-cells = <0>;
939 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
940 reg = <0x308b0000 0x10000>;
941 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
943 <&clks IMX7D_SAI2_ROOT_CLK>,
944 <&clks IMX7D_CLK_DUMMY>,
945 <&clks IMX7D_CLK_DUMMY>;
946 clock-names = "bus", "mclk1", "mclk2", "mclk3";
947 dma-names = "rx", "tx";
948 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
953 #sound-dai-cells = <0>;
954 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
955 reg = <0x308c0000 0x10000>;
956 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
958 <&clks IMX7D_SAI3_ROOT_CLK>,
959 <&clks IMX7D_CLK_DUMMY>,
960 <&clks IMX7D_CLK_DUMMY>;
961 clock-names = "bus", "mclk1", "mclk2", "mclk3";
962 dma-names = "rx", "tx";
963 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
968 crypto: crypto@30900000 {
969 compatible = "fsl,sec-v4.0";
970 #address-cells = <1>;
972 reg = <0x30900000 0x40000>;
973 ranges = <0 0x30900000 0x40000>;
974 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&clks IMX7D_CAAM_CLK>,
976 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
977 clock-names = "ipg", "aclk";
980 compatible = "fsl,sec-v4.0-job-ring";
981 reg = <0x1000 0x1000>;
982 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
986 compatible = "fsl,sec-v4.0-job-ring";
987 reg = <0x2000 0x1000>;
988 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
992 compatible = "fsl,sec-v4.0-job-ring";
993 reg = <0x3000 0x1000>;
994 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
998 flexcan1: can@30a00000 {
999 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1000 reg = <0x30a00000 0x10000>;
1001 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clks IMX7D_CLK_DUMMY>,
1003 <&clks IMX7D_CAN1_ROOT_CLK>;
1004 clock-names = "ipg", "per";
1005 fsl,stop-mode = <&gpr 0x10 1>;
1006 status = "disabled";
1009 flexcan2: can@30a10000 {
1010 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1011 reg = <0x30a10000 0x10000>;
1012 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clks IMX7D_CLK_DUMMY>,
1014 <&clks IMX7D_CAN2_ROOT_CLK>;
1015 clock-names = "ipg", "per";
1016 fsl,stop-mode = <&gpr 0x10 2>;
1017 status = "disabled";
1020 i2c1: i2c@30a20000 {
1021 #address-cells = <1>;
1023 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1024 reg = <0x30a20000 0x10000>;
1025 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1027 status = "disabled";
1030 i2c2: i2c@30a30000 {
1031 #address-cells = <1>;
1033 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1034 reg = <0x30a30000 0x10000>;
1035 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1037 status = "disabled";
1040 i2c3: i2c@30a40000 {
1041 #address-cells = <1>;
1043 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1044 reg = <0x30a40000 0x10000>;
1045 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1047 status = "disabled";
1050 i2c4: i2c@30a50000 {
1051 #address-cells = <1>;
1053 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1054 reg = <0x30a50000 0x10000>;
1055 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1057 status = "disabled";
1060 uart4: serial@30a60000 {
1061 compatible = "fsl,imx7d-uart",
1063 reg = <0x30a60000 0x10000>;
1064 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1066 <&clks IMX7D_UART4_ROOT_CLK>;
1067 clock-names = "ipg", "per";
1068 status = "disabled";
1071 uart5: serial@30a70000 {
1072 compatible = "fsl,imx7d-uart",
1074 reg = <0x30a70000 0x10000>;
1075 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1077 <&clks IMX7D_UART5_ROOT_CLK>;
1078 clock-names = "ipg", "per";
1079 status = "disabled";
1082 uart6: serial@30a80000 {
1083 compatible = "fsl,imx7d-uart",
1085 reg = <0x30a80000 0x10000>;
1086 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1087 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1088 <&clks IMX7D_UART6_ROOT_CLK>;
1089 clock-names = "ipg", "per";
1090 status = "disabled";
1093 uart7: serial@30a90000 {
1094 compatible = "fsl,imx7d-uart",
1096 reg = <0x30a90000 0x10000>;
1097 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1099 <&clks IMX7D_UART7_ROOT_CLK>;
1100 clock-names = "ipg", "per";
1101 status = "disabled";
1104 mu0a: mailbox@30aa0000 {
1105 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1106 reg = <0x30aa0000 0x10000>;
1107 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1110 status = "disabled";
1113 mu0b: mailbox@30ab0000 {
1114 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1115 reg = <0x30ab0000 0x10000>;
1116 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1120 status = "disabled";
1123 usbotg1: usb@30b10000 {
1124 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1125 reg = <0x30b10000 0x200>;
1126 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1128 fsl,usbphy = <&usbphynop1>;
1129 fsl,usbmisc = <&usbmisc1 0>;
1130 phy-clkgate-delay-us = <400>;
1131 status = "disabled";
1134 usbh: usb@30b30000 {
1135 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1136 reg = <0x30b30000 0x200>;
1137 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1138 power-domains = <&pgc_hsic_phy>;
1139 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1140 fsl,usbphy = <&usbphynop3>;
1141 fsl,usbmisc = <&usbmisc3 0>;
1144 phy-clkgate-delay-us = <400>;
1145 status = "disabled";
1148 usbmisc1: usbmisc@30b10200 {
1150 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1151 reg = <0x30b10200 0x200>;
1154 usbmisc3: usbmisc@30b30200 {
1156 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1157 reg = <0x30b30200 0x200>;
1160 usdhc1: mmc@30b40000 {
1161 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1162 reg = <0x30b40000 0x10000>;
1163 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1165 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1166 <&clks IMX7D_USDHC1_ROOT_CLK>;
1167 clock-names = "ipg", "ahb", "per";
1169 status = "disabled";
1172 usdhc2: mmc@30b50000 {
1173 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1174 reg = <0x30b50000 0x10000>;
1175 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1176 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1177 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1178 <&clks IMX7D_USDHC2_ROOT_CLK>;
1179 clock-names = "ipg", "ahb", "per";
1181 status = "disabled";
1184 usdhc3: mmc@30b60000 {
1185 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1186 reg = <0x30b60000 0x10000>;
1187 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1189 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1190 <&clks IMX7D_USDHC3_ROOT_CLK>;
1191 clock-names = "ipg", "ahb", "per";
1193 status = "disabled";
1196 qspi: spi@30bb0000 {
1197 compatible = "fsl,imx7d-qspi";
1198 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1199 reg-names = "QuadSPI", "QuadSPI-memory";
1200 #address-cells = <1>;
1202 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1204 <&clks IMX7D_QSPI_ROOT_CLK>;
1205 clock-names = "qspi_en", "qspi";
1206 status = "disabled";
1209 sdma: sdma@30bd0000 {
1210 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1211 reg = <0x30bd0000 0x10000>;
1212 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1214 <&clks IMX7D_SDMA_CORE_CLK>;
1215 clock-names = "ipg", "ahb";
1217 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
1220 fec1: ethernet@30be0000 {
1221 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1222 reg = <0x30be0000 0x10000>;
1223 interrupt-names = "int0", "int1", "int2", "pps";
1224 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1229 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1230 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1231 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1232 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1233 clock-names = "ipg", "ahb", "ptp",
1234 "enet_clk_ref", "enet_out";
1235 fsl,num-tx-queues = <3>;
1236 fsl,num-rx-queues = <3>;
1237 fsl,stop-mode = <&gpr 0x10 3>;
1238 status = "disabled";
1242 dma_apbh: dma-apbh@33000000 {
1243 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1244 reg = <0x33000000 0x2000>;
1245 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1249 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1252 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1255 gpmi: nand-controller@33002000{
1256 compatible = "fsl,imx7d-gpmi-nand";
1257 #address-cells = <1>;
1259 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1260 reg-names = "gpmi-nand", "bch";
1261 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1262 interrupt-names = "bch";
1263 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1264 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1265 clock-names = "gpmi_io", "gpmi_bch_apb";
1266 dmas = <&dma_apbh 0>;
1267 dma-names = "rx-tx";
1268 status = "disabled";
1269 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1270 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;