arch/arm/boot/dts/imx7s.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4 // Copyright 2016 Toradex AG
   5
   6 #include <dt-bindings/clock/imx7d-clock.h>
   7 #include <dt-bindings/power/imx7-power.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include "imx7d-pinfunc.h"
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16         /*
  17          * The decompressor and also some bootloaders rely on a
  18          * pre-existing /chosen node to be available to insert the
  19          * command line and merge other ATAGS info.
  20          */
  21         chosen {};
  22
  23         aliases {
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 gpio4 = &gpio5;
  29                 gpio5 = &gpio6;
  30                 gpio6 = &gpio7;
  31                 i2c0 = &i2c1;
  32                 i2c1 = &i2c2;
  33                 i2c2 = &i2c3;
  34                 i2c3 = &i2c4;
  35                 mmc0 = &usdhc1;
  36                 mmc1 = &usdhc2;
  37                 mmc2 = &usdhc3;
  38                 serial0 = &uart1;
  39                 serial1 = &uart2;
  40                 serial2 = &uart3;
  41                 serial3 = &uart4;
  42                 serial4 = &uart5;
  43                 serial5 = &uart6;
  44                 serial6 = &uart7;
  45                 spi0 = &ecspi1;
  46                 spi1 = &ecspi2;
  47                 spi2 = &ecspi3;
  48                 spi3 = &ecspi4;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a7";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         clock-frequency = <792000000>;
  60                         clock-latency = <61036>; /* two CLK32 periods */
  61                         clocks = <&clks IMX7D_CLK_ARM>;
  62                 };
  63         };
  64
  65         ckil: clock-cki {
  66                 compatible = "fixed-clock";
  67                 #clock-cells = <0>;
  68                 clock-frequency = <32768>;
  69                 clock-output-names = "ckil";
  70         };
  71
  72         osc: clock-osc {
  73                 compatible = "fixed-clock";
  74                 #clock-cells = <0>;
  75                 clock-frequency = <24000000>;
  76                 clock-output-names = "osc";
  77         };
  78
  79         usbphynop1: usbphynop1 {
  80                 compatible = "usb-nop-xceiv";
  81                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
  82                 clock-names = "main_clk";
  83                 #phy-cells = <0>;
  84         };
  85
  86         usbphynop3: usbphynop3 {
  87                 compatible = "usb-nop-xceiv";
  88                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
  89                 clock-names = "main_clk";
  90                 #phy-cells = <0>;
  91         };
  92
  93         pmu {
  94                 compatible = "arm,cortex-a7-pmu";
  95                 interrupt-parent = <&gpc>;
  96                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  97                 interrupt-affinity = <&cpu0>;
  98         };
  99
 100         replicator {
 101                 /*
 102                  * non-configurable replicators don't show up on the
 103                  * AMBA bus.  As such no need to add "arm,primecell"
 104                  */
 105                 compatible = "arm,coresight-replicator";
 106
 107                 ports {
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                                 /* replicator output ports */
 111                         port@0 {
 112                                 reg = <0>;
 113                                 replicator_out_port0: endpoint {
 114                                         remote-endpoint = <&tpiu_in_port>;
 115                                 };
 116                         };
 117
 118                         port@1 {
 119                                 reg = <1>;
 120                                 replicator_out_port1: endpoint {
 121                                         remote-endpoint = <&etr_in_port>;
 122                                 };
 123                         };
 124
 125                         /* replicator input port */
 126                         port@2 {
 127                                 reg = <0>;
 128                                 replicator_in_port0: endpoint {
 129                                         slave-mode;
 130                                         remote-endpoint = <&etf_out_port>;
 131                                 };
 132                         };
 133                 };
 134         };
 135
 136         tempmon: tempmon {
 137                 compatible = "fsl,imx7d-tempmon";
 138                 interrupt-parent = <&gpc>;
 139                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 140                 fsl,tempmon =<&anatop>;
 141                 nvmem-cells = <&tempmon_calib>,
 142                         <&tempmon_temp_grade>;
 143                 nvmem-cell-names = "calib", "temp_grade";
 144                 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
 145         };
 146
 147         timer {
 148                 compatible = "arm,armv7-timer";
 149                 interrupt-parent = <&intc>;
 150                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 151                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 152                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 153                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 154         };
 155
 156         soc {
 157                 #address-cells = <1>;
 158                 #size-cells = <1>;
 159                 compatible = "simple-bus";
 160                 interrupt-parent = <&gpc>;
 161                 ranges;
 162
 163                 funnel@30041000 {
 164                         compatible = "arm,coresight-funnel", "arm,primecell";
 165                         reg = <0x30041000 0x1000>;
 166                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 167                         clock-names = "apb_pclk";
 168
 169                         ca_funnel_ports: ports {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172
 173                                 /* funnel input ports */
 174                                 port@0 {
 175                                         reg = <0>;
 176                                         ca_funnel_in_port0: endpoint {
 177                                                 slave-mode;
 178                                                 remote-endpoint = <&etm0_out_port>;
 179                                         };
 180                                 };
 181
 182                                 /* funnel output port */
 183                                 port@2 {
 184                                         reg = <0>;
 185                                         ca_funnel_out_port0: endpoint {
 186                                                 remote-endpoint = <&hugo_funnel_in_port0>;
 187                                         };
 188                                 };
 189
 190                                 /* the other input ports are not connect to anything */
 191                         };
 192                 };
 193
 194                 etm@3007c000 {
 195                         compatible = "arm,coresight-etm3x", "arm,primecell";
 196                         reg = <0x3007c000 0x1000>;
 197                         cpu = <&cpu0>;
 198                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 199                         clock-names = "apb_pclk";
 200
 201                         port {
 202                                 etm0_out_port: endpoint {
 203                                         remote-endpoint = <&ca_funnel_in_port0>;
 204                                 };
 205                         };
 206                 };
 207
 208                 funnel@30083000 {
 209                         compatible = "arm,coresight-funnel", "arm,primecell";
 210                         reg = <0x30083000 0x1000>;
 211                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 212                         clock-names = "apb_pclk";
 213
 214                         ports {
 215                                 #address-cells = <1>;
 216                                 #size-cells = <0>;
 217
 218                                 /* funnel input ports */
 219                                 port@0 {
 220                                         reg = <0>;
 221                                         hugo_funnel_in_port0: endpoint {
 222                                                 slave-mode;
 223                                                 remote-endpoint = <&ca_funnel_out_port0>;
 224                                         };
 225                                 };
 226
 227                                 port@1 {
 228                                         reg = <1>;
 229                                         hugo_funnel_in_port1: endpoint {
 230                                                 slave-mode; /* M4 input */
 231                                         };
 232                                 };
 233
 234                                 port@2 {
 235                                         reg = <0>;
 236                                         hugo_funnel_out_port0: endpoint {
 237                                                 remote-endpoint = <&etf_in_port>;
 238                                         };
 239                                 };
 240
 241                                 /* the other input ports are not connect to anything */
 242                         };
 243                 };
 244
 245                 etf@30084000 {
 246                         compatible = "arm,coresight-tmc", "arm,primecell";
 247                         reg = <0x30084000 0x1000>;
 248                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 249                         clock-names = "apb_pclk";
 250
 251                         ports {
 252                                 #address-cells = <1>;
 253                                 #size-cells = <0>;
 254
 255                                 port@0 {
 256                                         reg = <0>;
 257                                         etf_in_port: endpoint {
 258                                                 slave-mode;
 259                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 260                                         };
 261                                 };
 262
 263                                 port@1 {
 264                                         reg = <0>;
 265                                         etf_out_port: endpoint {
 266                                                 remote-endpoint = <&replicator_in_port0>;
 267                                         };
 268                                 };
 269                         };
 270                 };
 271
 272                 etr@30086000 {
 273                         compatible = "arm,coresight-tmc", "arm,primecell";
 274                         reg = <0x30086000 0x1000>;
 275                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 276                         clock-names = "apb_pclk";
 277
 278                         port {
 279                                 etr_in_port: endpoint {
 280                                         slave-mode;
 281                                         remote-endpoint = <&replicator_out_port1>;
 282                                 };
 283                         };
 284                 };
 285
 286                 tpiu@30087000 {
 287                         compatible = "arm,coresight-tpiu", "arm,primecell";
 288                         reg = <0x30087000 0x1000>;
 289                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 290                         clock-names = "apb_pclk";
 291
 292                         port {
 293                                 tpiu_in_port: endpoint {
 294                                         slave-mode;
 295                                         remote-endpoint = <&replicator_out_port0>;
 296                                 };
 297                         };
 298                 };
 299
 300                 intc: interrupt-controller@31001000 {
 301                         compatible = "arm,cortex-a7-gic";
 302                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 303                         #interrupt-cells = <3>;
 304                         interrupt-controller;
 305                         interrupt-parent = <&intc>;
 306                         reg = <0x31001000 0x1000>,
 307                               <0x31002000 0x2000>,
 308                               <0x31004000 0x2000>,
 309                               <0x31006000 0x2000>;
 310                 };
 311
 312                 aips1: aips-bus@30000000 {
 313                         compatible = "fsl,aips-bus", "simple-bus";
 314                         #address-cells = <1>;
 315                         #size-cells = <1>;
 316                         reg = <0x30000000 0x400000>;
 317                         ranges;
 318
 319                         gpio1: gpio@30200000 {
 320                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 321                                 reg = <0x30200000 0x10000>;
 322                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 323                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 324                                 gpio-controller;
 325                                 #gpio-cells = <2>;
 326                                 interrupt-controller;
 327                                 #interrupt-cells = <2>;
 328                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
 329                         };
 330
 331                         gpio2: gpio@30210000 {
 332                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 333                                 reg = <0x30210000 0x10000>;
 334                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 335                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 336                                 gpio-controller;
 337                                 #gpio-cells = <2>;
 338                                 interrupt-controller;
 339                                 #interrupt-cells = <2>;
 340                                 gpio-ranges = <&iomuxc 0 13 32>;
 341                         };
 342
 343                         gpio3: gpio@30220000 {
 344                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 345                                 reg = <0x30220000 0x10000>;
 346                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 347                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 348                                 gpio-controller;
 349                                 #gpio-cells = <2>;
 350                                 interrupt-controller;
 351                                 #interrupt-cells = <2>;
 352                                 gpio-ranges = <&iomuxc 0 45 29>;
 353                         };
 354
 355                         gpio4: gpio@30230000 {
 356                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 357                                 reg = <0x30230000 0x10000>;
 358                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 359                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 360                                 gpio-controller;
 361                                 #gpio-cells = <2>;
 362                                 interrupt-controller;
 363                                 #interrupt-cells = <2>;
 364                                 gpio-ranges = <&iomuxc 0 74 24>;
 365                         };
 366
 367                         gpio5: gpio@30240000 {
 368                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 369                                 reg = <0x30240000 0x10000>;
 370                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 371                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 372                                 gpio-controller;
 373                                 #gpio-cells = <2>;
 374                                 interrupt-controller;
 375                                 #interrupt-cells = <2>;
 376                                 gpio-ranges = <&iomuxc 0 98 18>;
 377                         };
 378
 379                         gpio6: gpio@30250000 {
 380                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 381                                 reg = <0x30250000 0x10000>;
 382                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 383                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 384                                 gpio-controller;
 385                                 #gpio-cells = <2>;
 386                                 interrupt-controller;
 387                                 #interrupt-cells = <2>;
 388                                 gpio-ranges = <&iomuxc 0 116 23>;
 389                         };
 390
 391                         gpio7: gpio@30260000 {
 392                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 393                                 reg = <0x30260000 0x10000>;
 394                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 395                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 396                                 gpio-controller;
 397                                 #gpio-cells = <2>;
 398                                 interrupt-controller;
 399                                 #interrupt-cells = <2>;
 400                                 gpio-ranges = <&iomuxc 0 139 16>;
 401                         };
 402
 403                         wdog1: wdog@30280000 {
 404                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 405                                 reg = <0x30280000 0x10000>;
 406                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 407                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 408                         };
 409
 410                         wdog2: wdog@30290000 {
 411                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 412                                 reg = <0x30290000 0x10000>;
 413                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 414                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 415                                 status = "disabled";
 416                         };
 417
 418                         wdog3: wdog@302a0000 {
 419                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 420                                 reg = <0x302a0000 0x10000>;
 421                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 422                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 423                                 status = "disabled";
 424                         };
 425
 426                         wdog4: wdog@302b0000 {
 427                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 428                                 reg = <0x302b0000 0x10000>;
 429                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 430                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 431                                 status = "disabled";
 432                         };
 433
 434                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
 435                                 compatible = "fsl,imx7d-iomuxc-lpsr";
 436                                 reg = <0x302c0000 0x10000>;
 437                                 fsl,input-sel = <&iomuxc>;
 438                         };
 439
 440                         gpt1: gpt@302d0000 {
 441                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 442                                 reg = <0x302d0000 0x10000>;
 443                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 444                                 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
 445                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 446                                 clock-names = "ipg", "per";
 447                         };
 448
 449                         gpt2: gpt@302e0000 {
 450                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 451                                 reg = <0x302e0000 0x10000>;
 452                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
 454                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 455                                 clock-names = "ipg", "per";
 456                                 status = "disabled";
 457                         };
 458
 459                         gpt3: gpt@302f0000 {
 460                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 461                                 reg = <0x302f0000 0x10000>;
 462                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 463                                 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
 464                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 465                                 clock-names = "ipg", "per";
 466                                 status = "disabled";
 467                         };
 468
 469                         gpt4: gpt@30300000 {
 470                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 471                                 reg = <0x30300000 0x10000>;
 472                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 473                                 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
 474                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 475                                 clock-names = "ipg", "per";
 476                                 status = "disabled";
 477                         };
 478
 479                         kpp: kpp@30320000 {
 480                                 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
 481                                 reg = <0x30320000 0x10000>;
 482                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
 484                                 status = "disabled";
 485                         };
 486
 487                         iomuxc: iomuxc@30330000 {
 488                                 compatible = "fsl,imx7d-iomuxc";
 489                                 reg = <0x30330000 0x10000>;
 490                         };
 491
 492                         gpr: iomuxc-gpr@30340000 {
 493                                 compatible = "fsl,imx7d-iomuxc-gpr",
 494                                         "fsl,imx6q-iomuxc-gpr", "syscon";
 495                                 reg = <0x30340000 0x10000>;
 496                         };
 497
 498                         ocotp: ocotp-ctrl@30350000 {
 499                                 #address-cells = <1>;
 500                                 #size-cells = <1>;
 501                                 compatible = "fsl,imx7d-ocotp", "syscon";
 502                                 reg = <0x30350000 0x10000>;
 503                                 clocks = <&clks IMX7D_OCOTP_CLK>;
 504
 505                                 tempmon_calib: calib@3c {
 506                                         reg = <0x3c 0x4>;
 507                                 };
 508
 509                                 tempmon_temp_grade: temp-grade@10 {
 510                                         reg = <0x10 0x4>;
 511                                 };
 512                         };
 513
 514                         anatop: anatop@30360000 {
 515                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 516                                         "syscon", "simple-bus";
 517                                 reg = <0x30360000 0x10000>;
 518                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 519                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 520
 521                                 reg_1p0d: regulator-vdd1p0d {
 522                                         compatible = "fsl,anatop-regulator";
 523                                         regulator-name = "vdd1p0d";
 524                                         regulator-min-microvolt = <800000>;
 525                                         regulator-max-microvolt = <1200000>;
 526                                         anatop-reg-offset = <0x210>;
 527                                         anatop-vol-bit-shift = <8>;
 528                                         anatop-vol-bit-width = <5>;
 529                                         anatop-min-bit-val = <8>;
 530                                         anatop-min-voltage = <800000>;
 531                                         anatop-max-voltage = <1200000>;
 532                                         anatop-enable-bit = <0>;
 533                                 };
 534
 535                                 reg_1p2: regulator-vdd1p2 {
 536                                         compatible = "fsl,anatop-regulator";
 537                                         regulator-name = "vdd1p2";
 538                                         regulator-min-microvolt = <1100000>;
 539                                         regulator-max-microvolt = <1300000>;
 540                                         anatop-reg-offset = <0x220>;
 541                                         anatop-vol-bit-shift = <8>;
 542                                         anatop-vol-bit-width = <5>;
 543                                         anatop-min-bit-val = <0x14>;
 544                                         anatop-min-voltage = <1100000>;
 545                                         anatop-max-voltage = <1300000>;
 546                                         anatop-enable-bit = <0>;
 547                                 };
 548                         };
 549
 550                         snvs: snvs@30370000 {
 551                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 552                                 reg = <0x30370000 0x10000>;
 553
 554                                 snvs_rtc: snvs-rtc-lp {
 555                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 556                                         regmap = <&snvs>;
 557                                         offset = <0x34>;
 558                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 559                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 560                                         clocks = <&clks IMX7D_SNVS_CLK>;
 561                                         clock-names = "snvs-rtc";
 562                                 };
 563
 564                                 snvs_poweroff: snvs-poweroff {
 565                                         compatible = "syscon-poweroff";
 566                                         regmap = <&snvs>;
 567                                         offset = <0x38>;
 568                                         value = <0x60>;
 569                                         mask = <0x60>;
 570                                 };
 571
 572                                 snvs_pwrkey: snvs-powerkey {
 573                                         compatible = "fsl,sec-v4.0-pwrkey";
 574                                         regmap = <&snvs>;
 575                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 576                                         linux,keycode = <KEY_POWER>;
 577                                         wakeup-source;
 578                                 };
 579                         };
 580
 581                         clks: ccm@30380000 {
 582                                 compatible = "fsl,imx7d-ccm";
 583                                 reg = <0x30380000 0x10000>;
 584                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 585                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 586                                 #clock-cells = <1>;
 587                                 clocks = <&ckil>, <&osc>;
 588                                 clock-names = "ckil", "osc";
 589                         };
 590
 591                         src: src@30390000 {
 592                                 compatible = "fsl,imx7d-src", "syscon";
 593                                 reg = <0x30390000 0x10000>;
 594                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 595                                 #reset-cells = <1>;
 596                         };
 597
 598                         gpc: gpc@303a0000 {
 599                                 compatible = "fsl,imx7d-gpc";
 600                                 reg = <0x303a0000 0x10000>;
 601                                 interrupt-controller;
 602                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 603                                 #interrupt-cells = <3>;
 604                                 interrupt-parent = <&intc>;
 605                                 #power-domain-cells = <1>;
 606
 607                                 pgc {
 608                                         #address-cells = <1>;
 609                                         #size-cells = <0>;
 610
 611                                         pgc_pcie_phy: pgc-power-domain@1 {
 612                                                 #power-domain-cells = <0>;
 613                                                 reg = <1>;
 614                                                 power-supply = <&reg_1p0d>;
 615                                         };
 616                                 };
 617                         };
 618                 };
 619
 620                 aips2: aips-bus@30400000 {
 621                         compatible = "fsl,aips-bus", "simple-bus";
 622                         #address-cells = <1>;
 623                         #size-cells = <1>;
 624                         reg = <0x30400000 0x400000>;
 625                         ranges;
 626
 627                         adc1: adc@30610000 {
 628                                 compatible = "fsl,imx7d-adc";
 629                                 reg = <0x30610000 0x10000>;
 630                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 631                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 632                                 clock-names = "adc";
 633                                 status = "disabled";
 634                         };
 635
 636                         adc2: adc@30620000 {
 637                                 compatible = "fsl,imx7d-adc";
 638                                 reg = <0x30620000 0x10000>;
 639                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 640                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 641                                 clock-names = "adc";
 642                                 status = "disabled";
 643                         };
 644
 645                         ecspi4: ecspi@30630000 {
 646                                 #address-cells = <1>;
 647                                 #size-cells = <0>;
 648                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 649                                 reg = <0x30630000 0x10000>;
 650                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 651                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 652                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
 653                                 clock-names = "ipg", "per";
 654                                 status = "disabled";
 655                         };
 656
 657                         pwm1: pwm@30660000 {
 658                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 659                                 reg = <0x30660000 0x10000>;
 660                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 661                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 662                                          <&clks IMX7D_PWM1_ROOT_CLK>;
 663                                 clock-names = "ipg", "per";
 664                                 #pwm-cells = <3>;
 665                                 status = "disabled";
 666                         };
 667
 668                         pwm2: pwm@30670000 {
 669                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 670                                 reg = <0x30670000 0x10000>;
 671                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 672                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 673                                          <&clks IMX7D_PWM2_ROOT_CLK>;
 674                                 clock-names = "ipg", "per";
 675                                 #pwm-cells = <3>;
 676                                 status = "disabled";
 677                         };
 678
 679                         pwm3: pwm@30680000 {
 680                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 681                                 reg = <0x30680000 0x10000>;
 682                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 683                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 684                                          <&clks IMX7D_PWM3_ROOT_CLK>;
 685                                 clock-names = "ipg", "per";
 686                                 #pwm-cells = <3>;
 687                                 status = "disabled";
 688                         };
 689
 690                         pwm4: pwm@30690000 {
 691                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 692                                 reg = <0x30690000 0x10000>;
 693                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 695                                          <&clks IMX7D_PWM4_ROOT_CLK>;
 696                                 clock-names = "ipg", "per";
 697                                 #pwm-cells = <3>;
 698                                 status = "disabled";
 699                         };
 700
 701                         lcdif: lcdif@30730000 {
 702                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 703                                 reg = <0x30730000 0x10000>;
 704                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
 706                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
 707                                 clock-names = "pix", "axi";
 708                                 status = "disabled";
 709                         };
 710                 };
 711
 712                 aips3: aips-bus@30800000 {
 713                         compatible = "fsl,aips-bus", "simple-bus";
 714                         #address-cells = <1>;
 715                         #size-cells = <1>;
 716                         reg = <0x30800000 0x400000>;
 717                         ranges;
 718
 719                         spba-bus@30800000 {
 720                                 compatible = "fsl,spba-bus", "simple-bus";
 721                                 #address-cells = <1>;
 722                                 #size-cells = <1>;
 723                                 reg = <0x30800000 0x100000>;
 724                                 ranges;
 725
 726                                 ecspi1: ecspi@30820000 {
 727                                         #address-cells = <1>;
 728                                         #size-cells = <0>;
 729                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 730                                         reg = <0x30820000 0x10000>;
 731                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 732                                         clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 733                                                 <&clks IMX7D_ECSPI1_ROOT_CLK>;
 734                                         clock-names = "ipg", "per";
 735                                         status = "disabled";
 736                                 };
 737
 738                                 ecspi2: ecspi@30830000 {
 739                                         #address-cells = <1>;
 740                                         #size-cells = <0>;
 741                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 742                                         reg = <0x30830000 0x10000>;
 743                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 744                                         clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 745                                                 <&clks IMX7D_ECSPI2_ROOT_CLK>;
 746                                         clock-names = "ipg", "per";
 747                                         status = "disabled";
 748                                 };
 749
 750                                 ecspi3: ecspi@30840000 {
 751                                         #address-cells = <1>;
 752                                         #size-cells = <0>;
 753                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 754                                         reg = <0x30840000 0x10000>;
 755                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 756                                         clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 757                                                 <&clks IMX7D_ECSPI3_ROOT_CLK>;
 758                                         clock-names = "ipg", "per";
 759                                         status = "disabled";
 760                                 };
 761
 762                                 uart1: serial@30860000 {
 763                                         compatible = "fsl,imx7d-uart",
 764                                                      "fsl,imx6q-uart";
 765                                         reg = <0x30860000 0x10000>;
 766                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 767                                         clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 768                                                 <&clks IMX7D_UART1_ROOT_CLK>;
 769                                         clock-names = "ipg", "per";
 770                                         status = "disabled";
 771                                 };
 772
 773                                 uart2: serial@30890000 {
 774                                         compatible = "fsl,imx7d-uart",
 775                                                      "fsl,imx6q-uart";
 776                                         reg = <0x30890000 0x10000>;
 777                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 778                                         clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 779                                                 <&clks IMX7D_UART2_ROOT_CLK>;
 780                                         clock-names = "ipg", "per";
 781                                         status = "disabled";
 782                                 };
 783
 784                                 uart3: serial@30880000 {
 785                                         compatible = "fsl,imx7d-uart",
 786                                                      "fsl,imx6q-uart";
 787                                         reg = <0x30880000 0x10000>;
 788                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 789                                         clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 790                                                 <&clks IMX7D_UART3_ROOT_CLK>;
 791                                         clock-names = "ipg", "per";
 792                                         status = "disabled";
 793                                 };
 794
 795                                 sai1: sai@308a0000 {
 796                                         #sound-dai-cells = <0>;
 797                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 798                                         reg = <0x308a0000 0x10000>;
 799                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 800                                         clocks = <&clks IMX7D_SAI1_IPG_CLK>,
 801                                                  <&clks IMX7D_SAI1_ROOT_CLK>,
 802                                                  <&clks IMX7D_CLK_DUMMY>,
 803                                                  <&clks IMX7D_CLK_DUMMY>;
 804                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 805                                         dma-names = "rx", "tx";
 806                                         dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
 807                                         status = "disabled";
 808                                 };
 809
 810                                 sai2: sai@308b0000 {
 811                                         #sound-dai-cells = <0>;
 812                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 813                                         reg = <0x308b0000 0x10000>;
 814                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 815                                         clocks = <&clks IMX7D_SAI2_IPG_CLK>,
 816                                                  <&clks IMX7D_SAI2_ROOT_CLK>,
 817                                                  <&clks IMX7D_CLK_DUMMY>,
 818                                                  <&clks IMX7D_CLK_DUMMY>;
 819                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 820                                         dma-names = "rx", "tx";
 821                                         dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
 822                                         status = "disabled";
 823                                 };
 824
 825                                 sai3: sai@308c0000 {
 826                                         #sound-dai-cells = <0>;
 827                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 828                                         reg = <0x308c0000 0x10000>;
 829                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 830                                         clocks = <&clks IMX7D_SAI3_IPG_CLK>,
 831                                                  <&clks IMX7D_SAI3_ROOT_CLK>,
 832                                                  <&clks IMX7D_CLK_DUMMY>,
 833                                                  <&clks IMX7D_CLK_DUMMY>;
 834                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 835                                         dma-names = "rx", "tx";
 836                                         dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
 837                                         status = "disabled";
 838                                 };
 839                         };
 840
 841                         crypto: caam@30900000 {
 842                                 compatible = "fsl,sec-v4.0";
 843                                 #address-cells = <1>;
 844                                 #size-cells = <1>;
 845                                 reg = <0x30900000 0x40000>;
 846                                 ranges = <0 0x30900000 0x40000>;
 847                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 848                                 clocks = <&clks IMX7D_CAAM_CLK>,
 849                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
 850                                 clock-names = "ipg", "aclk";
 851
 852                                 sec_jr0: jr0@1000 {
 853                                         compatible = "fsl,sec-v4.0-job-ring";
 854                                         reg = <0x1000 0x1000>;
 855                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 856                                 };
 857
 858                                 sec_jr1: jr1@2000 {
 859                                         compatible = "fsl,sec-v4.0-job-ring";
 860                                         reg = <0x2000 0x1000>;
 861                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 862                                 };
 863
 864                                 sec_jr2: jr1@3000 {
 865                                         compatible = "fsl,sec-v4.0-job-ring";
 866                                         reg = <0x3000 0x1000>;
 867                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 868                                 };
 869                         };
 870
 871                         flexcan1: can@30a00000 {
 872                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 873                                 reg = <0x30a00000 0x10000>;
 874                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 875                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 876                                         <&clks IMX7D_CAN1_ROOT_CLK>;
 877                                 clock-names = "ipg", "per";
 878                                 status = "disabled";
 879                         };
 880
 881                         flexcan2: can@30a10000 {
 882                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 883                                 reg = <0x30a10000 0x10000>;
 884                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 885                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 886                                         <&clks IMX7D_CAN2_ROOT_CLK>;
 887                                 clock-names = "ipg", "per";
 888                                 status = "disabled";
 889                         };
 890
 891                         i2c1: i2c@30a20000 {
 892                                 #address-cells = <1>;
 893                                 #size-cells = <0>;
 894                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 895                                 reg = <0x30a20000 0x10000>;
 896                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 897                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
 898                                 status = "disabled";
 899                         };
 900
 901                         i2c2: i2c@30a30000 {
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 905                                 reg = <0x30a30000 0x10000>;
 906                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 907                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
 908                                 status = "disabled";
 909                         };
 910
 911                         i2c3: i2c@30a40000 {
 912                                 #address-cells = <1>;
 913                                 #size-cells = <0>;
 914                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 915                                 reg = <0x30a40000 0x10000>;
 916                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 917                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
 918                                 status = "disabled";
 919                         };
 920
 921                         i2c4: i2c@30a50000 {
 922                                 #address-cells = <1>;
 923                                 #size-cells = <0>;
 924                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 925                                 reg = <0x30a50000 0x10000>;
 926                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 927                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
 928                                 status = "disabled";
 929                         };
 930
 931                         uart4: serial@30a60000 {
 932                                 compatible = "fsl,imx7d-uart",
 933                                              "fsl,imx6q-uart";
 934                                 reg = <0x30a60000 0x10000>;
 935                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 936                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
 937                                         <&clks IMX7D_UART4_ROOT_CLK>;
 938                                 clock-names = "ipg", "per";
 939                                 status = "disabled";
 940                         };
 941
 942                         uart5: serial@30a70000 {
 943                                 compatible = "fsl,imx7d-uart",
 944                                              "fsl,imx6q-uart";
 945                                 reg = <0x30a70000 0x10000>;
 946                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 947                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
 948                                         <&clks IMX7D_UART5_ROOT_CLK>;
 949                                 clock-names = "ipg", "per";
 950                                 status = "disabled";
 951                         };
 952
 953                         uart6: serial@30a80000 {
 954                                 compatible = "fsl,imx7d-uart",
 955                                              "fsl,imx6q-uart";
 956                                 reg = <0x30a80000 0x10000>;
 957                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 958                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
 959                                         <&clks IMX7D_UART6_ROOT_CLK>;
 960                                 clock-names = "ipg", "per";
 961                                 status = "disabled";
 962                         };
 963
 964                         uart7: serial@30a90000 {
 965                                 compatible = "fsl,imx7d-uart",
 966                                              "fsl,imx6q-uart";
 967                                 reg = <0x30a90000 0x10000>;
 968                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 969                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
 970                                         <&clks IMX7D_UART7_ROOT_CLK>;
 971                                 clock-names = "ipg", "per";
 972                                 status = "disabled";
 973                         };
 974
 975                         usbotg1: usb@30b10000 {
 976                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 977                                 reg = <0x30b10000 0x200>;
 978                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 979                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 980                                 fsl,usbphy = <&usbphynop1>;
 981                                 fsl,usbmisc = <&usbmisc1 0>;
 982                                 phy-clkgate-delay-us = <400>;
 983                                 status = "disabled";
 984                         };
 985
 986                         usbh: usb@30b30000 {
 987                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 988                                 reg = <0x30b30000 0x200>;
 989                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 990                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 991                                 fsl,usbphy = <&usbphynop3>;
 992                                 fsl,usbmisc = <&usbmisc3 0>;
 993                                 phy_type = "hsic";
 994                                 dr_mode = "host";
 995                                 phy-clkgate-delay-us = <400>;
 996                                 status = "disabled";
 997                         };
 998
 999                         usbmisc1: usbmisc@30b10200 {
1000                                 #index-cells = <1>;
1001                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1002                                 reg = <0x30b10200 0x200>;
1003                         };
1004
1005                         usbmisc3: usbmisc@30b30200 {
1006                                 #index-cells = <1>;
1007                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1008                                 reg = <0x30b30200 0x200>;
1009                         };
1010
1011                         usdhc1: usdhc@30b40000 {
1012                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1013                                 reg = <0x30b40000 0x10000>;
1014                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1015                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1016                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1017                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
1018                                 clock-names = "ipg", "ahb", "per";
1019                                 bus-width = <4>;
1020                                 status = "disabled";
1021                         };
1022
1023                         usdhc2: usdhc@30b50000 {
1024                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1025                                 reg = <0x30b50000 0x10000>;
1026                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1027                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1028                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1029                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
1030                                 clock-names = "ipg", "ahb", "per";
1031                                 bus-width = <4>;
1032                                 status = "disabled";
1033                         };
1034
1035                         usdhc3: usdhc@30b60000 {
1036                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1037                                 reg = <0x30b60000 0x10000>;
1038                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1039                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1040                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1041                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
1042                                 clock-names = "ipg", "ahb", "per";
1043                                 bus-width = <4>;
1044                                 status = "disabled";
1045                         };
1046
1047                         sdma: sdma@30bd0000 {
1048                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1049                                 reg = <0x30bd0000 0x10000>;
1050                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1051                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1052                                          <&clks IMX7D_SDMA_CORE_CLK>;
1053                                 clock-names = "ipg", "ahb";
1054                                 #dma-cells = <3>;
1055                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
1056                         };
1057
1058                         fec1: ethernet@30be0000 {
1059                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1060                                 reg = <0x30be0000 0x10000>;
1061                                 interrupt-names = "int0", "int1", "int2", "pps";
1062                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1063                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1064                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1065                                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1066                                 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1067                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1068                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1069                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1070                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1071                                 clock-names = "ipg", "ahb", "ptp",
1072                                         "enet_clk_ref", "enet_out";
1073                                 fsl,num-tx-queues=<3>;
1074                                 fsl,num-rx-queues=<3>;
1075                                 status = "disabled";
1076                         };
1077                 };
1078
1079                 dma_apbh: dma-apbh@33000000 {
1080                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1081                         reg = <0x33000000 0x2000>;
1082                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1083                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1084                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1085                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1086                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1087                         #dma-cells = <1>;
1088                         dma-channels = <4>;
1089                         clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1090                 };
1091
1092                 gpmi: gpmi-nand@33002000{
1093                         compatible = "fsl,imx7d-gpmi-nand";
1094                         #address-cells = <1>;
1095                         #size-cells = <1>;
1096                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1097                         reg-names = "gpmi-nand", "bch";
1098                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1099                         interrupt-names = "bch";
1100                         clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1101                                 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1102                         clock-names = "gpmi_io", "gpmi_bch_apb";
1103                         dmas = <&dma_apbh 0>;
1104                         dma-names = "rx-tx";
1105                         status = "disabled";
1106                         assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1107                         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1108                 };
1109         };
1110 };