arch/arm/boot/dts/imx7d.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4 // Copyright 2016 Toradex AG
   5
   6 #include "imx7s.dtsi"
   7 #include <dt-bindings/reset/imx7-reset.h>
   8
   9 / {
  10         aliases {
  11                 usb0 = &usbotg1;
  12                 usb1 = &usbotg2;
  13                 usb2 = &usbh;
  14         };
  15
  16         cpus {
  17                 cpu0: cpu@0 {
  18                         clock-frequency = <996000000>;
  19                         operating-points-v2 = <&cpu0_opp_table>;
  20                         #cooling-cells = <2>;
  21                         nvmem-cells = <&cpu_speed_grade>;
  22                         nvmem-cell-names = "speed_grade";
  23                 };
  24
  25                 cpu1: cpu@1 {
  26                         compatible = "arm,cortex-a7";
  27                         device_type = "cpu";
  28                         reg = <1>;
  29                         clock-frequency = <996000000>;
  30                         operating-points-v2 = <&cpu0_opp_table>;
  31                         cpu-idle-states = <&cpu_sleep_wait>;
  32                 };
  33         };
  34
  35         timer {
  36                 compatible = "arm,armv7-timer";
  37                 interrupt-parent = <&intc>;
  38                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  39                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  40                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  41                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  42         };
  43
  44         cpu0_opp_table: opp-table {
  45                 compatible = "operating-points-v2";
  46                 opp-shared;
  47
  48                 opp-792000000 {
  49                         opp-hz = /bits/ 64 <792000000>;
  50                         opp-microvolt = <1000000>;
  51                         clock-latency-ns = <150000>;
  52                         opp-supported-hw = <0xf>, <0xf>;
  53                 };
  54
  55                 opp-996000000 {
  56                         opp-hz = /bits/ 64 <996000000>;
  57                         opp-microvolt = <1100000>;
  58                         clock-latency-ns = <150000>;
  59                         opp-supported-hw = <0xc>, <0xf>;
  60                 };
  61
  62                 opp-1200000000 {
  63                         opp-hz = /bits/ 64 <1200000000>;
  64                         opp-microvolt = <1225000>;
  65                         clock-latency-ns = <150000>;
  66                         opp-supported-hw = <0x8>, <0xf>;
  67                 };
  68         };
  69
  70         usbphynop2: usbphynop2 {
  71                 compatible = "usb-nop-xceiv";
  72                 clocks = <&clks IMX7D_USB_PHY2_CLK>;
  73                 clock-names = "main_clk";
  74                 #phy-cells = <0>;
  75         };
  76
  77         soc {
  78                 etm@3007d000 {
  79                         compatible = "arm,coresight-etm3x", "arm,primecell";
  80                         reg = <0x3007d000 0x1000>;
  81
  82                         /*
  83                          * System will hang if added nosmp in kernel command line
  84                          * without arm,primecell-periphid because amba bus try to
  85                          * read id and core1 power off at this time.
  86                          */
  87                         arm,primecell-periphid = <0xbb956>;
  88                         cpu = <&cpu1>;
  89                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
  90                         clock-names = "apb_pclk";
  91
  92                         out-ports {
  93                                 port {
  94                                         etm1_out_port: endpoint {
  95                                                 remote-endpoint = <&ca_funnel_in_port1>;
  96                                         };
  97                                 };
  98                         };
  99                 };
 100
 101                 intc: interrupt-controller@31001000 {
 102                         compatible = "arm,cortex-a7-gic";
 103                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 104                         #interrupt-cells = <3>;
 105                         interrupt-controller;
 106                         interrupt-parent = <&intc>;
 107                         reg = <0x31001000 0x1000>,
 108                               <0x31002000 0x2000>,
 109                               <0x31004000 0x2000>,
 110                               <0x31006000 0x2000>;
 111                 };
 112         };
 113 };
 114
 115 &aips2 {
 116         pcie_phy: pcie-phy@306d0000 {
 117                   compatible = "fsl,imx7d-pcie-phy";
 118                   reg = <0x306d0000 0x10000>;
 119                   status = "disabled";
 120         };
 121 };
 122
 123 &aips3 {
 124         usbotg2: usb@30b20000 {
 125                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 126                 reg = <0x30b20000 0x200>;
 127                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 128                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 129                 fsl,usbphy = <&usbphynop2>;
 130                 fsl,usbmisc = <&usbmisc2 0>;
 131                 phy-clkgate-delay-us = <400>;
 132                 status = "disabled";
 133         };
 134
 135         usbmisc2: usbmisc@30b20200 {
 136                 #index-cells = <1>;
 137                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 138                 reg = <0x30b20200 0x200>;
 139         };
 140
 141         fec2: ethernet@30bf0000 {
 142                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
 143                 reg = <0x30bf0000 0x10000>;
 144                 interrupt-names = "int0", "int1", "int2", "pps";
 145                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 146                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 147                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 148                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 149                 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
 150                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 151                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
 152                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
 153                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
 154                 clock-names = "ipg", "ahb", "ptp",
 155                         "enet_clk_ref", "enet_out";
 156                 fsl,num-tx-queues = <3>;
 157                 fsl,num-rx-queues = <3>;
 158                 status = "disabled";
 159         };
 160
 161         pcie: pcie@33800000 {
 162                 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
 163                 reg = <0x33800000 0x4000>,
 164                       <0x4ff00000 0x80000>;
 165                 reg-names = "dbi", "config";
 166                 #address-cells = <3>;
 167                 #size-cells = <2>;
 168                 device_type = "pci";
 169                 bus-range = <0x00 0xff>;
 170                 ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
 171                           0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
 172                 num-lanes = <1>;
 173                 num-viewport = <4>;
 174                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 175                 interrupt-names = "msi";
 176                 #interrupt-cells = <1>;
 177                 interrupt-map-mask = <0 0 0 0x7>;
 178                 /*
 179                  * Reference manual lists pci irqs incorrectly
 180                  * Real hardware ordering is same as imx6: D+MSI, C, B, A
 181                  */
 182                 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 183                                 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 184                                 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 185                                 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
 187                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
 188                          <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
 189                 clock-names = "pcie", "pcie_bus", "pcie_phy";
 190                 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
 191                                   <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
 192                 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
 193                                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 194
 195                 fsl,max-link-speed = <2>;
 196                 power-domains = <&pgc_pcie_phy>;
 197                 resets = <&src IMX7_RESET_PCIEPHY>,
 198                          <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
 199                          <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
 200                 reset-names = "pciephy", "apps", "turnoff";
 201                 fsl,imx7d-pcie-phy = <&pcie_phy>;
 202                 status = "disabled";
 203         };
 204 };
 205
 206 &ca_funnel_in_ports {
 207         port@1 {
 208                 reg = <1>;
 209                 ca_funnel_in_port1: endpoint {
 210                         remote-endpoint = <&etm1_out_port>;
 211                 };
 212         };
 213 };