1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
10 model = "Freescale i.MX7 SabreSD Board";
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
18 device_type = "memory";
19 reg = <0x80000000 0x80000000>;
23 compatible = "gpio-keys";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_VOLUMEUP>;
34 label = "Volume Down";
35 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
36 linux,code = <KEY_VOLUMEDOWN>;
41 compatible = "spi-gpio";
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_spi4>;
44 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
45 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
46 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
47 num-chipselects = <1>;
51 extended_io: gpio-expander@0 {
52 compatible = "fairchild,74hc595";
56 registers-number = <1>;
57 spi-max-frequency = <100000>;
61 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
62 compatible = "regulator-fixed";
63 regulator-name = "usb_otg1_vbus";
64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>;
66 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
70 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
71 compatible = "regulator-fixed";
72 regulator-name = "usb_otg2_vbus";
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
79 reg_vref_1v8: regulator-vref-1v8 {
80 compatible = "regulator-fixed";
81 regulator-name = "vref-1v8";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
86 reg_brcm: regulator-brcm {
87 compatible = "regulator-fixed";
88 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
90 regulator-name = "brcm_reg";
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_brcm_reg>;
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 startup-delay-us = <200000>;
98 reg_lcd_3v3: regulator-lcd-3v3 {
99 compatible = "regulator-fixed";
100 regulator-name = "lcd-3v3";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
106 reg_can2_3v3: regulator-can2-3v3 {
107 compatible = "regulator-fixed";
108 regulator-name = "can2-3v3";
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_flexcan2_reg>;
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
116 backlight: backlight {
117 compatible = "pwm-backlight";
118 pwms = <&pwm1 0 5000000 0>;
119 brightness-levels = <0 4 8 16 32 64 128 255>;
120 default-brightness-level = <6>;
125 compatible = "innolux,at043tn24";
126 backlight = <&backlight>;
127 power-supply = <®_lcd_3v3>;
131 remote-endpoint = <&display_out>;
138 vref-supply = <®_vref_1v8>;
143 vref-supply = <®_vref_1v8>;
148 cpu-supply = <&sw1a_reg>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_ecspi3>;
154 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
158 compatible = "ti,tsc2046";
160 spi-max-frequency = <1000000>;
161 pinctrl-names ="default";
162 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
163 interrupt-parent = <&gpio2>;
165 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
166 touchscreen-max-pressure = <255>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_enet1>;
174 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
175 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
176 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
177 assigned-clock-rates = <0>, <100000000>;
179 phy-handle = <ðphy0>;
181 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
185 #address-cells = <1>;
188 ethphy0: ethernet-phy@0 {
192 ethphy1: ethernet-phy@1 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_enet2>;
201 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
202 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
203 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
204 assigned-clock-rates = <0>, <100000000>;
206 phy-handle = <ðphy1>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_flexcan2>;
214 xceiver-supply = <®_can2_3v3>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c1>;
224 compatible = "fsl,pfuze3000";
229 regulator-min-microvolt = <700000>;
230 regulator-max-microvolt = <1475000>;
233 regulator-ramp-delay = <6250>;
236 /* use sw1c_reg to align with pfuze100/pfuze200 */
238 regulator-min-microvolt = <700000>;
239 regulator-max-microvolt = <1475000>;
242 regulator-ramp-delay = <6250>;
246 regulator-min-microvolt = <1500000>;
247 regulator-max-microvolt = <1850000>;
253 regulator-min-microvolt = <900000>;
254 regulator-max-microvolt = <1650000>;
260 regulator-min-microvolt = <5000000>;
261 regulator-max-microvolt = <5150000>;
265 regulator-min-microvolt = <1000000>;
266 regulator-max-microvolt = <3000000>;
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <3300000>;
283 regulator-min-microvolt = <800000>;
284 regulator-max-microvolt = <1550000>;
288 regulator-min-microvolt = <2850000>;
289 regulator-max-microvolt = <3300000>;
294 regulator-min-microvolt = <2850000>;
295 regulator-max-microvolt = <3300000>;
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <3300000>;
306 regulator-min-microvolt = <2800000>;
307 regulator-max-microvolt = <2800000>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_i2c2>;
320 compatible = "fsl,mpl3115";
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_i2c3>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_i2c4>;
337 compatible = "wlf,wm8960";
339 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
340 clock-names = "mclk";
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_lcdif>;
351 display_out: endpoint {
352 remote-endpoint = <&panel_in>;
358 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_uart1>;
365 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
366 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_uart6>;
373 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
374 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
380 vbus-supply = <®_usb_otg1_vbus>;
385 vbus-supply = <®_usb_otg2_vbus>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_usdhc1>;
393 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
394 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
396 keep-power-in-suspend;
401 pinctrl-names = "default", "state_100mhz", "state_200mhz";
402 pinctrl-0 = <&pinctrl_usdhc2>;
403 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
404 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
406 keep-power-in-suspend;
408 vmmc-supply = <®_brcm>;
409 fsl,tuning-step = <2>;
414 pinctrl-names = "default", "state_100mhz", "state_200mhz";
415 pinctrl-0 = <&pinctrl_usdhc3>;
416 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
417 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
418 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
419 assigned-clock-rates = <400000000>;
421 fsl,tuning-step = <2>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_wdog>;
429 fsl,ext-reset-output;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_hog>;
437 pinctrl_brcm_reg: brcmreggrp {
439 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
443 pinctrl_ecspi3: ecspi3grp {
445 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
446 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
447 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
448 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
452 pinctrl_enet1: enet1grp {
454 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
455 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
456 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
457 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
458 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
459 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
460 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
461 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
462 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
463 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
464 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
465 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
466 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
467 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
471 pinctrl_enet2: enet2grp {
473 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
474 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
475 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
476 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
477 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
478 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
479 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
480 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
481 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
482 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
483 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
484 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
488 pinctrl_flexcan2: flexcan2grp {
490 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
491 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
495 pinctrl_flexcan2_reg: flexcan2reggrp {
497 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
501 pinctrl_gpio_keys: gpio_keysgrp {
503 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
504 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
508 pinctrl_hog: hoggrp {
510 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
511 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
515 pinctrl_i2c1: i2c1grp {
517 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
518 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
522 pinctrl_i2c2: i2c2grp {
524 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
525 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
529 pinctrl_i2c3: i2c3grp {
531 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
532 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
536 pinctrl_i2c4: i2c4grp {
538 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
539 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
543 pinctrl_lcdif: lcdifgrp {
545 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
546 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
547 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
548 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
549 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
550 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
551 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
552 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
553 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
554 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
555 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
556 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
557 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
558 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
559 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
560 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
561 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
562 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
563 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
564 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
565 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
566 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
567 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
568 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
569 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
570 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
571 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
572 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
573 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
577 pinctrl_spi4: spi4grp {
579 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
580 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
581 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
585 pinctrl_tsc2046_pendown: tsc2046_pendown {
587 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
591 pinctrl_uart1: uart1grp {
593 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
594 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
598 pinctrl_uart5: uart5grp {
600 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
601 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
602 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
603 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
607 pinctrl_uart6: uart6grp {
609 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
610 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
611 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
612 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
616 pinctrl_usdhc1: usdhc1grp {
618 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
619 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
620 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
621 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
622 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
623 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
624 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
625 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
626 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
630 pinctrl_usdhc2: usdhc2grp {
632 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
633 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
634 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
635 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
636 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
637 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
641 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
643 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
644 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
645 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
646 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
647 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
648 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
652 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
654 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
655 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
656 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
657 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
658 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
659 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
664 pinctrl_usdhc3: usdhc3grp {
666 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
667 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
668 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
669 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
670 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
671 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
672 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
673 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
674 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
675 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
676 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
680 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
682 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
683 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
684 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
685 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
686 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
687 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
688 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
689 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
690 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
691 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
692 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
696 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
698 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
699 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
700 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
701 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
702 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
703 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
704 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
705 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
706 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
707 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
708 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
715 pinctrl-names = "default";
716 pinctrl-0 = <&pinctrl_pwm1>;
721 pinctrl_wdog: wdoggrp {
723 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
727 pinctrl_pwm1: pwm1grp {
729 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30