arch/arm/boot/dts/imx7d-sdb.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include "imx7d.dtsi"
  46
  47 / {
  48         model = "Freescale i.MX7 SabreSD Board";
  49         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  50
  51         memory {
  52                 reg = <0x80000000 0x80000000>;
  53         };
  54
  55         regulators {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 reg_usb_otg1_vbus: regulator@0 {
  61                         compatible = "regulator-fixed";
  62                         reg = <0>;
  63                         regulator-name = "usb_otg1_vbus";
  64                         regulator-min-microvolt = <5000000>;
  65                         regulator-max-microvolt = <5000000>;
  66                         gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  67                         enable-active-high;
  68                 };
  69
  70                 reg_usb_otg2_vbus: regulator@1 {
  71                         compatible = "regulator-fixed";
  72                         reg = <1>;
  73                         regulator-name = "usb_otg2_vbus";
  74                         regulator-min-microvolt = <5000000>;
  75                         regulator-max-microvolt = <5000000>;
  76                         gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  77                         enable-active-high;
  78                 };
  79
  80                 reg_can2_3v3: regulator@2 {
  81                         compatible = "regulator-fixed";
  82                         reg = <2>;
  83                         regulator-name = "can2-3v3";
  84                         regulator-min-microvolt = <3300000>;
  85                         regulator-max-microvolt = <3300000>;
  86                         gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
  87                 };
  88
  89                 reg_vref_1v8: regulator@3 {
  90                         compatible = "regulator-fixed";
  91                         reg = <3>;
  92                         regulator-name = "vref-1v8";
  93                         regulator-min-microvolt = <1800000>;
  94                         regulator-max-microvolt = <1800000>;
  95                 };
  96         };
  97 };
  98
  99 &adc1 {
 100         vref-supply = <&reg_vref_1v8>;
 101         status = "okay";
 102 };
 103
 104 &adc2 {
 105         vref-supply = <&reg_vref_1v8>;
 106         status = "okay";
 107 };
 108
 109 &cpu0 {
 110         arm-supply = <&sw1a_reg>;
 111 };
 112
 113 &ecspi3 {
 114         fsl,spi-num-chipselects = <1>;
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_ecspi3>;
 117         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 118         status = "okay";
 119
 120         tsc2046@0 {
 121                 compatible = "ti,tsc2046";
 122                 reg = <0>;
 123                 spi-max-frequency = <1000000>;
 124                 pinctrl-names ="default";
 125                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 126                 interrupt-parent = <&gpio2>;
 127                 interrupts = <29 0>;
 128                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 129                 touchscreen-max-pressure = <255>;
 130                 wakeup-source;
 131         };
 132 };
 133
 134 &fec1 {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_enet1>;
 137         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 138                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 139         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 140         assigned-clock-rates = <0>, <100000000>;
 141         phy-mode = "rgmii";
 142         phy-handle = <&ethphy0>;
 143         fsl,magic-packet;
 144         status = "okay";
 145
 146         mdio {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149
 150                 ethphy0: ethernet-phy@0 {
 151                         reg = <0>;
 152                 };
 153
 154                 ethphy1: ethernet-phy@1 {
 155                         reg = <1>;
 156                 };
 157         };
 158 };
 159
 160 &fec2 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_enet2>;
 163         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 164                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 165         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 166         assigned-clock-rates = <0>, <100000000>;
 167         phy-mode = "rgmii";
 168         phy-handle = <&ethphy1>;
 169         fsl,magic-packet;
 170         status = "okay";
 171 };
 172
 173 &i2c1 {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_i2c1>;
 176         status = "okay";
 177
 178         pmic: pfuze3000@08 {
 179                 compatible = "fsl,pfuze3000";
 180                 reg = <0x08>;
 181
 182                 regulators {
 183                         sw1a_reg: sw1a {
 184                                 regulator-min-microvolt = <700000>;
 185                                 regulator-max-microvolt = <1475000>;
 186                                 regulator-boot-on;
 187                                 regulator-always-on;
 188                                 regulator-ramp-delay = <6250>;
 189                         };
 190
 191                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 192                         sw1c_reg: sw1b {
 193                                 regulator-min-microvolt = <700000>;
 194                                 regulator-max-microvolt = <1475000>;
 195                                 regulator-boot-on;
 196                                 regulator-always-on;
 197                                 regulator-ramp-delay = <6250>;
 198                         };
 199
 200                         sw2_reg: sw2 {
 201                                 regulator-min-microvolt = <1500000>;
 202                                 regulator-max-microvolt = <1850000>;
 203                                 regulator-boot-on;
 204                                 regulator-always-on;
 205                         };
 206
 207                         sw3a_reg: sw3 {
 208                                 regulator-min-microvolt = <900000>;
 209                                 regulator-max-microvolt = <1650000>;
 210                                 regulator-boot-on;
 211                                 regulator-always-on;
 212                         };
 213
 214                         swbst_reg: swbst {
 215                                 regulator-min-microvolt = <5000000>;
 216                                 regulator-max-microvolt = <5150000>;
 217                         };
 218
 219                         snvs_reg: vsnvs {
 220                                 regulator-min-microvolt = <1000000>;
 221                                 regulator-max-microvolt = <3000000>;
 222                                 regulator-boot-on;
 223                                 regulator-always-on;
 224                         };
 225
 226                         vref_reg: vrefddr {
 227                                 regulator-boot-on;
 228                                 regulator-always-on;
 229                         };
 230
 231                         vgen1_reg: vldo1 {
 232                                 regulator-min-microvolt = <1800000>;
 233                                 regulator-max-microvolt = <3300000>;
 234                                 regulator-always-on;
 235                         };
 236
 237                         vgen2_reg: vldo2 {
 238                                 regulator-min-microvolt = <800000>;
 239                                 regulator-max-microvolt = <1550000>;
 240                         };
 241
 242                         vgen3_reg: vccsd {
 243                                 regulator-min-microvolt = <2850000>;
 244                                 regulator-max-microvolt = <3300000>;
 245                                 regulator-always-on;
 246                         };
 247
 248                         vgen4_reg: v33 {
 249                                 regulator-min-microvolt = <2850000>;
 250                                 regulator-max-microvolt = <3300000>;
 251                                 regulator-always-on;
 252                         };
 253
 254                         vgen5_reg: vldo3 {
 255                                 regulator-min-microvolt = <1800000>;
 256                                 regulator-max-microvolt = <3300000>;
 257                                 regulator-always-on;
 258                         };
 259
 260                         vgen6_reg: vldo4 {
 261                                 regulator-min-microvolt = <1800000>;
 262                                 regulator-max-microvolt = <3300000>;
 263                                 regulator-always-on;
 264                         };
 265                 };
 266         };
 267 };
 268
 269 &i2c2 {
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&pinctrl_i2c2>;
 272         status = "okay";
 273 };
 274
 275 &i2c3 {
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&pinctrl_i2c3>;
 278         status = "okay";
 279 };
 280
 281 &i2c4 {
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_i2c4>;
 284         status = "okay";
 285
 286         codec: wm8960@1a {
 287                 compatible = "wlf,wm8960";
 288                 reg = <0x1a>;
 289                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 290                 clock-names = "mclk";
 291                 wlf,shared-lrclk;
 292         };
 293 };
 294
 295 &lcdif {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_lcdif>;
 298         display = <&display0>;
 299         status = "okay";
 300
 301         display0: display {
 302                 bits-per-pixel = <16>;
 303                 bus-width = <24>;
 304
 305                 display-timings {
 306                         native-mode = <&timing0>;
 307
 308                         timing0: timing0 {
 309                                 clock-frequency = <9200000>;
 310                                 hactive = <480>;
 311                                 vactive = <272>;
 312                                 hfront-porch = <8>;
 313                                 hback-porch = <4>;
 314                                 hsync-len = <41>;
 315                                 vback-porch = <2>;
 316                                 vfront-porch = <4>;
 317                                 vsync-len = <10>;
 318                                 hsync-active = <0>;
 319                                 vsync-active = <0>;
 320                                 de-active = <1>;
 321                                 pixelclk-active = <0>;
 322                         };
 323                 };
 324         };
 325 };
 326
 327 &pwm1 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_pwm1>;
 330         status = "okay";
 331 };
 332
 333 &uart1 {
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&pinctrl_uart1>;
 336         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 337         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 338         status = "okay";
 339 };
 340
 341 &usbotg1 {
 342         vbus-supply = <&reg_usb_otg1_vbus>;
 343         status = "okay";
 344 };
 345
 346 &usbotg2 {
 347         vbus-supply = <&reg_usb_otg2_vbus>;
 348         dr_mode = "host";
 349         status = "okay";
 350 };
 351
 352 &usdhc1 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_usdhc1>;
 355         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 356         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 357         wakeup-source;
 358         keep-power-in-suspend;
 359         status = "okay";
 360 };
 361
 362 &usdhc3 {
 363         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 364         pinctrl-0 = <&pinctrl_usdhc3>;
 365         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 366         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 367         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 368         assigned-clock-rates = <400000000>;
 369         bus-width = <8>;
 370         fsl,tuning-step = <2>;
 371         non-removable;
 372         status = "okay";
 373 };
 374
 375 &wdog1 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_wdog>;
 378         fsl,ext-reset-output;
 379 };
 380
 381 &iomuxc {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_hog>;
 384
 385         imx7d-sdb {
 386                 pinctrl_ecspi3: ecspi3grp {
 387                         fsl,pins = <
 388                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 389                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 390                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 391                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 392                         >;
 393                 };
 394
 395                 pinctrl_enet1: enet1grp {
 396                         fsl,pins = <
 397                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 398                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 399                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 400                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 401                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 402                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 403                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 404                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 405                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 406                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 407                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 408                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 409                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 410                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 411                         >;
 412                 };
 413
 414                 pinctrl_enet2: enet2grp {
 415                         fsl,pins = <
 416                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 417                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 418                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 419                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 420                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 421                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 422                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 423                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 424                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 425                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 426                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 427                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 428                         >;
 429                 };
 430
 431                 pinctrl_hog: hoggrp {
 432                         fsl,pins = <
 433                                 MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 434                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 435                         >;
 436                 };
 437
 438                 pinctrl_i2c1: i2c1grp {
 439                         fsl,pins = <
 440                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 441                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 442                         >;
 443                 };
 444
 445                 pinctrl_i2c2: i2c2grp {
 446                         fsl,pins = <
 447                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 448                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 449                         >;
 450                 };
 451
 452                 pinctrl_i2c3: i2c3grp {
 453                         fsl,pins = <
 454                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 455                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 456                         >;
 457                 };
 458
 459                 pinctrl_i2c4: i2c4grp {
 460                         fsl,pins = <
 461                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 462                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 463                         >;
 464                 };
 465
 466                 pinctrl_lcdif: lcdifgrp {
 467                         fsl,pins = <
 468                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 469                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 470                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 471                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 472                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 473                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 474                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 475                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 476                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 477                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 478                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 479                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 480                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 481                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 482                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 483                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 484                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 485                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 486                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 487                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 488                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 489                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 490                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 491                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 492                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 493                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 494                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 495                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 496                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 497                         >;
 498                 };
 499
 500                 pinctrl_pwm1: pwm1grp {
 501                         fsl,pins = <
 502                                 MX7D_PAD_GPIO1_IO01__PWM1_OUT           0x110b0
 503                         >;
 504                 };
 505
 506                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 507                         fsl,pins = <
 508                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 509                         >;
 510                 };
 511
 512                 pinctrl_uart1: uart1grp {
 513                         fsl,pins = <
 514                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 515                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 516                         >;
 517                 };
 518
 519                 pinctrl_uart5: uart5grp {
 520                         fsl,pins = <
 521                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 522                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 523                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 524                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 525                         >;
 526                 };
 527
 528                 pinctrl_uart6: uart6grp {
 529                         fsl,pins = <
 530                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 531                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 532                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 533                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 534                         >;
 535                 };
 536
 537                 pinctrl_usdhc1: usdhc1grp {
 538                         fsl,pins = <
 539                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 540                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 541                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 542                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 543                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 544                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 545                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 546                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 547                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 548                         >;
 549                 };
 550
 551                 pinctrl_usdhc2: usdhc2grp {
 552                         fsl,pins = <
 553                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 554                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 555                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 556                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 557                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 558                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 559                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x59 /* WL_REG_ON */
 560                         >;
 561                 };
 562
 563                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 564                         fsl,pins = <
 565                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 566                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 567                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 568                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 569                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 570                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 571                         >;
 572                 };
 573
 574                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 575                         fsl,pins = <
 576                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 577                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 578                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 579                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 580                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 581                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 582                         >;
 583                 };
 584
 585
 586                 pinctrl_usdhc3: usdhc3grp {
 587                         fsl,pins = <
 588                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 589                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 590                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 591                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 592                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 593                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 594                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 595                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 596                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 597                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 598                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 599                         >;
 600                 };
 601
 602                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 603                         fsl,pins = <
 604                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 605                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 606                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 607                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 608                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 609                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 610                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 611                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 612                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 613                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 614                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 615                         >;
 616                 };
 617
 618                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 619                         fsl,pins = <
 620                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 621                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 622                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 623                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 624                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 625                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 626                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 627                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 628                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 629                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 630                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 631                         >;
 632                 };
 633
 634                 pinctrl_wdog: wdoggrp {
 635                         fsl,pins = <
 636                                 MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B       0x74
 637                         >;
 638                 };
 639         };
 640 };