arch/arm/boot/dts/imx7d-sdb.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include "imx7d.dtsi"
  46
  47 / {
  48         model = "Freescale i.MX7 SabreSD Board";
  49         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  50
  51         memory {
  52                 reg = <0x80000000 0x80000000>;
  53         };
  54
  55         spi4 {
  56                 compatible = "spi-gpio";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_spi4>;
  59                 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  60                 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  61                 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  62                 num-chipselects = <1>;
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 extended_io: gpio-expander@0 {
  67                         compatible = "fairchild,74hc595";
  68                         gpio-controller;
  69                         #gpio-cells = <2>;
  70                         reg = <0>;
  71                         registers-number = <1>;
  72                         spi-max-frequency = <100000>;
  73                 };
  74         };
  75
  76         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "usb_otg1_vbus";
  79                 regulator-min-microvolt = <5000000>;
  80                 regulator-max-microvolt = <5000000>;
  81                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  82                 enable-active-high;
  83         };
  84
  85         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "usb_otg2_vbus";
  88                 regulator-min-microvolt = <5000000>;
  89                 regulator-max-microvolt = <5000000>;
  90                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  91                 enable-active-high;
  92         };
  93
  94         reg_can2_3v3: regulator-can2-3v3 {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "can2-3v3";
  97                 regulator-min-microvolt = <3300000>;
  98                 regulator-max-microvolt = <3300000>;
  99                 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
 100         };
 101
 102         reg_vref_1v8: regulator-vref-1v8 {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "vref-1v8";
 105                 regulator-min-microvolt = <1800000>;
 106                 regulator-max-microvolt = <1800000>;
 107         };
 108
 109         reg_brcm: regulator-brcm {
 110                 compatible = "regulator-fixed";
 111                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 112                 enable-active-high;
 113                 regulator-name = "brcm_reg";
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_brcm_reg>;
 116                 regulator-min-microvolt = <3300000>;
 117                 regulator-max-microvolt = <3300000>;
 118                 startup-delay-us = <200000>;
 119         };
 120
 121         reg_lcd_3v3: regulator-lcd-3v3 {
 122                 compatible = "regulator-fixed";
 123                 regulator-name = "lcd-3v3";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
 127         };
 128
 129         reg_can2_3v3: regulator-can2-3v3 {
 130                 compatible = "regulator-fixed";
 131                 regulator-name = "can2-3v3";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
 134                 regulator-min-microvolt = <3300000>;
 135                 regulator-max-microvolt = <3300000>;
 136                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 137         };
 138
 139         panel {
 140                 compatible = "innolux,at043tn24";
 141                 pinctrl-0 = <&pinctrl_backlight>;
 142                 enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 143                 power-supply = <&reg_lcd_3v3>;
 144
 145                 port {
 146                         panel_in: endpoint {
 147                                 remote-endpoint = <&display_out>;
 148                         };
 149                 };
 150         };
 151 };
 152
 153 &adc1 {
 154         vref-supply = <&reg_vref_1v8>;
 155         status = "okay";
 156 };
 157
 158 &adc2 {
 159         vref-supply = <&reg_vref_1v8>;
 160         status = "okay";
 161 };
 162
 163 &cpu0 {
 164         arm-supply = <&sw1a_reg>;
 165 };
 166
 167 &ecspi3 {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_ecspi3>;
 170         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 171         status = "okay";
 172
 173         tsc2046@0 {
 174                 compatible = "ti,tsc2046";
 175                 reg = <0>;
 176                 spi-max-frequency = <1000000>;
 177                 pinctrl-names ="default";
 178                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 179                 interrupt-parent = <&gpio2>;
 180                 interrupts = <29 0>;
 181                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 182                 touchscreen-max-pressure = <255>;
 183                 wakeup-source;
 184         };
 185 };
 186
 187 &fec1 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_enet1>;
 190         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 191                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 192         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 193         assigned-clock-rates = <0>, <100000000>;
 194         phy-mode = "rgmii";
 195         phy-handle = <&ethphy0>;
 196         fsl,magic-packet;
 197         phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
 198         status = "okay";
 199
 200         mdio {
 201                 #address-cells = <1>;
 202                 #size-cells = <0>;
 203
 204                 ethphy0: ethernet-phy@0 {
 205                         reg = <0>;
 206                 };
 207
 208                 ethphy1: ethernet-phy@1 {
 209                         reg = <1>;
 210                 };
 211         };
 212 };
 213
 214 &fec2 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_enet2>;
 217         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 218                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 219         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 220         assigned-clock-rates = <0>, <100000000>;
 221         phy-mode = "rgmii";
 222         phy-handle = <&ethphy1>;
 223         fsl,magic-packet;
 224         status = "okay";
 225 };
 226
 227 &flexcan2 {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_flexcan2>;
 230         xceiver-supply = <&reg_can2_3v3>;
 231         status = "okay";
 232 };
 233
 234 &i2c1 {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_i2c1>;
 237         status = "okay";
 238
 239         pmic: pfuze3000@08 {
 240                 compatible = "fsl,pfuze3000";
 241                 reg = <0x08>;
 242
 243                 regulators {
 244                         sw1a_reg: sw1a {
 245                                 regulator-min-microvolt = <700000>;
 246                                 regulator-max-microvolt = <1475000>;
 247                                 regulator-boot-on;
 248                                 regulator-always-on;
 249                                 regulator-ramp-delay = <6250>;
 250                         };
 251
 252                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 253                         sw1c_reg: sw1b {
 254                                 regulator-min-microvolt = <700000>;
 255                                 regulator-max-microvolt = <1475000>;
 256                                 regulator-boot-on;
 257                                 regulator-always-on;
 258                                 regulator-ramp-delay = <6250>;
 259                         };
 260
 261                         sw2_reg: sw2 {
 262                                 regulator-min-microvolt = <1500000>;
 263                                 regulator-max-microvolt = <1850000>;
 264                                 regulator-boot-on;
 265                                 regulator-always-on;
 266                         };
 267
 268                         sw3a_reg: sw3 {
 269                                 regulator-min-microvolt = <900000>;
 270                                 regulator-max-microvolt = <1650000>;
 271                                 regulator-boot-on;
 272                                 regulator-always-on;
 273                         };
 274
 275                         swbst_reg: swbst {
 276                                 regulator-min-microvolt = <5000000>;
 277                                 regulator-max-microvolt = <5150000>;
 278                         };
 279
 280                         snvs_reg: vsnvs {
 281                                 regulator-min-microvolt = <1000000>;
 282                                 regulator-max-microvolt = <3000000>;
 283                                 regulator-boot-on;
 284                                 regulator-always-on;
 285                         };
 286
 287                         vref_reg: vrefddr {
 288                                 regulator-boot-on;
 289                                 regulator-always-on;
 290                         };
 291
 292                         vgen1_reg: vldo1 {
 293                                 regulator-min-microvolt = <1800000>;
 294                                 regulator-max-microvolt = <3300000>;
 295                                 regulator-always-on;
 296                         };
 297
 298                         vgen2_reg: vldo2 {
 299                                 regulator-min-microvolt = <800000>;
 300                                 regulator-max-microvolt = <1550000>;
 301                         };
 302
 303                         vgen3_reg: vccsd {
 304                                 regulator-min-microvolt = <2850000>;
 305                                 regulator-max-microvolt = <3300000>;
 306                                 regulator-always-on;
 307                         };
 308
 309                         vgen4_reg: v33 {
 310                                 regulator-min-microvolt = <2850000>;
 311                                 regulator-max-microvolt = <3300000>;
 312                                 regulator-always-on;
 313                         };
 314
 315                         vgen5_reg: vldo3 {
 316                                 regulator-min-microvolt = <1800000>;
 317                                 regulator-max-microvolt = <3300000>;
 318                                 regulator-always-on;
 319                         };
 320
 321                         vgen6_reg: vldo4 {
 322                                 regulator-min-microvolt = <2800000>;
 323                                 regulator-max-microvolt = <2800000>;
 324                                 regulator-always-on;
 325                         };
 326                 };
 327         };
 328 };
 329
 330 &i2c2 {
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_i2c2>;
 333         status = "okay";
 334 };
 335
 336 &i2c3 {
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_i2c3>;
 339         status = "okay";
 340 };
 341
 342 &i2c4 {
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_i2c4>;
 345         status = "okay";
 346
 347         codec: wm8960@1a {
 348                 compatible = "wlf,wm8960";
 349                 reg = <0x1a>;
 350                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 351                 clock-names = "mclk";
 352                 wlf,shared-lrclk;
 353         };
 354 };
 355
 356 &lcdif {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_lcdif>;
 359         status = "okay";
 360
 361         port {
 362                 display_out: endpoint {
 363                         remote-endpoint = <&panel_in>;
 364                 };
 365         };
 366 };
 367
 368 &pcie {
 369         reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 370         status = "okay";
 371 };
 372
 373 &uart1 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_uart1>;
 376         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 377         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 378         status = "okay";
 379 };
 380
 381 &uart6 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_uart6>;
 384         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 385         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 386         uart-has-rtscts;
 387         status = "okay";
 388 };
 389
 390 &usbotg1 {
 391         vbus-supply = <&reg_usb_otg1_vbus>;
 392         status = "okay";
 393 };
 394
 395 &usbotg2 {
 396         vbus-supply = <&reg_usb_otg2_vbus>;
 397         dr_mode = "host";
 398         status = "okay";
 399 };
 400
 401 &usdhc1 {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_usdhc1>;
 404         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 405         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 406         wakeup-source;
 407         keep-power-in-suspend;
 408         status = "okay";
 409 };
 410
 411 &usdhc2 {
 412         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 413         pinctrl-0 = <&pinctrl_usdhc2>;
 414         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 415         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 416         wakeup-source;
 417         keep-power-in-suspend;
 418         non-removable;
 419         vmmc-supply = <&reg_brcm>;
 420         fsl,tuning-step = <2>;
 421         status = "okay";
 422 };
 423
 424 &usdhc3 {
 425         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 426         pinctrl-0 = <&pinctrl_usdhc3>;
 427         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 428         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 429         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 430         assigned-clock-rates = <400000000>;
 431         bus-width = <8>;
 432         fsl,tuning-step = <2>;
 433         non-removable;
 434         status = "okay";
 435 };
 436
 437 &wdog1 {
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&pinctrl_wdog>;
 440         fsl,ext-reset-output;
 441 };
 442
 443 &iomuxc {
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&pinctrl_hog>;
 446
 447         imx7d-sdb {
 448                 pinctrl_brcm_reg: brcmreggrp {
 449                         fsl,pins = <
 450                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
 451                         >;
 452                 };
 453
 454                 pinctrl_ecspi3: ecspi3grp {
 455                         fsl,pins = <
 456                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 457                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 458                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 459                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 460                         >;
 461                 };
 462
 463                 pinctrl_enet1: enet1grp {
 464                         fsl,pins = <
 465                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 466                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 467                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 468                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 469                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 470                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 471                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 472                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 473                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 474                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 475                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 476                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 477                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 478                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 479                         >;
 480                 };
 481
 482                 pinctrl_enet2: enet2grp {
 483                         fsl,pins = <
 484                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 485                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 486                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 487                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 488                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 489                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 490                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 491                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 492                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 493                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 494                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 495                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 496                         >;
 497                 };
 498
 499                 pinctrl_flexcan2: flexcan2grp {
 500                         fsl,pins = <
 501                                 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 502                                 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 503                         >;
 504                 };
 505
 506                 pinctrl_flexcan2_reg: flexcan2reggrp {
 507                         fsl,pins = <
 508                                 MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
 509                         >;
 510                 };
 511
 512
 513                 pinctrl_hog: hoggrp {
 514                         fsl,pins = <
 515                                 MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 516                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 517                         >;
 518                 };
 519
 520                 pinctrl_i2c1: i2c1grp {
 521                         fsl,pins = <
 522                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 523                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 524                         >;
 525                 };
 526
 527                 pinctrl_i2c2: i2c2grp {
 528                         fsl,pins = <
 529                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 530                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 531                         >;
 532                 };
 533
 534                 pinctrl_i2c3: i2c3grp {
 535                         fsl,pins = <
 536                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 537                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 538                         >;
 539                 };
 540
 541                 pinctrl_i2c4: i2c4grp {
 542                         fsl,pins = <
 543                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 544                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 545                         >;
 546                 };
 547
 548                 pinctrl_lcdif: lcdifgrp {
 549                         fsl,pins = <
 550                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 551                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 552                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 553                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 554                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 555                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 556                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 557                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 558                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 559                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 560                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 561                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 562                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 563                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 564                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 565                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 566                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 567                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 568                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 569                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 570                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 571                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 572                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 573                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 574                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 575                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 576                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 577                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 578                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 579                         >;
 580                 };
 581
 582                 pinctrl_spi4: spi4grp {
 583                         fsl,pins = <
 584                                 MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 585                                 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 586                                 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 587                         >;
 588                 };
 589
 590                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 591                         fsl,pins = <
 592                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 593                         >;
 594                 };
 595
 596                 pinctrl_uart1: uart1grp {
 597                         fsl,pins = <
 598                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 599                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 600                         >;
 601                 };
 602
 603                 pinctrl_uart5: uart5grp {
 604                         fsl,pins = <
 605                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 606                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 607                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 608                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 609                         >;
 610                 };
 611
 612                 pinctrl_uart6: uart6grp {
 613                         fsl,pins = <
 614                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 615                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 616                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 617                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 618                         >;
 619                 };
 620
 621                 pinctrl_usdhc1: usdhc1grp {
 622                         fsl,pins = <
 623                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 624                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 625                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 626                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 627                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 628                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 629                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 630                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 631                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 632                         >;
 633                 };
 634
 635                 pinctrl_usdhc2: usdhc2grp {
 636                         fsl,pins = <
 637                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 638                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 639                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 640                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 641                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 642                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 643                         >;
 644                 };
 645
 646                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 647                         fsl,pins = <
 648                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 649                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 650                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 651                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 652                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 653                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 654                         >;
 655                 };
 656
 657                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 658                         fsl,pins = <
 659                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 660                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 661                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 662                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 663                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 664                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 665                         >;
 666                 };
 667
 668
 669                 pinctrl_usdhc3: usdhc3grp {
 670                         fsl,pins = <
 671                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 672                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 673                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 674                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 675                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 676                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 677                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 678                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 679                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 680                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 681                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 682                         >;
 683                 };
 684
 685                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 686                         fsl,pins = <
 687                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 688                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 689                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 690                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 691                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 692                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 693                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 694                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 695                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 696                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 697                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 698                         >;
 699                 };
 700
 701                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 702                         fsl,pins = <
 703                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 704                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 705                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 706                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 707                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 708                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 709                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 710                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 711                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 712                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 713                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 714                         >;
 715                 };
 716         };
 717 };
 718
 719 &iomuxc_lpsr {
 720         pinctrl_wdog: wdoggrp {
 721                 fsl,pins = <
 722                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
 723                 >;
 724         };
 725
 726         pinctrl_backlight: backlightgrp {
 727                 fsl,pins = <
 728                         MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1             0x110b0
 729                 >;
 730         };
 731 };