arch/arm/boot/dts/imx7d-nitrogen7.dts

   1 /*
   2  * Copyright 2016 Boundary Devices, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include "imx7d.dtsi"
  46
  47 / {
  48         model = "Boundary Devices i.MX7 Nitrogen7 Board";
  49         compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
  50
  51         aliases {
  52                 fb_lcd = &lcdif;
  53                 t_lcd = &t_lcd;
  54         };
  55
  56         memory {
  57                 reg = <0x80000000 0x40000000>;
  58         };
  59
  60         backlight-j9 {
  61                 compatible = "gpio-backlight";
  62                 pinctrl-names = "default";
  63                 pinctrl-0 = <&pinctrl_backlight_j9>;
  64                 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  65                 default-on;
  66         };
  67
  68         backlight-j20 {
  69                 compatible = "pwm-backlight";
  70                 pwms = <&pwm1 0 5000000 0>;
  71                 brightness-levels = <0 4 8 16 32 64 128 255>;
  72                 default-brightness-level = <6>;
  73                 status = "okay";
  74         };
  75
  76         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "usb_otg1_vbus";
  79                 regulator-min-microvolt = <5000000>;
  80                 regulator-max-microvolt = <5000000>;
  81                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  82                 enable-active-high;
  83         };
  84
  85         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "usb_otg2_vbus";
  88                 regulator-min-microvolt = <5000000>;
  89                 regulator-max-microvolt = <5000000>;
  90                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  91                 enable-active-high;
  92         };
  93
  94         reg_can2_3v3: regulator-can2-3v3 {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "can2-3v3";
  97                 regulator-min-microvolt = <3300000>;
  98                 regulator-max-microvolt = <3300000>;
  99                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 100         };
 101
 102         reg_vref_1v8: regulator-vref-1v8 {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "vref-1v8";
 105                 regulator-min-microvolt = <1800000>;
 106                 regulator-max-microvolt = <1800000>;
 107         };
 108
 109         reg_vref_3v3: regulator-vref-3v3 {
 110                 compatible = "regulator-fixed";
 111                 regulator-name = "vref-3v3";
 112                 regulator-min-microvolt = <3300000>;
 113                 regulator-max-microvolt = <3300000>;
 114         };
 115
 116         reg_wlan: regulator-wlan {
 117                 compatible = "regulator-fixed";
 118                 regulator-min-microvolt = <3300000>;
 119                 regulator-max-microvolt = <3300000>;
 120                 regulator-name = "reg_wlan";
 121                 startup-delay-us = <70000>;
 122                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 123                 enable-active-high;
 124         };
 125
 126         usdhc2_pwrseq: usdhc2_pwrseq {
 127                 compatible = "mmc-pwrseq-simple";
 128                 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
 129                 clock-names = "ext_clock";
 130         };
 131 };
 132
 133 &adc1 {
 134         vref-supply = <&reg_vref_1v8>;
 135         status = "okay";
 136 };
 137
 138 &adc2 {
 139         vref-supply = <&reg_vref_1v8>;
 140         status = "okay";
 141 };
 142
 143 &clks {
 144         assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
 145                           <&clks IMX7D_CLKO2_ROOT_DIV>;
 146         assigned-clock-parents = <&clks IMX7D_CKIL>;
 147         assigned-clock-rates = <0>, <32768>;
 148 };
 149
 150 &cpu0 {
 151         arm-supply = <&sw1a_reg>;
 152 };
 153
 154 &fec1 {
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_enet1>;
 157         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 158                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 159         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 160         assigned-clock-rates = <0>, <100000000>;
 161         phy-mode = "rgmii";
 162         phy-handle = <&ethphy0>;
 163         fsl,magic-packet;
 164         status = "okay";
 165
 166         mdio {
 167                 #address-cells = <1>;
 168                 #size-cells = <0>;
 169
 170                 ethphy0: ethernet-phy@4 {
 171                         reg = <4>;
 172                 };
 173         };
 174 };
 175
 176 &flexcan2 {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_flexcan2>;
 179         xceiver-supply = <&reg_can2_3v3>;
 180         status = "okay";
 181 };
 182
 183 &i2c1 {
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&pinctrl_i2c1>;
 186         status = "okay";
 187
 188         pmic: pfuze3000@08 {
 189                 compatible = "fsl,pfuze3000";
 190                 reg = <0x08>;
 191
 192                 regulators {
 193                         sw1a_reg: sw1a {
 194                                 regulator-min-microvolt = <700000>;
 195                                 regulator-max-microvolt = <1475000>;
 196                                 regulator-boot-on;
 197                                 regulator-always-on;
 198                                 regulator-ramp-delay = <6250>;
 199                         };
 200
 201                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 202                         sw1c_reg: sw1b {
 203                                 regulator-min-microvolt = <700000>;
 204                                 regulator-max-microvolt = <1475000>;
 205                                 regulator-boot-on;
 206                                 regulator-always-on;
 207                                 regulator-ramp-delay = <6250>;
 208                         };
 209
 210                         sw2_reg: sw2 {
 211                                 regulator-min-microvolt = <1500000>;
 212                                 regulator-max-microvolt = <1850000>;
 213                                 regulator-boot-on;
 214                                 regulator-always-on;
 215                         };
 216
 217                         sw3a_reg: sw3 {
 218                                 regulator-min-microvolt = <900000>;
 219                                 regulator-max-microvolt = <1650000>;
 220                                 regulator-boot-on;
 221                                 regulator-always-on;
 222                         };
 223
 224                         swbst_reg: swbst {
 225                                 regulator-min-microvolt = <5000000>;
 226                                 regulator-max-microvolt = <5150000>;
 227                         };
 228
 229                         snvs_reg: vsnvs {
 230                                 regulator-min-microvolt = <1000000>;
 231                                 regulator-max-microvolt = <3000000>;
 232                                 regulator-boot-on;
 233                                 regulator-always-on;
 234                         };
 235
 236                         vref_reg: vrefddr {
 237                                 regulator-boot-on;
 238                                 regulator-always-on;
 239                         };
 240
 241                         vgen1_reg: vldo1 {
 242                                 regulator-min-microvolt = <1800000>;
 243                                 regulator-max-microvolt = <3300000>;
 244                                 regulator-always-on;
 245                         };
 246
 247                         vgen2_reg: vldo2 {
 248                                 regulator-min-microvolt = <800000>;
 249                                 regulator-max-microvolt = <1550000>;
 250                                 regulator-always-on;
 251                         };
 252
 253                         vgen3_reg: vccsd {
 254                                 regulator-min-microvolt = <2850000>;
 255                                 regulator-max-microvolt = <3300000>;
 256                                 regulator-always-on;
 257                         };
 258
 259                         vgen4_reg: v33 {
 260                                 regulator-min-microvolt = <2850000>;
 261                                 regulator-max-microvolt = <3300000>;
 262                                 regulator-always-on;
 263                         };
 264
 265                         vgen5_reg: vldo3 {
 266                                 regulator-min-microvolt = <1800000>;
 267                                 regulator-max-microvolt = <3300000>;
 268                                 regulator-always-on;
 269                         };
 270
 271                         vgen6_reg: vldo4 {
 272                                 regulator-min-microvolt = <1800000>;
 273                                 regulator-max-microvolt = <3300000>;
 274                                 regulator-always-on;
 275                         };
 276                 };
 277         };
 278 };
 279
 280 &i2c2 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_i2c2>;
 283         status = "okay";
 284
 285         rtc@68 {
 286                 compatible = "microcrystal,rv4162";
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&pinctrl_i2c2_rv4162>;
 289                 reg = <0x68>;
 290                 interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
 291         };
 292 };
 293
 294 &i2c3 {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&pinctrl_i2c3>;
 297         status = "okay";
 298
 299         touch@48 {
 300                 compatible = "ti,tsc2004";
 301                 reg = <0x48>;
 302                 pinctrl-names = "default";
 303                 pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
 304                 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
 305                 wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
 306         };
 307 };
 308
 309 &i2c4 {
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_i2c4>;
 312         status = "okay";
 313
 314         codec: wm8960@1a {
 315                 compatible = "wlf,wm8960";
 316                 reg = <0x1a>;
 317                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 318                 clock-names = "mclk";
 319                 wlf,shared-lrclk;
 320         };
 321 };
 322
 323 &lcdif {
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&pinctrl_lcdif_dat
 326                      &pinctrl_lcdif_ctrl>;
 327         lcd-supply = <&reg_vref_3v3>;
 328         display = <&display0>;
 329         status = "okay";
 330
 331         display0: lcd-display {
 332                 bits-per-pixel = <16>;
 333                 bus-width = <18>;
 334
 335                 display-timings {
 336                         native-mode = <&t_lcd>;
 337                         t_lcd: t_lcd_default {
 338                                 /* default to Okaya display */
 339                                 clock-frequency = <30000000>;
 340                                 hactive = <800>;
 341                                 vactive = <480>;
 342                                 hfront-porch = <40>;
 343                                 hback-porch = <40>;
 344                                 hsync-len = <48>;
 345                                 vback-porch = <29>;
 346                                 vfront-porch = <13>;
 347                                 vsync-len = <3>;
 348                                 hsync-active = <0>;
 349                                 vsync-active = <0>;
 350                                 de-active = <1>;
 351                                 pixelclk-active = <0>;
 352                         };
 353                 };
 354         };
 355 };
 356
 357 &pwm1 {
 358         pinctrl-names = "default";
 359         pinctrl-0 = <&pinctrl_pwm1>;
 360         status = "okay";
 361 };
 362
 363 &pwm2 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_pwm2>;
 366         status = "okay";
 367 };
 368
 369 &uart1 {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_uart1>;
 372         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 373         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 374         status = "okay";
 375 };
 376
 377 &uart2 {
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&pinctrl_uart2>;
 380         assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 381         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 382         status = "okay";
 383 };
 384
 385 &uart3 {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_uart3>;
 388         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 389         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 390         status = "okay";
 391 };
 392
 393 &uart6 {
 394         pinctrl-names = "default";
 395         pinctrl-0 = <&pinctrl_uart6>;
 396         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 397         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 398         uart-has-rtscts;
 399         status = "okay";
 400 };
 401
 402 &usbotg1 {
 403         vbus-supply = <&reg_usb_otg1_vbus>;
 404         pinctrl-names = "default";
 405         pinctrl-0 = <&pinctrl_usbotg1>;
 406         status = "okay";
 407 };
 408
 409 &usbotg2 {
 410         vbus-supply = <&reg_usb_otg2_vbus>;
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&pinctrl_usbotg2>;
 413         dr_mode = "host";
 414         status = "okay";
 415 };
 416
 417 &usdhc1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_usdhc1>;
 420         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 421         vmmc-supply = <&vgen3_reg>;
 422         bus-width = <4>;
 423         fsl,tuning-step = <2>;
 424         wakeup-source;
 425         keep-power-in-suspend;
 426         status = "okay";
 427 };
 428
 429 &usdhc2 {
 430         #address-cells = <1>;
 431         #size-cells = <0>;
 432         pinctrl-names = "default";
 433         pinctrl-0 = <&pinctrl_usdhc2>;
 434         bus-width = <4>;
 435         non-removable;
 436         vmmc-supply = <&reg_wlan>;
 437         mmc-pwrseq = <&usdhc2_pwrseq>;
 438         cap-power-off-card;
 439         keep-power-in-suspend;
 440         status = "okay";
 441
 442         wlcore: wlcore@2 {
 443                 compatible = "ti,wl1271";
 444                 reg = <2>;
 445                 interrupt-parent = <&gpio4>;
 446                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 447                 ref-clock-frequency = <38400000>;
 448         };
 449 };
 450
 451 &usdhc3 {
 452         pinctrl-names = "default";
 453         pinctrl-0 = <&pinctrl_usdhc3>;
 454         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 455         assigned-clock-rates = <400000000>;
 456         bus-width = <8>;
 457         fsl,tuning-step = <2>;
 458         non-removable;
 459         status = "okay";
 460 };
 461
 462 &wdog1 {
 463         pinctrl-names = "default";
 464         pinctrl-0 = <&pinctrl_wdog1>;
 465         status = "okay";
 466 };
 467
 468 &iomuxc {
 469         pinctrl-names = "default";
 470         pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
 471
 472         pinctrl_hog_1: hoggrp-1 {
 473                 fsl,pins = <
 474                         MX7D_PAD_SD3_RESET_B__GPIO6_IO11        0x5d
 475                         MX7D_PAD_GPIO1_IO13__GPIO1_IO13         0x7d
 476                         MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x7d
 477                 >;
 478         };
 479
 480         pinctrl_enet1: enet1grp {
 481                 fsl,pins = <
 482                         MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 483                         MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 484                         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x3
 485                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x71
 486                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x71
 487                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x71
 488                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x71
 489                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x71
 490                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
 491                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x71
 492                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
 493                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
 494                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
 495                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x71
 496                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
 497                         MX7D_PAD_SD3_STROBE__GPIO6_IO10                 0x75
 498                 >;
 499         };
 500
 501         pinctrl_flexcan2: flexcan2grp {
 502                 fsl,pins = <
 503                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x7d
 504                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x7d
 505                         MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x7d
 506                 >;
 507         };
 508
 509         pinctrl_i2c1: i2c1grp {
 510                 fsl,pins = <
 511                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 512                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 513                 >;
 514         };
 515
 516         pinctrl_i2c2: i2c2grp {
 517                 fsl,pins = <
 518                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 519                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 520                 >;
 521         };
 522
 523         pinctrl_i2c2_rv4162: i2c2-rv4162grp {
 524                 fsl,pins = <
 525                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x7d
 526                 >;
 527         };
 528
 529         pinctrl_i2c3: i2c3grp {
 530                 fsl,pins = <
 531                         MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 532                         MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 533                 >;
 534         };
 535
 536         pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
 537                 fsl,pins = <
 538                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x79
 539                         MX7D_PAD_SD2_WP__GPIO5_IO10             0x7d
 540                 >;
 541         };
 542
 543         pinctrl_i2c4: i2c4grp {
 544                 fsl,pins = <
 545                         MX7D_PAD_I2C4_SDA__I2C4_SDA             0x4000007f
 546                         MX7D_PAD_I2C4_SCL__I2C4_SCL             0x4000007f
 547                 >;
 548         };
 549
 550         pinctrl_j2: j2grp {
 551                 fsl,pins = <
 552                         MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15       0x7d
 553                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x7d
 554                         MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12       0x7d
 555                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x7d
 556                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x7d
 557                         MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x7d
 558                         MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x7d
 559                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x7d
 560                         MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x7d
 561                         MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x7d
 562                         MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x7d
 563                         MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x7d
 564                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x7d
 565                         MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x7d
 566                         MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14       0x7d
 567                         MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x7d
 568                         MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13       0x7d
 569                         MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x7d
 570                         MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x7d
 571                         MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21       0x7d
 572                         MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x7d
 573                         MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x7d
 574                         MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22       0x7d
 575                         MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x7d
 576                         MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20       0x7d
 577                         MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x7d
 578                         MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19       0x7d
 579                         MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x7d
 580                         MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x7d
 581                         MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x7d
 582                         MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x7d
 583                         MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x7d
 584                         MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x7d
 585                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x7d
 586                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x7d
 587                 >;
 588         };
 589
 590         pinctrl_lcdif_dat: lcdifdatgrp {
 591                 fsl,pins = <
 592                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 593                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 594                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 595                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 596                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 597                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 598                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 599                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 600                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 601                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 602                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 603                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 604                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 605                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 606                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 607                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 608                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 609                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 610                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 611                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 612                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 613                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 614                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 615                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 616                 >;
 617         };
 618
 619         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 620                 fsl,pins = <
 621                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 622                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 623                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 624                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 625                 >;
 626         };
 627
 628         pinctrl_pwm2: pwm2grp {
 629                 fsl,pins = <
 630                         MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x7d
 631                 >;
 632         };
 633
 634         pinctrl_uart1: uart1grp {
 635                 fsl,pins = <
 636                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 637                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 638                 >;
 639         };
 640
 641         pinctrl_uart2: uart2grp {
 642                 fsl,pins = <
 643                         MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX    0x79
 644                         MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX    0x79
 645                 >;
 646         };
 647
 648         pinctrl_uart3: uart3grp {
 649                 fsl,pins = <
 650                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 651                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 652                         MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x7d
 653                 >;
 654         };
 655
 656         pinctrl_uart6: uart6grp {
 657                 fsl,pins = <
 658                         MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 659                         MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 660                         MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 661                         MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 662                 >;
 663         };
 664
 665         pinctrl_usbotg2: usbotg2grp {
 666                 fsl,pins = <
 667                         MX7D_PAD_UART3_RTS_B__USB_OTG2_OC       0x7d
 668                         MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 669                 >;
 670         };
 671
 672         pinctrl_usdhc1: usdhc1grp {
 673                 fsl,pins = <
 674                         MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 675                         MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 676                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 677                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 678                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 679                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 680                         MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x75
 681                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x75
 682                 >;
 683         };
 684
 685         pinctrl_usdhc2: usdhc2grp {
 686                 fsl,pins = <
 687                         MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 688                         MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 689                         MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 690                         MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 691                         MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 692                         MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 693                         MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x59
 694                         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x59
 695                 >;
 696         };
 697
 698         pinctrl_usdhc3: usdhc3grp {
 699                 fsl,pins = <
 700                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 701                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 702                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 703                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 704                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 705                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 706                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 707                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 708                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 709                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 710                 >;
 711         };
 712 };
 713
 714 &iomuxc_lpsr {
 715         pinctrl-names = "default";
 716         pinctrl-0 = <&pinctrl_hog_2>;
 717
 718         pinctrl_hog_2: hoggrp-2 {
 719                 fsl,pins = <
 720                         MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2     0x7d
 721                         MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2     0x7d
 722                 >;
 723         };
 724
 725         pinctrl_backlight_j9: backlightj9grp {
 726                 fsl,pins = <
 727                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x7d
 728                 >;
 729         };
 730
 731         pinctrl_pwm1: pwm1grp {
 732                 fsl,pins = <
 733                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT      0x7d
 734                 >;
 735         };
 736
 737         pinctrl_usbotg1: usbotg1grp {
 738                 fsl,pins = <
 739                         MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC   0x7d
 740                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14
 741                 >;
 742         };
 743
 744         pinctrl_wdog1: wdog1grp {
 745                 fsl,pins = <
 746                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x75
 747                 >;
 748         };
 749 };