1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2016-2022 Toradex
6 #include <dt-bindings/pwm/pwm.h>
14 backlight: backlight {
15 brightness-levels = <0 45 63 88 119 158 203 255>;
16 compatible = "pwm-backlight";
17 default-brightness-level = <4>;
18 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_bl_on>;
21 power-supply = <®_module_3v3>;
22 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
27 stdout-path = "serial0:115200n8";
30 extcon_usbc_det: usbc-det {
31 compatible = "linux,extcon-usb-gpio";
33 id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_usbc_det>;
39 compatible = "gpio-keys";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpiokeys>;
44 debounce-interval = <10>;
45 gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
47 linux,code = <KEY_WAKEUP>;
52 panel_dpi: panel-dpi {
53 backlight = <&backlight>;
54 compatible = "edt,et057090dhu";
55 power-supply = <®_3v3>;
59 lcd_panel_in: endpoint {
60 remote-endpoint = <&lcdif_out>;
65 reg_3v3: regulator-3v3 {
66 compatible = "regulator-fixed";
68 regulator-max-microvolt = <3300000>;
69 regulator-min-microvolt = <3300000>;
70 regulator-name = "3.3V";
73 reg_5v0: regulator-5v0 {
74 compatible = "regulator-fixed";
76 regulator-max-microvolt = <5000000>;
77 regulator-min-microvolt = <5000000>;
78 regulator-name = "5V";
81 reg_module_3v3: regulator-module-3v3 {
82 compatible = "regulator-fixed";
84 regulator-max-microvolt = <3300000>;
85 regulator-min-microvolt = <3300000>;
86 regulator-name = "+V3.3";
89 reg_module_3v3_avdd: regulator-module-3v3-avdd {
90 compatible = "regulator-fixed";
92 regulator-max-microvolt = <3300000>;
93 regulator-min-microvolt = <3300000>;
94 regulator-name = "+V3.3_AVDD_AUDIO";
97 reg_module_3v3_eth: regulator-module-3v3-eth {
98 compatible = "regulator-fixed";
99 off-on-delay-us = <200000>;
100 regulator-name = "+V3.3_ETH";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
104 startup-delay-us = <200000>;
105 vin-supply = <®_LDO1>;
108 reg_usbh_vbus: regulator-usbh-vbus {
109 compatible = "regulator-fixed";
110 gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_usbh_reg>;
113 regulator-max-microvolt = <5000000>;
114 regulator-min-microvolt = <5000000>;
115 regulator-name = "VCC_USB[1-4]";
116 vin-supply = <®_5v0>;
120 compatible = "simple-audio-card";
121 simple-audio-card,bitclock-master = <&dailink_master>;
122 simple-audio-card,format = "i2s";
123 simple-audio-card,frame-master = <&dailink_master>;
124 simple-audio-card,name = "imx7-sgtl5000";
126 simple-audio-card,cpu {
130 dailink_master: simple-audio-card,codec {
131 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
132 sound-dai = <&codec>;
137 /* Colibri AD0 to AD3 */
139 vref-supply = <®_DCDC3>;
142 /* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */
145 cpu-supply = <®_DCDC2>;
150 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
155 /* Colibri Fast Ethernet */
157 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
158 assigned-clock-rates = <0>, <100000000>;
159 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
160 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
161 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
162 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
163 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
164 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
165 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
167 phy-handle = <ðphy0>;
169 phy-supply = <®_module_3v3_eth>;
170 pinctrl-names = "default", "sleep";
171 pinctrl-0 = <&pinctrl_enet1>;
172 pinctrl-1 = <&pinctrl_enet1_sleep>;
175 #address-cells = <1>;
178 /* Micrel KSZ8041RNL */
179 ethphy0: ethernet-phy@0 {
180 compatible = "ethernet-phy-ieee802.3-c22";
182 micrel,led-mode = <0>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_flexcan1>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_flexcan2>;
199 gpio-line-names = "SODIMM_43",
218 gpio-line-names = "SODIMM_111",
253 gpio-line-names = "SODIMM_56",
285 gpio-line-names = "SODIMM_35",
312 gpio-line-names = "SODIMM_69",
333 gpio-line-names = "",
359 gpio-line-names = "",
376 /* NAND on such SKUs */
379 nand-ecc-mode = "hw";
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_gpmi_nand>;
385 /* On-module Power I2C */
387 clock-frequency = <100000>;
388 pinctrl-names = "default", "gpio";
389 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
390 pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
391 scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
392 sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
396 #sound-dai-cells = <0>;
397 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
398 compatible = "fsl,sgtl5000";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_sai1_mclk>;
402 VDDA-supply = <®_module_3v3_avdd>;
403 VDDD-supply = <®_DCDC3>;
404 VDDIO-supply = <®_module_3v3>;
407 ad7879_ts: touchscreen@2c {
408 adi,acquisition-time = /bits/ 8 <1>;
409 adi,averaging = /bits/ 8 <1>;
410 adi,conversion-interval = /bits/ 8 <255>;
411 adi,first-conversion-delay = /bits/ 8 <3>;
412 adi,median-filter-size = /bits/ 8 <2>;
413 adi,resistance-plate-x = <120>;
414 compatible = "adi,ad7879-1";
415 interrupt-parent = <&gpio1>;
416 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
418 touchscreen-max-pressure = <4096>;
423 compatible = "ricoh,rn5t567";
430 regulator-max-microvolt = <1100000>;
431 regulator-min-microvolt = <1000000>;
432 regulator-name = "+V1.0_SOC";
438 regulator-max-microvolt = <1100000>;
439 regulator-min-microvolt = <975000>;
440 regulator-name = "+V1.1_ARM";
446 regulator-max-microvolt = <1800000>;
447 regulator-min-microvolt = <1800000>;
448 regulator-name = "+V1.8";
454 regulator-max-microvolt = <1350000>;
455 regulator-min-microvolt = <1350000>;
456 regulator-name = "+V1.35_DRAM";
461 regulator-max-microvolt = <3300000>;
462 regulator-min-microvolt = <3300000>;
463 regulator-name = "PWR_EN_+V3.3_ETH";
469 regulator-max-microvolt = <3300000>;
470 regulator-min-microvolt = <1800000>;
471 regulator-name = "+V1.8_SD";
477 regulator-max-microvolt = <3300000>;
478 regulator-min-microvolt = <3300000>;
479 regulator-name = "PWR_EN_+V3.3_LPSR";
485 regulator-max-microvolt = <1800000>;
486 regulator-min-microvolt = <1800000>;
487 regulator-name = "+V1.8_LPSR";
493 regulator-max-microvolt = <3300000>;
494 regulator-min-microvolt = <3300000>;
495 regulator-name = "PWR_EN_+V3.3";
501 /* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
503 clock-frequency = <100000>;
504 pinctrl-names = "default", "gpio";
505 pinctrl-0 = <&pinctrl_i2c4>;
506 pinctrl-1 = <&pinctrl_i2c4_recovery>;
507 scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
508 sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
511 /* Atmel maxtouch controller */
512 atmel_mxt_ts: touchscreen@4a {
513 compatible = "atmel,maxtouch";
514 interrupt-parent = <&gpio2>;
515 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
516 pinctrl-names = "default";
517 pinctrl-0 = <&pinctrl_atmel_connector>;
519 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
523 /* M41T0M6 real time clock on carrier board */
525 compatible = "st,m41t0";
532 assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>;
533 assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&pinctrl_lcdif_dat
536 &pinctrl_lcdif_ctrl>;
540 lcdif_out: endpoint {
541 remote-endpoint = <&lcd_panel_in>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_pwm1>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_pwm2>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_pwm3>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_pwm4>;
571 vin-supply = <®_DCDC3>; /* VDDA_1P8_IN */
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_sai1>;
582 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
583 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
592 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
593 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_uart2>;
602 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
603 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&pinctrl_uart3>;
612 extcon = <0>, <&extcon_usbc_det>;
617 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
620 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
621 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
622 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
623 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
624 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>;
625 vmmc-supply = <®_3v3>;
626 vqmmc-supply = <®_LDO2>;
630 /* eMMC on 1GB (eMMC) SKUs */
632 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
633 assigned-clock-rates = <400000000>;
635 fsl,tuning-step = <2>;
637 pinctrl-names = "default", "state_100mhz", "state_200mhz";
638 pinctrl-0 = <&pinctrl_usdhc3>;
639 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
640 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
641 sdhci-caps-mask = <0x80000000 0x0>;
642 vmmc-supply = <®_module_3v3>;
643 vqmmc-supply = <®_DCDC3>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
651 * Atmel MXT touchsceen + Capacitive Touch Adapter
652 * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3.
653 * Don't use them simultaneously.
655 pinctrl_atmel_adapter: atmelconnectorgrp {
657 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */
658 MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */
662 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
663 pinctrl_atmel_connector: atmeladaptergrp {
665 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */
666 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */
670 pinctrl_can_int: canintgrp {
672 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
676 pinctrl_ecspi3: ecspi3grp {
678 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */
679 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */
680 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */
684 pinctrl_ecspi3_cs: ecspi3csgrp {
686 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */
690 pinctrl_enet1: enet1grp {
692 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
693 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
694 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
695 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
696 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
697 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
698 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
699 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
700 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
701 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
705 pinctrl_enet1_sleep: enet1-sleepgrp {
707 MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
708 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
709 MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
710 MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
711 MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
712 MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
713 MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
714 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
715 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
716 MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
720 pinctrl_flexcan1: flexcan1grp {
722 MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
723 MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
727 pinctrl_flexcan2: flexcan2grp {
729 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
730 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
734 pinctrl_gpio1: gpio1grp {
736 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
737 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
738 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
739 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
740 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
741 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
742 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
743 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
744 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
745 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
746 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
747 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
748 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
749 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
750 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
751 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
752 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
753 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
754 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
755 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
756 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
757 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
758 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
759 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
760 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
761 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
762 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
763 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
764 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
765 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
766 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
767 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
768 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
769 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
770 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
771 MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
772 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
773 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
777 pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */
779 MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
780 MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
781 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
782 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
783 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
784 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
785 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
786 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
787 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
788 MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
789 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
790 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
794 pinctrl_gpio3: gpio3grp { /* LCD 18-23 */
796 MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
797 MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
798 MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
799 MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
800 MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
801 MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
805 pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */
807 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
808 MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
812 pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */
814 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
815 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
819 pinctrl_gpio_bl_on: gpioblongrp {
821 MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
825 pinctrl_gpmi_nand: gpminandgrp {
827 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
828 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
829 MX7D_PAD_SD3_CLK__NAND_CLE 0x71
830 MX7D_PAD_SD3_CMD__NAND_ALE 0x71
831 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
832 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
833 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
834 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
835 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
836 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
837 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
838 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
839 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
840 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
844 pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */
846 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
850 pinctrl_i2c4: i2c4grp {
852 MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */
853 MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */
857 pinctrl_i2c4_recovery: i2c4-recoverygrp {
859 MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
860 MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
864 pinctrl_lcdif_dat: lcdifdatgrp {
866 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */
867 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */
868 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */
869 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */
870 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */
871 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */
872 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */
873 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */
874 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */
875 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */
876 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */
877 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */
878 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */
879 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */
880 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */
881 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */
882 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */
883 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */
887 pinctrl_lcdif_dat_24: lcdifdat24grp {
889 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */
890 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */
891 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */
892 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */
893 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */
894 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */
898 pinctrl_lcdif_ctrl: lcdifctrlgrp {
900 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */
901 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */
902 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */
903 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */
907 pinctrl_lvds_transceiver: lvdstx {
909 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
910 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
911 MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
912 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
916 pinctrl_pwm1: pwm1grp {
918 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */
919 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */
923 pinctrl_pwm2: pwm2grp {
925 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */
929 pinctrl_pwm3: pwm3grp {
931 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */
935 pinctrl_pwm4: pwm4grp {
937 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */
938 MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */
942 pinctrl_uart1: uart1grp {
944 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */
945 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */
946 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */
947 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */
951 pinctrl_uart1_ctrl1: uart1ctrl1grp {
953 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */
954 MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */
958 pinctrl_uart2: uart2grp {
960 MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */
961 MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */
962 MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */
963 MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */
966 pinctrl_uart3: uart3grp {
968 MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */
969 MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */
973 pinctrl_usbc_det: usbcdetgrp {
975 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */
979 pinctrl_usbh_reg: usbhreggrp {
981 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */
985 pinctrl_usdhc1: usdhc1grp {
987 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */
988 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */
989 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */
990 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */
991 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */
992 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */
996 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
998 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
999 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
1000 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
1001 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
1002 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
1003 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
1007 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1009 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
1010 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
1011 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
1012 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
1013 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
1014 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
1018 /* Avoid backfeeding with removed card power. */
1019 pinctrl_usdhc1_sleep: usdhc1-slpgrp {
1021 MX7D_PAD_SD1_CMD__SD1_CMD 0x10
1022 MX7D_PAD_SD1_CLK__SD1_CLK 0x10
1023 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10
1024 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10
1025 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10
1026 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10
1030 pinctrl_usdhc3: usdhc3grp {
1032 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
1033 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
1034 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
1035 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
1036 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
1037 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
1038 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
1039 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
1040 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
1041 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
1042 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
1046 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1048 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
1049 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
1050 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
1051 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
1052 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
1053 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
1054 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
1055 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
1056 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
1057 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
1058 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
1062 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1064 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
1065 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
1066 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
1067 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
1068 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
1069 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
1070 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
1071 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
1072 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
1073 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
1074 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
1078 pinctrl_sai1: sai1grp {
1080 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
1081 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
1082 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
1083 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
1087 pinctrl_sai1_mclk: sai1mclkgrp {
1089 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&pinctrl_gpio_lpsr>;
1098 pinctrl_cd_usdhc1: cdusdhc1grp {
1100 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */
1104 pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp {
1106 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0
1110 pinctrl_gpio_lpsr: gpiolpsrgrp {
1112 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */
1113 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */
1117 pinctrl_gpiokeys: gpiokeysgrp {
1119 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */
1123 pinctrl_i2c1: i2c1grp {
1125 MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
1126 MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
1130 pinctrl_i2c1_recovery: i2c1-recoverygrp {
1132 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
1133 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
1137 pinctrl_uart1_ctrl2: uart1ctrl2grp {
1139 MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */
1140 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */