arch/arm/boot/dts/imx6ul.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6ul-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6ul-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          */
  19         chosen {};
  20
  21         aliases {
  22                 ethernet0 = &fec1;
  23                 ethernet1 = &fec2;
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 gpio4 = &gpio5;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 i2c3 = &i2c4;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 serial5 = &uart6;
  41                 serial6 = &uart7;
  42                 serial7 = &uart8;
  43                 sai1 = &sai1;
  44                 sai2 = &sai2;
  45                 sai3 = &sai3;
  46                 spi0 = &ecspi1;
  47                 spi1 = &ecspi2;
  48                 spi2 = &ecspi3;
  49                 spi3 = &ecspi4;
  50                 usb0 = &usbotg1;
  51                 usb1 = &usbotg2;
  52                 usbphy0 = &usbphy1;
  53                 usbphy1 = &usbphy2;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@0 {
  61                         compatible = "arm,cortex-a7";
  62                         device_type = "cpu";
  63                         reg = <0>;
  64                         clock-frequency = <696000000>;
  65                         clock-latency = <61036>; /* two CLK32 periods */
  66                         #cooling-cells = <2>;
  67                         operating-points =
  68                                 /* kHz  uV */
  69                                 <696000 1275000>,
  70                                 <528000 1175000>,
  71                                 <396000 1025000>,
  72                                 <198000 950000>;
  73                         fsl,soc-operating-points =
  74                                 /* KHz  uV */
  75                                 <696000 1275000>,
  76                                 <528000 1175000>,
  77                                 <396000 1175000>,
  78                                 <198000 1175000>;
  79                         clocks = <&clks IMX6UL_CLK_ARM>,
  80                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  81                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  82                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  83                                  <&clks IMX6UL_CLK_STEP>,
  84                                  <&clks IMX6UL_CLK_PLL1_SW>,
  85                                  <&clks IMX6UL_CLK_PLL1_SYS>;
  86                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  87                                       "secondary_sel", "step", "pll1_sw",
  88                                       "pll1_sys";
  89                         arm-supply = <&reg_arm>;
  90                         soc-supply = <&reg_soc>;
  91                         nvmem-cells = <&cpu_speed_grade>;
  92                         nvmem-cell-names = "speed_grade";
  93                 };
  94         };
  95
  96         timer {
  97                 compatible = "arm,armv7-timer";
  98                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 100                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 101                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 102                 interrupt-parent = <&intc>;
 103                 status = "disabled";
 104         };
 105
 106         ckil: clock-cli {
 107                 compatible = "fixed-clock";
 108                 #clock-cells = <0>;
 109                 clock-frequency = <32768>;
 110                 clock-output-names = "ckil";
 111         };
 112
 113         osc: clock-osc {
 114                 compatible = "fixed-clock";
 115                 #clock-cells = <0>;
 116                 clock-frequency = <24000000>;
 117                 clock-output-names = "osc";
 118         };
 119
 120         ipp_di0: clock-di0 {
 121                 compatible = "fixed-clock";
 122                 #clock-cells = <0>;
 123                 clock-frequency = <0>;
 124                 clock-output-names = "ipp_di0";
 125         };
 126
 127         ipp_di1: clock-di1 {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <0>;
 131                 clock-output-names = "ipp_di1";
 132         };
 133
 134         tempmon: tempmon {
 135                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 136                 interrupt-parent = <&gpc>;
 137                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 138                 fsl,tempmon = <&anatop>;
 139                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 140                 nvmem-cell-names = "calib", "temp_grade";
 141                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 142         };
 143
 144         pmu {
 145                 compatible = "arm,cortex-a7-pmu";
 146                 interrupt-parent = <&gpc>;
 147                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 148         };
 149
 150         soc {
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 compatible = "simple-bus";
 154                 interrupt-parent = <&gpc>;
 155                 ranges;
 156
 157                 ocram: sram@900000 {
 158                         compatible = "mmio-sram";
 159                         reg = <0x00900000 0x20000>;
 160                         ranges = <0 0x00900000 0x20000>;
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                 };
 164
 165                 intc: interrupt-controller@a01000 {
 166                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 167                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 168                         #interrupt-cells = <3>;
 169                         interrupt-controller;
 170                         interrupt-parent = <&intc>;
 171                         reg = <0x00a01000 0x1000>,
 172                               <0x00a02000 0x2000>,
 173                               <0x00a04000 0x2000>,
 174                               <0x00a06000 0x2000>;
 175                 };
 176
 177                 dma_apbh: dma-controller@1804000 {
 178                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 179                         reg = <0x01804000 0x2000>;
 180                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 184                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 185                         #dma-cells = <1>;
 186                         dma-channels = <4>;
 187                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 188                 };
 189
 190                 gpmi: gpmi-nand@1806000 {
 191                         compatible = "fsl,imx6q-gpmi-nand";
 192                         #address-cells = <1>;
 193                         #size-cells = <1>;
 194                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 195                         reg-names = "gpmi-nand", "bch";
 196                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 197                         interrupt-names = "bch";
 198                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 199                                  <&clks IMX6UL_CLK_GPMI_APB>,
 200                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 201                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 202                                  <&clks IMX6UL_CLK_PER_BCH>;
 203                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 204                                       "gpmi_bch_apb", "per1_bch";
 205                         dmas = <&dma_apbh 0>;
 206                         dma-names = "rx-tx";
 207                         status = "disabled";
 208                 };
 209
 210                 aips1: aips-bus@2000000 {
 211                         compatible = "fsl,aips-bus", "simple-bus";
 212                         #address-cells = <1>;
 213                         #size-cells = <1>;
 214                         reg = <0x02000000 0x100000>;
 215                         ranges;
 216
 217                         spba-bus@2000000 {
 218                                 compatible = "fsl,spba-bus", "simple-bus";
 219                                 #address-cells = <1>;
 220                                 #size-cells = <1>;
 221                                 reg = <0x02000000 0x40000>;
 222                                 ranges;
 223
 224                                 ecspi1: spi@2008000 {
 225                                         #address-cells = <1>;
 226                                         #size-cells = <0>;
 227                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 228                                         reg = <0x02008000 0x4000>;
 229                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 230                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 231                                                  <&clks IMX6UL_CLK_ECSPI1>;
 232                                         clock-names = "ipg", "per";
 233                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 234                                         dma-names = "rx", "tx";
 235                                         status = "disabled";
 236                                 };
 237
 238                                 ecspi2: spi@200c000 {
 239                                         #address-cells = <1>;
 240                                         #size-cells = <0>;
 241                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 242                                         reg = <0x0200c000 0x4000>;
 243                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 244                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 245                                                  <&clks IMX6UL_CLK_ECSPI2>;
 246                                         clock-names = "ipg", "per";
 247                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 248                                         dma-names = "rx", "tx";
 249                                         status = "disabled";
 250                                 };
 251
 252                                 ecspi3: spi@2010000 {
 253                                         #address-cells = <1>;
 254                                         #size-cells = <0>;
 255                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 256                                         reg = <0x02010000 0x4000>;
 257                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 258                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 259                                                  <&clks IMX6UL_CLK_ECSPI3>;
 260                                         clock-names = "ipg", "per";
 261                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 262                                         dma-names = "rx", "tx";
 263                                         status = "disabled";
 264                                 };
 265
 266                                 ecspi4: spi@2014000 {
 267                                         #address-cells = <1>;
 268                                         #size-cells = <0>;
 269                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 270                                         reg = <0x02014000 0x4000>;
 271                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 272                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 273                                                  <&clks IMX6UL_CLK_ECSPI4>;
 274                                         clock-names = "ipg", "per";
 275                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 276                                         dma-names = "rx", "tx";
 277                                         status = "disabled";
 278                                 };
 279
 280                                 uart7: serial@2018000 {
 281                                         compatible = "fsl,imx6ul-uart",
 282                                                      "fsl,imx6q-uart";
 283                                         reg = <0x02018000 0x4000>;
 284                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 286                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 287                                         clock-names = "ipg", "per";
 288                                         status = "disabled";
 289                                 };
 290
 291                                 uart1: serial@2020000 {
 292                                         compatible = "fsl,imx6ul-uart",
 293                                                      "fsl,imx6q-uart";
 294                                         reg = <0x02020000 0x4000>;
 295                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 296                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 297                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 298                                         clock-names = "ipg", "per";
 299                                         status = "disabled";
 300                                 };
 301
 302                                 uart8: serial@2024000 {
 303                                         compatible = "fsl,imx6ul-uart",
 304                                                      "fsl,imx6q-uart";
 305                                         reg = <0x02024000 0x4000>;
 306                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 307                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 308                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 309                                         clock-names = "ipg", "per";
 310                                         status = "disabled";
 311                                 };
 312
 313                                 sai1: sai@2028000 {
 314                                         #sound-dai-cells = <0>;
 315                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 316                                         reg = <0x02028000 0x4000>;
 317                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 318                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 319                                                  <&clks IMX6UL_CLK_SAI1>,
 320                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 321                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 322                                         dmas = <&sdma 35 24 0>,
 323                                                <&sdma 36 24 0>;
 324                                         dma-names = "rx", "tx";
 325                                         status = "disabled";
 326                                 };
 327
 328                                 sai2: sai@202c000 {
 329                                         #sound-dai-cells = <0>;
 330                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 331                                         reg = <0x0202c000 0x4000>;
 332                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 333                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 334                                                  <&clks IMX6UL_CLK_SAI2>,
 335                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 336                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 337                                         dmas = <&sdma 37 24 0>,
 338                                                <&sdma 38 24 0>;
 339                                         dma-names = "rx", "tx";
 340                                         status = "disabled";
 341                                 };
 342
 343                                 sai3: sai@2030000 {
 344                                         #sound-dai-cells = <0>;
 345                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 346                                         reg = <0x02030000 0x4000>;
 347                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 348                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 349                                                  <&clks IMX6UL_CLK_SAI3>,
 350                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 351                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 352                                         dmas = <&sdma 39 24 0>,
 353                                                <&sdma 40 24 0>;
 354                                         dma-names = "rx", "tx";
 355                                         status = "disabled";
 356                                 };
 357                         };
 358
 359                         tsc: tsc@2040000 {
 360                                 compatible = "fsl,imx6ul-tsc";
 361                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 362                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 363                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 364                                 clocks = <&clks IMX6UL_CLK_IPG>,
 365                                          <&clks IMX6UL_CLK_ADC2>;
 366                                 clock-names = "tsc", "adc";
 367                                 status = "disabled";
 368                         };
 369
 370                         pwm1: pwm@2080000 {
 371                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 372                                 reg = <0x02080000 0x4000>;
 373                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 374                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 375                                          <&clks IMX6UL_CLK_PWM1>;
 376                                 clock-names = "ipg", "per";
 377                                 #pwm-cells = <2>;
 378                                 status = "disabled";
 379                         };
 380
 381                         pwm2: pwm@2084000 {
 382                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 383                                 reg = <0x02084000 0x4000>;
 384                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 385                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 386                                          <&clks IMX6UL_CLK_PWM2>;
 387                                 clock-names = "ipg", "per";
 388                                 #pwm-cells = <2>;
 389                                 status = "disabled";
 390                         };
 391
 392                         pwm3: pwm@2088000 {
 393                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 394                                 reg = <0x02088000 0x4000>;
 395                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 396                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 397                                          <&clks IMX6UL_CLK_PWM3>;
 398                                 clock-names = "ipg", "per";
 399                                 #pwm-cells = <2>;
 400                                 status = "disabled";
 401                         };
 402
 403                         pwm4: pwm@208c000 {
 404                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 405                                 reg = <0x0208c000 0x4000>;
 406                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 407                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 408                                          <&clks IMX6UL_CLK_PWM4>;
 409                                 clock-names = "ipg", "per";
 410                                 #pwm-cells = <2>;
 411                                 status = "disabled";
 412                         };
 413
 414                         can1: flexcan@2090000 {
 415                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 416                                 reg = <0x02090000 0x4000>;
 417                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 419                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 420                                 clock-names = "ipg", "per";
 421                                 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
 422                                 status = "disabled";
 423                         };
 424
 425                         can2: flexcan@2094000 {
 426                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 427                                 reg = <0x02094000 0x4000>;
 428                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 429                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 430                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 431                                 clock-names = "ipg", "per";
 432                                 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
 433                                 status = "disabled";
 434                         };
 435
 436                         gpt1: timer@2098000 {
 437                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 438                                 reg = <0x02098000 0x4000>;
 439                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 440                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 441                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 442                                 clock-names = "ipg", "per";
 443                         };
 444
 445                         gpio1: gpio@209c000 {
 446                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 447                                 reg = <0x0209c000 0x4000>;
 448                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 449                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 450                                 clocks = <&clks IMX6UL_CLK_GPIO1>;
 451                                 gpio-controller;
 452                                 #gpio-cells = <2>;
 453                                 interrupt-controller;
 454                                 #interrupt-cells = <2>;
 455                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 456                                               <&iomuxc 16 33 16>;
 457                         };
 458
 459                         gpio2: gpio@20a0000 {
 460                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 461                                 reg = <0x020a0000 0x4000>;
 462                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 463                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 464                                 clocks = <&clks IMX6UL_CLK_GPIO2>;
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 interrupt-controller;
 468                                 #interrupt-cells = <2>;
 469                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 470                         };
 471
 472                         gpio3: gpio@20a4000 {
 473                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 474                                 reg = <0x020a4000 0x4000>;
 475                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 476                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 477                                 clocks = <&clks IMX6UL_CLK_GPIO3>;
 478                                 gpio-controller;
 479                                 #gpio-cells = <2>;
 480                                 interrupt-controller;
 481                                 #interrupt-cells = <2>;
 482                                 gpio-ranges = <&iomuxc 0 65 29>;
 483                         };
 484
 485                         gpio4: gpio@20a8000 {
 486                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 487                                 reg = <0x020a8000 0x4000>;
 488                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 489                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 490                                 clocks = <&clks IMX6UL_CLK_GPIO4>;
 491                                 gpio-controller;
 492                                 #gpio-cells = <2>;
 493                                 interrupt-controller;
 494                                 #interrupt-cells = <2>;
 495                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 496                         };
 497
 498                         gpio5: gpio@20ac000 {
 499                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 500                                 reg = <0x020ac000 0x4000>;
 501                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 502                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 503                                 clocks = <&clks IMX6UL_CLK_GPIO5>;
 504                                 gpio-controller;
 505                                 #gpio-cells = <2>;
 506                                 interrupt-controller;
 507                                 #interrupt-cells = <2>;
 508                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 509                         };
 510
 511                         fec2: ethernet@20b4000 {
 512                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 513                                 reg = <0x020b4000 0x4000>;
 514                                 interrupt-names = "int0", "pps";
 515                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 516                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 517                                 clocks = <&clks IMX6UL_CLK_ENET>,
 518                                          <&clks IMX6UL_CLK_ENET_AHB>,
 519                                          <&clks IMX6UL_CLK_ENET_PTP>,
 520                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 521                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 522                                 clock-names = "ipg", "ahb", "ptp",
 523                                               "enet_clk_ref", "enet_out";
 524                                 fsl,num-tx-queues = <1>;
 525                                 fsl,num-rx-queues = <1>;
 526                                 status = "disabled";
 527                         };
 528
 529                         kpp: kpp@20b8000 {
 530                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 531                                 reg = <0x020b8000 0x4000>;
 532                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 533                                 clocks = <&clks IMX6UL_CLK_KPP>;
 534                                 status = "disabled";
 535                         };
 536
 537                         wdog1: wdog@20bc000 {
 538                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 539                                 reg = <0x020bc000 0x4000>;
 540                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 541                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 542                         };
 543
 544                         wdog2: wdog@20c0000 {
 545                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 546                                 reg = <0x020c0000 0x4000>;
 547                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 548                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 549                                 status = "disabled";
 550                         };
 551
 552                         clks: ccm@20c4000 {
 553                                 compatible = "fsl,imx6ul-ccm";
 554                                 reg = <0x020c4000 0x4000>;
 555                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 556                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 557                                 #clock-cells = <1>;
 558                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 559                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 560                         };
 561
 562                         anatop: anatop@20c8000 {
 563                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 564                                              "syscon", "simple-bus";
 565                                 reg = <0x020c8000 0x1000>;
 566                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 567                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 568                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 569
 570                                 reg_3p0: regulator-3p0 {
 571                                         compatible = "fsl,anatop-regulator";
 572                                         regulator-name = "vdd3p0";
 573                                         regulator-min-microvolt = <2625000>;
 574                                         regulator-max-microvolt = <3400000>;
 575                                         anatop-reg-offset = <0x120>;
 576                                         anatop-vol-bit-shift = <8>;
 577                                         anatop-vol-bit-width = <5>;
 578                                         anatop-min-bit-val = <0>;
 579                                         anatop-min-voltage = <2625000>;
 580                                         anatop-max-voltage = <3400000>;
 581                                         anatop-enable-bit = <0>;
 582                                 };
 583
 584                                 reg_arm: regulator-vddcore {
 585                                         compatible = "fsl,anatop-regulator";
 586                                         regulator-name = "cpu";
 587                                         regulator-min-microvolt = <725000>;
 588                                         regulator-max-microvolt = <1450000>;
 589                                         regulator-always-on;
 590                                         anatop-reg-offset = <0x140>;
 591                                         anatop-vol-bit-shift = <0>;
 592                                         anatop-vol-bit-width = <5>;
 593                                         anatop-delay-reg-offset = <0x170>;
 594                                         anatop-delay-bit-shift = <24>;
 595                                         anatop-delay-bit-width = <2>;
 596                                         anatop-min-bit-val = <1>;
 597                                         anatop-min-voltage = <725000>;
 598                                         anatop-max-voltage = <1450000>;
 599                                 };
 600
 601                                 reg_soc: regulator-vddsoc {
 602                                         compatible = "fsl,anatop-regulator";
 603                                         regulator-name = "vddsoc";
 604                                         regulator-min-microvolt = <725000>;
 605                                         regulator-max-microvolt = <1450000>;
 606                                         regulator-always-on;
 607                                         anatop-reg-offset = <0x140>;
 608                                         anatop-vol-bit-shift = <18>;
 609                                         anatop-vol-bit-width = <5>;
 610                                         anatop-delay-reg-offset = <0x170>;
 611                                         anatop-delay-bit-shift = <28>;
 612                                         anatop-delay-bit-width = <2>;
 613                                         anatop-min-bit-val = <1>;
 614                                         anatop-min-voltage = <725000>;
 615                                         anatop-max-voltage = <1450000>;
 616                                 };
 617                         };
 618
 619                         usbphy1: usbphy@20c9000 {
 620                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 621                                 reg = <0x020c9000 0x1000>;
 622                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 623                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 624                                 phy-3p0-supply = <&reg_3p0>;
 625                                 fsl,anatop = <&anatop>;
 626                         };
 627
 628                         usbphy2: usbphy@20ca000 {
 629                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 630                                 reg = <0x020ca000 0x1000>;
 631                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 632                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 633                                 phy-3p0-supply = <&reg_3p0>;
 634                                 fsl,anatop = <&anatop>;
 635                         };
 636
 637                         snvs: snvs@20cc000 {
 638                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 639                                 reg = <0x020cc000 0x4000>;
 640
 641                                 snvs_rtc: snvs-rtc-lp {
 642                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 643                                         regmap = <&snvs>;
 644                                         offset = <0x34>;
 645                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 646                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 647                                 };
 648
 649                                 snvs_poweroff: snvs-poweroff {
 650                                         compatible = "syscon-poweroff";
 651                                         regmap = <&snvs>;
 652                                         offset = <0x38>;
 653                                         value = <0x60>;
 654                                         mask = <0x60>;
 655                                         status = "disabled";
 656                                 };
 657
 658                                 snvs_pwrkey: snvs-powerkey {
 659                                         compatible = "fsl,sec-v4.0-pwrkey";
 660                                         regmap = <&snvs>;
 661                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 662                                         linux,keycode = <KEY_POWER>;
 663                                         wakeup-source;
 664                                         status = "disabled";
 665                                 };
 666
 667                                 snvs_lpgpr: snvs-lpgpr {
 668                                         compatible = "fsl,imx6ul-snvs-lpgpr";
 669                                 };
 670                         };
 671
 672                         epit1: epit@20d0000 {
 673                                 reg = <0x020d0000 0x4000>;
 674                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 675                         };
 676
 677                         epit2: epit@20d4000 {
 678                                 reg = <0x020d4000 0x4000>;
 679                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 680                         };
 681
 682                         src: src@20d8000 {
 683                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 684                                 reg = <0x020d8000 0x4000>;
 685                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 686                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 687                                 #reset-cells = <1>;
 688                         };
 689
 690                         gpc: gpc@20dc000 {
 691                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 692                                 reg = <0x020dc000 0x4000>;
 693                                 interrupt-controller;
 694                                 #interrupt-cells = <3>;
 695                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 696                                 interrupt-parent = <&intc>;
 697                         };
 698
 699                         iomuxc: iomuxc@20e0000 {
 700                                 compatible = "fsl,imx6ul-iomuxc";
 701                                 reg = <0x020e0000 0x4000>;
 702                         };
 703
 704                         gpr: iomuxc-gpr@20e4000 {
 705                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 706                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 707                                 reg = <0x020e4000 0x4000>;
 708                         };
 709
 710                         gpt2: timer@20e8000 {
 711                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 712                                 reg = <0x020e8000 0x4000>;
 713                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 715                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 716                                 clock-names = "ipg", "per";
 717                         };
 718
 719                         sdma: sdma@20ec000 {
 720                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 721                                              "fsl,imx35-sdma";
 722                                 reg = <0x020ec000 0x4000>;
 723                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 724                                 clocks = <&clks IMX6UL_CLK_IPG>,
 725                                          <&clks IMX6UL_CLK_SDMA>;
 726                                 clock-names = "ipg", "ahb";
 727                                 #dma-cells = <3>;
 728                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 729                         };
 730
 731                         pwm5: pwm@20f0000 {
 732                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 733                                 reg = <0x020f0000 0x4000>;
 734                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 736                                          <&clks IMX6UL_CLK_PWM5>;
 737                                 clock-names = "ipg", "per";
 738                                 #pwm-cells = <2>;
 739                                 status = "disabled";
 740                         };
 741
 742                         pwm6: pwm@20f4000 {
 743                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 744                                 reg = <0x020f4000 0x4000>;
 745                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 746                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 747                                          <&clks IMX6UL_CLK_PWM6>;
 748                                 clock-names = "ipg", "per";
 749                                 #pwm-cells = <2>;
 750                                 status = "disabled";
 751                         };
 752
 753                         pwm7: pwm@20f8000 {
 754                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 755                                 reg = <0x020f8000 0x4000>;
 756                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 758                                          <&clks IMX6UL_CLK_PWM7>;
 759                                 clock-names = "ipg", "per";
 760                                 #pwm-cells = <2>;
 761                                 status = "disabled";
 762                         };
 763
 764                         pwm8: pwm@20fc000 {
 765                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 766                                 reg = <0x020fc000 0x4000>;
 767                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 768                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 769                                          <&clks IMX6UL_CLK_PWM8>;
 770                                 clock-names = "ipg", "per";
 771                                 #pwm-cells = <2>;
 772                                 status = "disabled";
 773                         };
 774                 };
 775
 776                 aips2: aips-bus@2100000 {
 777                         compatible = "fsl,aips-bus", "simple-bus";
 778                         #address-cells = <1>;
 779                         #size-cells = <1>;
 780                         reg = <0x02100000 0x100000>;
 781                         ranges;
 782
 783                         crypto: caam@2140000 {
 784                                 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
 785                                 #address-cells = <1>;
 786                                 #size-cells = <1>;
 787                                 reg = <0x2140000 0x3c000>;
 788                                 ranges = <0 0x2140000 0x3c000>;
 789                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 790                                 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
 791                                          <&clks IMX6UL_CLK_CAAM_MEM>;
 792                                 clock-names = "ipg", "aclk", "mem";
 793
 794                                 sec_jr0: jr0@1000 {
 795                                         compatible = "fsl,sec-v4.0-job-ring";
 796                                         reg = <0x1000 0x1000>;
 797                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 798                                 };
 799
 800                                 sec_jr1: jr1@2000 {
 801                                         compatible = "fsl,sec-v4.0-job-ring";
 802                                         reg = <0x2000 0x1000>;
 803                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 804                                 };
 805
 806                                 sec_jr2: jr2@3000 {
 807                                         compatible = "fsl,sec-v4.0-job-ring";
 808                                         reg = <0x3000 0x1000>;
 809                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 810                                 };
 811                         };
 812
 813                         usbotg1: usb@2184000 {
 814                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 815                                 reg = <0x02184000 0x200>;
 816                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 817                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 818                                 fsl,usbphy = <&usbphy1>;
 819                                 fsl,usbmisc = <&usbmisc 0>;
 820                                 fsl,anatop = <&anatop>;
 821                                 ahb-burst-config = <0x0>;
 822                                 tx-burst-size-dword = <0x10>;
 823                                 rx-burst-size-dword = <0x10>;
 824                                 status = "disabled";
 825                         };
 826
 827                         usbotg2: usb@2184200 {
 828                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 829                                 reg = <0x02184200 0x200>;
 830                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 831                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 832                                 fsl,usbphy = <&usbphy2>;
 833                                 fsl,usbmisc = <&usbmisc 1>;
 834                                 ahb-burst-config = <0x0>;
 835                                 tx-burst-size-dword = <0x10>;
 836                                 rx-burst-size-dword = <0x10>;
 837                                 status = "disabled";
 838                         };
 839
 840                         usbmisc: usbmisc@2184800 {
 841                                 #index-cells = <1>;
 842                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 843                                 reg = <0x02184800 0x200>;
 844                         };
 845
 846                         fec1: ethernet@2188000 {
 847                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 848                                 reg = <0x02188000 0x4000>;
 849                                 interrupt-names = "int0", "pps";
 850                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 851                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&clks IMX6UL_CLK_ENET>,
 853                                          <&clks IMX6UL_CLK_ENET_AHB>,
 854                                          <&clks IMX6UL_CLK_ENET_PTP>,
 855                                          <&clks IMX6UL_CLK_ENET_REF>,
 856                                          <&clks IMX6UL_CLK_ENET_REF>;
 857                                 clock-names = "ipg", "ahb", "ptp",
 858                                               "enet_clk_ref", "enet_out";
 859                                 fsl,num-tx-queues = <1>;
 860                                 fsl,num-rx-queues = <1>;
 861                                 status = "disabled";
 862                         };
 863
 864                         usdhc1: usdhc@2190000 {
 865                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 866                                 reg = <0x02190000 0x4000>;
 867                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 868                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 869                                          <&clks IMX6UL_CLK_USDHC1>,
 870                                          <&clks IMX6UL_CLK_USDHC1>;
 871                                 clock-names = "ipg", "ahb", "per";
 872                                 fsl,tuning-step = <2>;
 873                                 fsl,tuning-start-tap = <20>;
 874                                 bus-width = <4>;
 875                                 status = "disabled";
 876                         };
 877
 878                         usdhc2: usdhc@2194000 {
 879                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 880                                 reg = <0x02194000 0x4000>;
 881                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 882                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 883                                          <&clks IMX6UL_CLK_USDHC2>,
 884                                          <&clks IMX6UL_CLK_USDHC2>;
 885                                 clock-names = "ipg", "ahb", "per";
 886                                 bus-width = <4>;
 887                                 fsl,tuning-step = <2>;
 888                                 fsl,tuning-start-tap = <20>;
 889                                 status = "disabled";
 890                         };
 891
 892                         adc1: adc@2198000 {
 893                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 894                                 reg = <0x02198000 0x4000>;
 895                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 897                                 num-channels = <2>;
 898                                 clock-names = "adc";
 899                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 900                                                          <20000000>;
 901                                 status = "disabled";
 902                         };
 903
 904                         i2c1: i2c@21a0000 {
 905                                 #address-cells = <1>;
 906                                 #size-cells = <0>;
 907                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 908                                 reg = <0x021a0000 0x4000>;
 909                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 910                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 911                                 status = "disabled";
 912                         };
 913
 914                         i2c2: i2c@21a4000 {
 915                                 #address-cells = <1>;
 916                                 #size-cells = <0>;
 917                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 918                                 reg = <0x021a4000 0x4000>;
 919                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 920                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 921                                 status = "disabled";
 922                         };
 923
 924                         i2c3: i2c@21a8000 {
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 928                                 reg = <0x021a8000 0x4000>;
 929                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 930                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 931                                 status = "disabled";
 932                         };
 933
 934                         memory-controller@21b0000 {
 935                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 936                                 reg = <0x021b0000 0x4000>;
 937                                 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
 938                         };
 939
 940                         weim: weim@21b8000 {
 941                                 #address-cells = <2>;
 942                                 #size-cells = <1>;
 943                                 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
 944                                 reg = <0x021b8000 0x4000>;
 945                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 946                                 clocks = <&clks IMX6UL_CLK_EIM>;
 947                                 fsl,weim-cs-gpr = <&gpr>;
 948                                 status = "disabled";
 949                         };
 950
 951                         ocotp: ocotp-ctrl@21bc000 {
 952                                 #address-cells = <1>;
 953                                 #size-cells = <1>;
 954                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 955                                 reg = <0x021bc000 0x4000>;
 956                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 957
 958                                 tempmon_calib: calib@38 {
 959                                         reg = <0x38 4>;
 960                                 };
 961
 962                                 tempmon_temp_grade: temp-grade@20 {
 963                                         reg = <0x20 4>;
 964                                 };
 965
 966                                 cpu_speed_grade: speed-grade@10 {
 967                                         reg = <0x10 4>;
 968                                 };
 969                         };
 970
 971                         csi: csi@21c4000 {
 972                                 compatible = "fsl,imx6ul-csi";
 973                                 reg = <0x021c4000 0x4000>;
 974                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 975                                 clocks = <&clks IMX6UL_CLK_CSI>;
 976                                 clock-names = "mclk";
 977                                 status = "disabled";
 978                         };
 979
 980                         lcdif: lcdif@21c8000 {
 981                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
 982                                 reg = <0x021c8000 0x4000>;
 983                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 984                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 985                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 986                                          <&clks IMX6UL_CLK_DUMMY>;
 987                                 clock-names = "pix", "axi", "disp_axi";
 988                                 status = "disabled";
 989                         };
 990
 991                         pxp: pxp@21cc000 {
 992                                 compatible = "fsl,imx6ul-pxp";
 993                                 reg = <0x021cc000 0x4000>;
 994                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 995                                 clocks = <&clks IMX6UL_CLK_PXP>;
 996                                 clock-names = "axi";
 997                         };
 998
 999                         qspi: spi@21e0000 {
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002                                 compatible = "fsl,imx6ul-qspi";
1003                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1004                                 reg-names = "QuadSPI", "QuadSPI-memory";
1005                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1006                                 clocks = <&clks IMX6UL_CLK_QSPI>,
1007                                          <&clks IMX6UL_CLK_QSPI>;
1008                                 clock-names = "qspi_en", "qspi";
1009                                 status = "disabled";
1010                         };
1011
1012                         wdog3: wdog@21e4000 {
1013                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1014                                 reg = <0x021e4000 0x4000>;
1015                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1016                                 clocks = <&clks IMX6UL_CLK_WDOG3>;
1017                                 status = "disabled";
1018                         };
1019
1020                         uart2: serial@21e8000 {
1021                                 compatible = "fsl,imx6ul-uart",
1022                                              "fsl,imx6q-uart";
1023                                 reg = <0x021e8000 0x4000>;
1024                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1025                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1026                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
1027                                 clock-names = "ipg", "per";
1028                                 status = "disabled";
1029                         };
1030
1031                         uart3: serial@21ec000 {
1032                                 compatible = "fsl,imx6ul-uart",
1033                                              "fsl,imx6q-uart";
1034                                 reg = <0x021ec000 0x4000>;
1035                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1036                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1037                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
1038                                 clock-names = "ipg", "per";
1039                                 status = "disabled";
1040                         };
1041
1042                         uart4: serial@21f0000 {
1043                                 compatible = "fsl,imx6ul-uart",
1044                                              "fsl,imx6q-uart";
1045                                 reg = <0x021f0000 0x4000>;
1046                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1047                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1048                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
1049                                 clock-names = "ipg", "per";
1050                                 status = "disabled";
1051                         };
1052
1053                         uart5: serial@21f4000 {
1054                                 compatible = "fsl,imx6ul-uart",
1055                                              "fsl,imx6q-uart";
1056                                 reg = <0x021f4000 0x4000>;
1057                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1058                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1059                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1060                                 clock-names = "ipg", "per";
1061                                 status = "disabled";
1062                         };
1063
1064                         i2c4: i2c@21f8000 {
1065                                 #address-cells = <1>;
1066                                 #size-cells = <0>;
1067                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1068                                 reg = <0x021f8000 0x4000>;
1069                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1070                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1071                                 status = "disabled";
1072                         };
1073
1074                         uart6: serial@21fc000 {
1075                                 compatible = "fsl,imx6ul-uart",
1076                                              "fsl,imx6q-uart";
1077                                 reg = <0x021fc000 0x4000>;
1078                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1079                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1080                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1081                                 clock-names = "ipg", "per";
1082                                 status = "disabled";
1083                         };
1084                 };
1085         };
1086 };