2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/gpio/gpio.h>
43 #include <dt-bindings/interrupt-controller/irq.h>
44 #include <dt-bindings/pwm/pwm.h>
56 lcdif-23bit-pins-a = &pinctrl_disp0_1;
57 lcdif-24bit-pins-a = &pinctrl_disp0_2;
59 reg-can-xcvr = ®_can_xcvr;
74 device_type = "memory";
75 reg = <0x80000000 0>; /* will be filled by U-Boot */
80 compatible = "fixed-clock";
82 clock-frequency = <26000000>;
86 backlight: backlight {
87 compatible = "pwm-backlight";
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_lcd_rst>;
90 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
91 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
92 power-supply = <®_lcd_pwr>;
94 * a poor man's way to create a 1:1 relationship between
95 * the PWM value and the actual duty cycle
97 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
98 10 11 12 13 14 15 16 17 18 19
99 20 21 22 23 24 25 26 27 28 29
100 30 31 32 33 34 35 36 37 38 39
101 40 41 42 43 44 45 46 47 48 49
102 50 51 52 53 54 55 56 57 58 59
103 60 61 62 63 64 65 66 67 68 69
104 70 71 72 73 74 75 76 77 78 79
105 80 81 82 83 84 85 86 87 88 89
106 90 91 92 93 94 95 96 97 98 99
108 default-brightness-level = <50>;
112 compatible = "i2c-gpio";
113 #address-cells = <1>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c_gpio>;
118 &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
119 &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
121 clock-frequency = <400000>;
125 compatible = "dallas,ds1339";
132 compatible = "gpio-leds";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_led>;
138 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
139 linux,default-trigger = "heartbeat";
143 reg_3v3_etn: regulator-3v3etn {
144 compatible = "regulator-fixed";
145 regulator-name = "3V3_ETN";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_etnphy_power>;
150 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
154 reg_2v5: regulator-2v5 {
155 compatible = "regulator-fixed";
156 regulator-name = "2V5";
157 regulator-min-microvolt = <2500000>;
158 regulator-max-microvolt = <2500000>;
162 reg_3v3: regulator-3v3 {
163 compatible = "regulator-fixed";
164 regulator-name = "3V3";
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
170 reg_can_xcvr: regulator-canxcvr {
171 compatible = "regulator-fixed";
172 regulator-name = "CAN XCVR";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
177 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
180 reg_lcd_pwr: regulator-lcdpwr {
181 compatible = "regulator-fixed";
182 regulator-name = "LCD POWER";
183 regulator-min-microvolt = <3300000>;
184 regulator-max-microvolt = <3300000>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_lcd_pwr>;
187 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
193 reg_usbh1_vbus: regulator-usbh1vbus {
194 compatible = "regulator-fixed";
195 regulator-name = "usbh1_vbus";
196 regulator-min-microvolt = <5000000>;
197 regulator-max-microvolt = <5000000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
200 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
204 reg_usbotg_vbus: regulator-usbotgvbus {
205 compatible = "regulator-fixed";
206 regulator-name = "usbotg_vbus";
207 regulator-min-microvolt = <5000000>;
208 regulator-max-microvolt = <5000000>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
211 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
216 #address-cells = <1>;
218 compatible = "spi-gpio";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_spi_gpio>;
221 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
222 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
223 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
224 num-chipselects = <2>;
226 &gpio1 29 GPIO_ACTIVE_HIGH
227 &gpio1 10 GPIO_ACTIVE_HIGH
233 compatible = "karo,imx6ul-tx6ul-sgtl5000",
235 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
236 simple-audio-card,format = "i2s";
237 simple-audio-card,bitclock-master = <&codec_dai>;
238 simple-audio-card,frame-master = <&codec_dai>;
239 simple-audio-card,widgets =
240 "Microphone", "Mic Jack",
243 "Headphone", "Headphone Jack";
244 simple-audio-card,routing =
245 "MIC_IN", "Mic Jack",
246 "Mic Jack", "Mic Bias",
247 "Headphone Jack", "HP_OUT";
249 cpu_dai: simple-audio-card,cpu {
253 codec_dai: simple-audio-card,codec {
254 sound-dai = <&sgtl5000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_flexcan1>;
262 xceiver-supply = <®_can_xcvr>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_flexcan2>;
269 xceiver-supply = <®_can_xcvr>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_ecspi2>;
277 &gpio1 29 GPIO_ACTIVE_HIGH
278 &gpio1 10 GPIO_ACTIVE_HIGH
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
287 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
288 phy-supply = <®_3v3_etn>;
289 phy-handle = <&etnphy0>;
293 #address-cells = <1>;
296 etnphy0: ethernet-phy@0 {
297 compatible = "ethernet-phy-ieee802.3-c22";
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_etnphy0_int>;
301 interrupt-parent = <&gpio5>;
302 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
306 etnphy1: ethernet-phy@2 {
307 compatible = "ethernet-phy-ieee802.3-c22";
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_etnphy1_int>;
311 interrupt-parent = <&gpio4>;
312 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
322 phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
323 phy-supply = <®_3v3_etn>;
324 phy-handle = <&etnphy1>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_gpmi_nand>;
332 fsl,no-blockmark-swap;
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_i2c2>;
339 clock-frequency = <400000>;
343 compatible = "fsl,sgtl5000";
345 #sound-dai-cells = <0>;
346 VDDA-supply = <®_2v5>;
347 VDDIO-supply = <®_3v3>;
351 polytouch: polytouch@38 {
352 compatible = "edt,edt-ft5x06";
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_edt_ft5x06>;
356 interrupt-parent = <&gpio5>;
357 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
358 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
359 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
363 touchscreen: touchscreen@48 {
364 compatible = "ti,tsc2007";
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_tsc2007>;
368 interrupt-parent = <&gpio3>;
369 interrupts = <26 IRQ_TYPE_NONE>;
370 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
371 ti,x-plate-ohms = <660>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_kpp>;
380 /* row/col 0..3 are mapped to KPP row/col 4..7 */
382 MATRIX_KEY(4, 4, KEY_POWER)
383 MATRIX_KEY(4, 5, KEY_KP0)
384 MATRIX_KEY(4, 6, KEY_KP1)
385 MATRIX_KEY(4, 7, KEY_KP2)
386 MATRIX_KEY(5, 4, KEY_KP3)
387 MATRIX_KEY(5, 5, KEY_KP4)
388 MATRIX_KEY(5, 6, KEY_KP5)
389 MATRIX_KEY(5, 7, KEY_KP6)
390 MATRIX_KEY(6, 4, KEY_KP7)
391 MATRIX_KEY(6, 5, KEY_KP8)
392 MATRIX_KEY(6, 6, KEY_KP9)
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_disp0_1>;
400 lcd-supply = <®_lcd_pwr>;
401 display = <&display>;
405 bits-per-pixel = <32>;
411 clock-frequency = <25200000>;
423 pixelclk-active = <1>;
427 clock-frequency = <25200000>;
439 pixelclk-active = <1>;
443 clock-frequency = <6413760>;
455 pixelclk-active = <1>;
459 clock-frequency = <9009000>;
471 pixelclk-active = <0>;
475 clock-frequency = <33264000>;
487 pixelclk-active = <1>;
490 ET0700 { /* same as ET0500 */
491 clock-frequency = <33264000>;
503 pixelclk-active = <1>;
507 clock-frequency = <6596040>;
519 pixelclk-active = <1>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_pwm5>;
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_sai2>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
559 vbus-supply = <®_usbotg_vbus>;
560 dr_mode = "peripheral";
561 disable-over-current;
566 vbus-supply = <®_usbh1_vbus>;
568 disable-over-current;
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
577 cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_hog>;
586 pinctrl_hog: hoggrp {
589 pinctrl_led: ledgrp {
591 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
595 pinctrl_disp0_1: disp0grp-1 {
597 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
598 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
599 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
600 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
601 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
602 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
603 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
604 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
605 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
606 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
607 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
608 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
609 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
610 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
611 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
612 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
613 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
614 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
615 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
616 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
617 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
618 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
619 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
620 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
621 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
622 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
623 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
624 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
628 pinctrl_disp0_2: disp0grp-2 {
630 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
631 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
632 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
633 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
634 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10
635 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
636 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
637 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
638 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
639 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
640 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
641 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
642 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
643 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
644 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
645 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
646 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
647 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
648 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
649 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
650 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
651 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
652 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
653 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
654 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
655 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
656 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
657 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
661 pinctrl_ecspi2: ecspi2grp {
663 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
664 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
665 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */
666 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */
667 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */
671 pinctrl_edt_ft5x06: edt-ft5x06grp {
673 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */
674 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */
675 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */
679 pinctrl_enet1: enet1grp {
681 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
682 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
683 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0
684 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0
685 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0
686 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
687 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
688 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
692 pinctrl_enet2: enet2grp {
694 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
695 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
696 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0
697 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0
698 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0
699 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
700 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
701 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1
705 pinctrl_enet1_mdio: enet1-mdiogrp {
707 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0
708 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
712 pinctrl_etnphy_power: etnphy-pwrgrp {
714 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
718 pinctrl_etnphy0_int: etnphy-intgrp-0 {
720 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
724 pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
726 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
730 pinctrl_etnphy1_int: etnphy-intgrp-1 {
732 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
736 pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
738 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
742 pinctrl_flexcan1: flexcan1grp {
744 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
745 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
749 pinctrl_flexcan2: flexcan2grp {
751 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
752 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
756 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
758 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */
762 pinctrl_gpmi_nand: gpminandgrp {
764 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
765 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
766 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
767 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
768 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
769 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
770 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
771 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
772 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
773 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
774 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
775 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
776 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
777 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
778 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
782 pinctrl_i2c_gpio: i2c-gpiogrp {
784 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */
785 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */
789 pinctrl_i2c2: i2c2grp {
791 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1
792 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1
796 pinctrl_kpp: kppgrp {
798 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0
799 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0
800 MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0
801 MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0
802 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0
803 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0
804 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0
805 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0
809 pinctrl_lcd_pwr: lcd-pwrgrp {
811 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */
815 pinctrl_lcd_rst: lcd-rstgrp {
817 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
821 pinctrl_pwm5: pwm5grp {
823 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0
827 pinctrl_sai2: sai2grp {
829 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */
830 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */
831 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */
832 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */
836 pinctrl_spi_gpio: spi-gpiogrp {
838 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
839 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
840 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */
841 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */
842 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */
846 pinctrl_tsc2007: tsc2007grp {
848 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */
852 pinctrl_uart1: uart1grp {
854 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0
855 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0
859 pinctrl_uart1_rtscts: uart1-rtsctsgrp {
861 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0
862 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0
866 pinctrl_uart2: uart2grp {
868 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0
869 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0
873 pinctrl_uart2_rtscts: uart2-rtsctsgrp {
875 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0
876 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0
880 pinctrl_uart5: uart5grp {
882 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0
883 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0
887 pinctrl_uart5_rtscts: uart5-rtsctsgrp {
889 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0
890 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0
894 pinctrl_usbh1_oc: usbh1-ocgrp {
896 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */
900 pinctrl_usbh1_vbus: usbh1-vbusgrp {
902 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */
906 pinctrl_usbotg_oc: usbotg-ocgrp {
908 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */
912 pinctrl_usbotg_vbus: usbotg-vbusgrp {
914 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */
918 pinctrl_usdhc1: usdhc1grp {
920 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
921 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
922 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
923 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
924 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
925 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
929 pinctrl_usdhc1_cd: usdhc1cdgrp {
931 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */
935 pinctrl_usdhc2: usdhc2grp {
937 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1
938 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1
939 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1
940 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1
941 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1
942 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1
944 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0