2 * Copyright 2015 Technexion Ltd.
4 * Author: Wig Cheng <wig.cheng@technexion.com>
5 * Richard Hu <richard.hu@technexion.com>
6 * Tapani Utriainen <tapani@technexion.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * version 2 as published by the Free Software Foundation.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "imx6ul.dtsi"
51 model = "Technexion Pico i.MX6UL Board";
52 compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
54 /* Will be filled by the bootloader */
56 device_type = "memory";
65 compatible = "pwm-backlight";
66 pwms = <&pwm3 0 5000000>;
67 brightness-levels = <0 4 8 16 32 64 128 255>;
68 default-brightness-level = <6>;
72 reg_2p5v: regulator-2p5v {
73 compatible = "regulator-fixed";
74 regulator-name = "2P5V";
75 regulator-min-microvolt = <2500000>;
76 regulator-max-microvolt = <2500000>;
79 reg_3p3v: regulator-3p3v {
80 compatible = "regulator-fixed";
81 regulator-name = "3P3V";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
86 reg_sd1_vmmc: regulator-sd1-vmmc {
87 compatible = "regulator-fixed";
88 regulator-name = "VSD_3V3";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
95 reg_usb_otg_vbus: regulator-usb-otg-vbus {
96 compatible = "regulator-fixed";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_usb_otg1>;
99 regulator-name = "usb_otg_vbus";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
105 reg_brcm: regulator-brcm {
106 compatible = "regulator-fixed";
108 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_brcm_reg>;
111 regulator-name = "brcm_reg";
112 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>;
114 startup-delay-us = <200000>;
118 compatible = "fsl,imx-audio-sgtl5000";
119 model = "imx6ul-sgtl5000";
121 audio-codec = <&codec>;
123 "LINE_IN", "Line In Jack",
124 "MIC_IN", "Mic Jack",
125 "Mic Jack", "Mic Bias",
126 "Headphone Jack", "HP_OUT";
129 sys_mclk: clock-sys-mclk {
130 compatible = "fixed-clock";
132 clock-frequency = <24576000>;
136 compatible = "gpio-leds";
140 gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_flexcan1>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_flexcan2>;
158 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
159 assigned-clock-rates = <786432000>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_enet2>;
166 phy-handle = <ðphy1>;
168 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
169 phy-reset-duration = <1>;
172 #address-cells = <1>;
175 ethphy1: ethernet-phy@1 {
176 compatible = "ethernet-phy-ieee802.3-c22";
179 interrupt-parent = <&gpio5>;
180 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
186 clock-frequency = <100000>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_i2c1>;
192 compatible = "fsl,pfuze3000";
198 regulator-min-microvolt = <700000>;
199 regulator-max-microvolt = <1475000>;
202 regulator-ramp-delay = <6250>;
207 regulator-min-microvolt = <900000>;
208 regulator-max-microvolt = <1650000>;
223 clock_frequency = <100000>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_i2c2>;
230 compatible = "fsl,sgtl5000";
231 clocks = <&sys_mclk>;
232 VDDA-supply = <®_2p5v>;
233 VDDIO-supply = <®_3p3v>;
238 clock_frequency = <100000>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_i2c3>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
247 display = <&display0>;
251 bits-per-pixel = <32>;
255 native-mode = <&timing0>;
258 clock-frequency = <33200000>;
261 hfront-porch = <210>;
270 pixelclk-active = <0>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_pwm3>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_pwm7>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_pwm8>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_sai1>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_uart3>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_uart6>;
314 vbus-supply = <®_usb_otg_vbus>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_usb_otg1_id>;
318 disable-over-current;
324 disable-over-current;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_usdhc1>;
334 keep-power-in-suspend;
338 &usdhc2 { /* Wifi SDIO */
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_usdhc2>;
343 keep-power-in-suspend;
345 vmmc-supply = <®_brcm>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_wdog>;
352 fsl,ext-reset-output;
356 pinctrl_brcm_reg: brcmreggrp {
358 MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
359 MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
363 pinctrl_enet2: enet2grp {
365 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
366 MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
367 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
368 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
369 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
370 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
371 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
372 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
373 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
374 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
375 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
376 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
380 pinctrl_flexcan1: flexcan1grp {
382 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
383 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
387 pinctrl_flexcan2: flexcan2grp {
389 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
390 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
394 pinctrl_i2c1: i2c1grp {
396 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
397 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
401 pinctrl_i2c2: i2c2grp {
403 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
404 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
408 pinctrl_i2c3: i2c3grp {
410 MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
411 MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
415 pinctrl_lcdif_dat: lcdifdatgrp {
417 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
418 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
419 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
420 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
421 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
422 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
423 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
424 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
425 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
426 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
427 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
428 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
429 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
430 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
431 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
432 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
433 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
434 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
435 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
436 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
437 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
438 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
439 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
440 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
444 pinctrl_lcdif_ctrl: lcdifctrlgrp {
446 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
447 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
448 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
449 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
451 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
455 pinctrl_pwm3: pwm3grp {
457 MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
461 pinctrl_pwm7: pwm7grp {
463 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
467 pinctrl_pwm8: pwm8grp {
469 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
473 pinctrl_sai1: sai1grp {
475 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
476 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
477 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
478 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
482 pinctrl_uart3: uart3grp {
484 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
485 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
486 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
487 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
491 pinctrl_uart5: uart5grp {
493 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
494 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
495 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
496 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
500 pinctrl_uart6: uart6grp {
502 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
503 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
507 pinctrl_usb_otg1: usbotg1grp {
509 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
513 pinctrl_usb_otg1_id: usbotg1idgrp {
515 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
519 pinctrl_usdhc1: usdhc1grp {
521 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
522 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
523 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
524 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
525 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
526 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
527 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
528 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
529 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
530 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
531 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
535 pinctrl_usdhc2: usdhc2grp {
537 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
538 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
539 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
540 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
541 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
542 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
546 pinctrl_wdog: wdoggrp {
548 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0