2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/gpio/gpio.h>
46 #include <dt-bindings/input/input.h>
47 #include "imx6ul.dtsi"
50 model = "Engicam GEAM6UL Starter Kit";
51 compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
54 device_type = "memory";
55 reg = <0x80000000 0x08000000>;
59 compatible = "pwm-backlight";
60 pwms = <&pwm8 0 100000>;
61 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
62 10 11 12 13 14 15 16 17 18 19
63 20 21 22 23 24 25 26 27 28 29
64 30 31 32 33 34 35 36 37 38 39
65 40 41 42 43 44 45 46 47 48 49
66 50 51 52 53 54 55 56 57 58 59
67 60 61 62 63 64 65 66 67 68 69
68 70 71 72 73 74 75 76 77 78 79
69 80 81 82 83 84 85 86 87 88 89
70 90 91 92 93 94 95 96 97 98 99
72 default-brightness-level = <100>;
79 reg_1p8v: regulator-1p8v {
80 compatible = "regulator-fixed";
81 regulator-name = "1P8V";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
88 reg_3p3v: regulator-3p3v {
89 compatible = "regulator-fixed";
90 regulator-name = "3P3V";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
98 compatible = "simple-audio-card";
99 simple-audio-card,name = "imx6ul-geam-sgtl5000";
100 simple-audio-card,format = "i2s";
101 simple-audio-card,bitclock-master = <&dailink_master>;
102 simple-audio-card,frame-master = <&dailink_master>;
103 simple-audio-card,widgets =
104 "Microphone", "Mic Jack",
107 "Headphone", "Headphone Jack";
108 simple-audio-card,routing =
109 "MIC_IN", "Mic Jack",
110 "Mic Jack", "Mic Bias",
111 "Headphone Jack", "HP_OUT";
113 simple-audio-card,cpu {
117 dailink_master: simple-audio-card,codec {
118 sound-dai = <&sgtl5000>;
119 clocks = <&clks IMX6UL_CLK_SAI2>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_flexcan1>;
127 xceiver-supply = <®_3p3v>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_flexcan2>;
134 xceiver-supply = <®_3p3v>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_enet1>;
142 phy-handle = <ðphy0>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_enet2>;
150 phy-handle = <ðphy1>;
154 #address-cells = <1>;
157 ethphy0: ethernet-phy@0 {
158 compatible = "ethernet-phy-ieee802.3-c22";
162 ethphy1: ethernet-phy@1 {
163 compatible = "ethernet-phy-ieee802.3-c22";
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_gpmi_nand>;
177 clock-frequency = <100000>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c1>;
183 compatible = "fsl,sgtl5000";
185 #sound-dai-cells = <0>;
186 clocks = <&clks IMX6UL_CLK_OSC>;
187 clock-names = "mclk";
188 VDDA-supply = <®_3p3v>;
189 VDDIO-supply = <®_3p3v>;
190 VDDD-supply = <®_1p8v>;
195 clock_frequency = <100000>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c2>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_lcdif_dat
204 &pinctrl_lcdif_ctrl>;
205 display = <&display0>;
209 bits-per-pixel = <16>;
213 native-mode = <&timing0>;
215 clock-frequency = <28000000>;
227 pixelclk-active = <0>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_pwm8>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_tsc>;
242 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_sai2>;
252 measure-delay-time = <0x1ffff>;
253 pre-charge-time = <0x1fff>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_uart1>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_uart2>;
270 dr_mode = "peripheral";
280 pinctrl-names = "default", "state_100mhz", "state_200mhz";
281 pinctrl-0 = <&pinctrl_usdhc1>;
282 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
283 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
285 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
291 pinctrl_enet1: enet1grp {
293 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
294 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
295 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
296 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
297 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
298 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
299 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
303 pinctrl_enet2: enet2grp {
305 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
306 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
307 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
308 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
309 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
310 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
311 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
312 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
313 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
314 MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
318 pinctrl_flexcan1: flexcan1grp {
320 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
321 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
325 pinctrl_flexcan2: flexcan2grp {
327 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
328 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
332 pinctrl_gpmi_nand: gpmi-nand {
334 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
335 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
336 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
337 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
338 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
339 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
340 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
341 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
342 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
343 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
344 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
345 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
346 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
347 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
348 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
352 pinctrl_i2c1: i2c1grp {
354 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
355 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
359 pinctrl_i2c2: i2c2grp {
361 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
362 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
366 pinctrl_lcdif_ctrl: lcdifctrlgrp {
368 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
369 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
370 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
371 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
375 pinctrl_lcdif_dat: lcdifdatgrp {
377 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
378 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
379 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
380 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
381 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
382 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
383 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
384 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
385 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
386 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
387 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
388 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
389 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
390 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
391 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
392 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
393 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
394 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
398 pinctrl_pwm8: pwm8grp {
400 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
404 pinctrl_tsc: tscgrp {
406 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
407 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
408 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
409 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
413 pinctrl_sai2: sai2grp {
415 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
416 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
417 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
418 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
419 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
423 pinctrl_uart1: uart1grp {
425 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
426 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
430 pinctrl_uart2: uart2grp {
432 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
433 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
434 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
435 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
439 pinctrl_usdhc1: usdhc1grp {
441 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
442 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
443 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
444 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
445 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
446 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
450 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
452 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
453 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
454 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
455 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
456 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
457 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
461 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
463 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
464 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
465 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
466 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
467 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
468 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
472 pinctrl_usdhc2: usdhc2grp {
474 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
475 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
476 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
477 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
478 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
479 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070