arch/arm/boot/dts/imx6ul-14x14-evk.dtsi

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart1;
  12         };
  13
  14         memory@80000000 {
  15                 device_type = "memory";
  16                 reg = <0x80000000 0x20000000>;
  17         };
  18
  19         backlight_display: backlight-display {
  20                 compatible = "pwm-backlight";
  21                 pwms = <&pwm1 0 5000000>;
  22                 brightness-levels = <0 4 8 16 32 64 128 255>;
  23                 default-brightness-level = <6>;
  24                 status = "okay";
  25         };
  26
  27
  28         reg_sd1_vmmc: regulator-sd1-vmmc {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "VSD_3V3";
  31                 regulator-min-microvolt = <3300000>;
  32                 regulator-max-microvolt = <3300000>;
  33                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  34                 enable-active-high;
  35         };
  36
  37         sound {
  38                 compatible = "simple-audio-card";
  39                 simple-audio-card,name = "mx6ul-wm8960";
  40                 simple-audio-card,format = "i2s";
  41                 simple-audio-card,bitclock-master = <&dailink_master>;
  42                 simple-audio-card,frame-master = <&dailink_master>;
  43                 simple-audio-card,widgets =
  44                         "Microphone", "Mic Jack",
  45                         "Line", "Line In",
  46                         "Line", "Line Out",
  47                         "Speaker", "Speaker",
  48                         "Headphone", "Headphone Jack";
  49                 simple-audio-card,routing =
  50                         "Headphone Jack", "HP_L",
  51                         "Headphone Jack", "HP_R",
  52                         "Speaker", "SPK_LP",
  53                         "Speaker", "SPK_LN",
  54                         "Speaker", "SPK_RP",
  55                         "Speaker", "SPK_RN",
  56                         "LINPUT1", "Mic Jack",
  57                         "LINPUT3", "Mic Jack",
  58                         "RINPUT1", "Mic Jack",
  59                         "RINPUT2", "Mic Jack";
  60
  61                 simple-audio-card,cpu {
  62                         sound-dai = <&sai2>;
  63                 };
  64
  65                 dailink_master: simple-audio-card,codec {
  66                         sound-dai = <&codec>;
  67                         clocks = <&clks IMX6UL_CLK_SAI2>;
  68                 };
  69         };
  70
  71         panel {
  72                 compatible = "innolux,at043tn24";
  73                 backlight = <&backlight_display>;
  74
  75                 port {
  76                         panel_in: endpoint {
  77                                 remote-endpoint = <&display_out>;
  78                         };
  79                 };
  80         };
  81 };
  82
  83 &clks {
  84         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  85         assigned-clock-rates = <786432000>;
  86 };
  87
  88 &i2c2 {
  89         clock_frequency = <100000>;
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_i2c2>;
  92         status = "okay";
  93
  94         codec: wm8960@1a {
  95                 #sound-dai-cells = <0>;
  96                 compatible = "wlf,wm8960";
  97                 reg = <0x1a>;
  98                 wlf,shared-lrclk;
  99         };
 100 };
 101
 102 &fec1 {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_enet1>;
 105         phy-mode = "rmii";
 106         phy-handle = <&ethphy0>;
 107         status = "okay";
 108 };
 109
 110 &fec2 {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_enet2>;
 113         phy-mode = "rmii";
 114         phy-handle = <&ethphy1>;
 115         status = "okay";
 116
 117         mdio {
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120
 121                 ethphy0: ethernet-phy@2 {
 122                         reg = <2>;
 123                         micrel,led-mode = <1>;
 124                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
 125                         clock-names = "rmii-ref";
 126                 };
 127
 128                 ethphy1: ethernet-phy@1 {
 129                         reg = <1>;
 130                         micrel,led-mode = <1>;
 131                         clocks = <&clks IMX6UL_CLK_ENET2_REF>;
 132                         clock-names = "rmii-ref";
 133                 };
 134         };
 135 };
 136
 137 &i2c1 {
 138         clock-frequency = <100000>;
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_i2c1>;
 141         status = "okay";
 142
 143         mag3110@e {
 144                 compatible = "fsl,mag3110";
 145                 reg = <0x0e>;
 146         };
 147 };
 148
 149 &lcdif {
 150         assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
 151         assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_lcdif_dat
 154                      &pinctrl_lcdif_ctrl>;
 155         status = "okay";
 156
 157         port {
 158                 display_out: endpoint {
 159                         remote-endpoint = <&panel_in>;
 160                 };
 161         };
 162 };
 163
 164 &pwm1 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_pwm1>;
 167         status = "okay";
 168 };
 169
 170 &qspi {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_qspi>;
 173         status = "okay";
 174
 175         flash0: n25q256a@0 {
 176                 #address-cells = <1>;
 177                 #size-cells = <1>;
 178                 compatible = "micron,n25q256a", "jedec,spi-nor";
 179                 spi-max-frequency = <29000000>;
 180                 reg = <0>;
 181         };
 182 };
 183
 184 &sai2 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_sai2>;
 187         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 188                           <&clks IMX6UL_CLK_SAI2>;
 189         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 190         assigned-clock-rates = <0>, <12288000>;
 191         fsl,sai-mclk-direction-output;
 192         status = "okay";
 193 };
 194
 195 &snvs_poweroff {
 196         status = "okay";
 197 };
 198
 199 &tsc {
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_tsc>;
 202         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 203         measure-delay-time = <0xffff>;
 204         pre-charge-time = <0xfff>;
 205         status = "okay";
 206 };
 207
 208 &uart1 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_uart1>;
 211         status = "okay";
 212 };
 213
 214 &uart2 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_uart2>;
 217         uart-has-rtscts;
 218         status = "okay";
 219 };
 220
 221 &usbotg1 {
 222         dr_mode = "otg";
 223         status = "okay";
 224 };
 225
 226 &usbotg2 {
 227         dr_mode = "host";
 228         disable-over-current;
 229         status = "okay";
 230 };
 231
 232 &usbphy1 {
 233         fsl,tx-d-cal = <106>;
 234 };
 235
 236 &usbphy2 {
 237         fsl,tx-d-cal = <106>;
 238 };
 239
 240 &usdhc1 {
 241         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 242         pinctrl-0 = <&pinctrl_usdhc1>;
 243         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 244         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 245         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 246         keep-power-in-suspend;
 247         wakeup-source;
 248         vmmc-supply = <&reg_sd1_vmmc>;
 249         status = "okay";
 250 };
 251
 252 &usdhc2 {
 253         pinctrl-names = "default";
 254         pinctrl-0 = <&pinctrl_usdhc2>;
 255         no-1-8-v;
 256         keep-power-in-suspend;
 257         wakeup-source;
 258         status = "okay";
 259 };
 260
 261 &wdog1 {
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&pinctrl_wdog>;
 264         fsl,ext-reset-output;
 265 };
 266
 267 &iomuxc {
 268         pinctrl-names = "default";
 269
 270         pinctrl_csi1: csi1grp {
 271                 fsl,pins = <
 272                         MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 273                         MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 274                         MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 275                         MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 276                         MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 277                         MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 278                         MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 279                         MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 280                         MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 281                         MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 282                         MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 283                         MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 284                 >;
 285         };
 286
 287         pinctrl_enet1: enet1grp {
 288                 fsl,pins = <
 289                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 290                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 291                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 292                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 293                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 294                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 295                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 296                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 297                 >;
 298         };
 299
 300         pinctrl_enet2: enet2grp {
 301                 fsl,pins = <
 302                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 303                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 304                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 305                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 306                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 307                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 308                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 309                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 310                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 311                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 312                 >;
 313         };
 314
 315         pinctrl_flexcan1: flexcan1grp{
 316                 fsl,pins = <
 317                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 318                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 319                 >;
 320         };
 321
 322         pinctrl_flexcan2: flexcan2grp{
 323                 fsl,pins = <
 324                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 325                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 326                 >;
 327         };
 328
 329         pinctrl_i2c1: i2c1grp {
 330                 fsl,pins = <
 331                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 332                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 333                 >;
 334         };
 335
 336         pinctrl_i2c2: i2c2grp {
 337                 fsl,pins = <
 338                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 339                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 340                 >;
 341         };
 342
 343         pinctrl_lcdif_dat: lcdifdatgrp {
 344                 fsl,pins = <
 345                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 346                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 347                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 348                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 349                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 350                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 351                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 352                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 353                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 354                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 355                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 356                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 357                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 358                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 359                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 360                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 361                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 362                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 363                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 364                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 365                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 366                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 367                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 368                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 369                 >;
 370         };
 371
 372         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 373                 fsl,pins = <
 374                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 375                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 376                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 377                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 378                         /* used for lcd reset */
 379                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 380                 >;
 381         };
 382
 383         pinctrl_qspi: qspigrp {
 384                 fsl,pins = <
 385                         MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
 386                         MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
 387                         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
 388                         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
 389                         MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
 390                         MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
 391                 >;
 392         };
 393
 394         pinctrl_sai2: sai2grp {
 395                 fsl,pins = <
 396                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 397                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 398                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 399                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 400                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 401                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
 402                 >;
 403         };
 404
 405         pinctrl_pwm1: pwm1grp {
 406                 fsl,pins = <
 407                         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 408                 >;
 409         };
 410
 411         pinctrl_sim2: sim2grp {
 412                 fsl,pins = <
 413                         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
 414                         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
 415                         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
 416                         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
 417                         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
 418                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
 419                 >;
 420         };
 421
 422         pinctrl_tsc: tscgrp {
 423                 fsl,pins = <
 424                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
 425                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
 426                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
 427                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
 428                 >;
 429         };
 430
 431         pinctrl_uart1: uart1grp {
 432                 fsl,pins = <
 433                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 434                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 435                 >;
 436         };
 437
 438         pinctrl_uart2: uart2grp {
 439                 fsl,pins = <
 440                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 441                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 442                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 443                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 444                 >;
 445         };
 446
 447         pinctrl_usdhc1: usdhc1grp {
 448                 fsl,pins = <
 449                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 450                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 451                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 452                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 453                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 454                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 455                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 456                         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 457                         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 458                 >;
 459         };
 460
 461         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 462                 fsl,pins = <
 463                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 464                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 465                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 466                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 467                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 468                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 469
 470                 >;
 471         };
 472
 473         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 474                 fsl,pins = <
 475                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 476                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 477                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 478                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 479                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 480                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 481                 >;
 482         };
 483
 484         pinctrl_usdhc2: usdhc2grp {
 485                 fsl,pins = <
 486                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 487                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 488                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 489                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 490                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 491                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 492                 >;
 493         };
 494
 495         pinctrl_wdog: wdoggrp {
 496                 fsl,pins = <
 497                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 498                 >;
 499         };
 500 };