arch/arm/boot/dts/imx6sx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2014 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6sx-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6sx-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          */
  19         chosen {};
  20
  21         aliases {
  22                 can0 = &flexcan1;
  23                 can1 = &flexcan2;
  24                 ethernet0 = &fec1;
  25                 ethernet1 = &fec2;
  26                 gpio0 = &gpio1;
  27                 gpio1 = &gpio2;
  28                 gpio2 = &gpio3;
  29                 gpio3 = &gpio4;
  30                 gpio4 = &gpio5;
  31                 gpio5 = &gpio6;
  32                 gpio6 = &gpio7;
  33                 i2c0 = &i2c1;
  34                 i2c1 = &i2c2;
  35                 i2c2 = &i2c3;
  36                 i2c3 = &i2c4;
  37                 mmc0 = &usdhc1;
  38                 mmc1 = &usdhc2;
  39                 mmc2 = &usdhc3;
  40                 mmc3 = &usdhc4;
  41                 serial0 = &uart1;
  42                 serial1 = &uart2;
  43                 serial2 = &uart3;
  44                 serial3 = &uart4;
  45                 serial4 = &uart5;
  46                 serial5 = &uart6;
  47                 spi0 = &ecspi1;
  48                 spi1 = &ecspi2;
  49                 spi2 = &ecspi3;
  50                 spi3 = &ecspi4;
  51                 spi4 = &ecspi5;
  52                 usbphy0 = &usbphy1;
  53                 usbphy1 = &usbphy2;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@0 {
  61                         compatible = "arm,cortex-a9";
  62                         device_type = "cpu";
  63                         reg = <0>;
  64                         next-level-cache = <&L2>;
  65                         operating-points = <
  66                                 /* kHz    uV */
  67                                 996000  1250000
  68                                 792000  1175000
  69                                 396000  1075000
  70                                 198000  975000
  71                         >;
  72                         fsl,soc-operating-points = <
  73                                 /* ARM kHz  SOC uV */
  74                                 996000      1175000
  75                                 792000      1175000
  76                                 396000      1175000
  77                                 198000      1175000
  78                         >;
  79                         clock-latency = <61036>; /* two CLK32 periods */
  80                         #cooling-cells = <2>;
  81                         clocks = <&clks IMX6SX_CLK_ARM>,
  82                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  83                                  <&clks IMX6SX_CLK_STEP>,
  84                                  <&clks IMX6SX_CLK_PLL1_SW>,
  85                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  86                         clock-names = "arm", "pll2_pfd2_396m", "step",
  87                                       "pll1_sw", "pll1_sys";
  88                         arm-supply = <&reg_arm>;
  89                         soc-supply = <&reg_soc>;
  90                 };
  91         };
  92
  93         intc: interrupt-controller@a01000 {
  94                 compatible = "arm,cortex-a9-gic";
  95                 #interrupt-cells = <3>;
  96                 interrupt-controller;
  97                 reg = <0x00a01000 0x1000>,
  98                       <0x00a00100 0x100>;
  99                 interrupt-parent = <&intc>;
 100         };
 101
 102         ckil: clock-ckil {
 103                 compatible = "fixed-clock";
 104                 #clock-cells = <0>;
 105                 clock-frequency = <32768>;
 106                 clock-output-names = "ckil";
 107         };
 108
 109         osc: clock-osc {
 110                 compatible = "fixed-clock";
 111                 #clock-cells = <0>;
 112                 clock-frequency = <24000000>;
 113                 clock-output-names = "osc";
 114         };
 115
 116         ipp_di0: clock-ipp-di0 {
 117                 compatible = "fixed-clock";
 118                 #clock-cells = <0>;
 119                 clock-frequency = <0>;
 120                 clock-output-names = "ipp_di0";
 121         };
 122
 123         ipp_di1: clock-ipp-di1 {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 clock-frequency = <0>;
 127                 clock-output-names = "ipp_di1";
 128         };
 129
 130         anaclk1: clock-anaclk1 {
 131                 compatible = "fixed-clock";
 132                 #clock-cells = <0>;
 133                 clock-frequency = <0>;
 134                 clock-output-names = "anaclk1";
 135         };
 136
 137         anaclk2: clock-anaclk2 {
 138                 compatible = "fixed-clock";
 139                 #clock-cells = <0>;
 140                 clock-frequency = <0>;
 141                 clock-output-names = "anaclk2";
 142         };
 143
 144         tempmon: tempmon {
 145                 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
 146                 interrupt-parent = <&gpc>;
 147                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 148                 fsl,tempmon = <&anatop>;
 149                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 150                 nvmem-cell-names = "calib", "temp_grade";
 151                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 152         };
 153
 154         pmu {
 155                 compatible = "arm,cortex-a9-pmu";
 156                 interrupt-parent = <&gpc>;
 157                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 158         };
 159
 160         soc {
 161                 #address-cells = <1>;
 162                 #size-cells = <1>;
 163                 compatible = "simple-bus";
 164                 interrupt-parent = <&gpc>;
 165                 ranges;
 166
 167                 ocram_s: sram@8f8000 {
 168                         compatible = "mmio-sram";
 169                         reg = <0x008f8000 0x4000>;
 170                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 171                 };
 172
 173                 ocram: sram@900000 {
 174                         compatible = "mmio-sram";
 175                         reg = <0x00900000 0x20000>;
 176                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 177                 };
 178
 179                 L2: l2-cache@a02000 {
 180                         compatible = "arm,pl310-cache";
 181                         reg = <0x00a02000 0x1000>;
 182                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 183                         cache-unified;
 184                         cache-level = <2>;
 185                         arm,tag-latency = <4 2 3>;
 186                         arm,data-latency = <4 2 3>;
 187                 };
 188
 189                 gpu: gpu@1800000 {
 190                         compatible = "vivante,gc";
 191                         reg = <0x01800000 0x4000>;
 192                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 193                         clocks = <&clks IMX6SX_CLK_GPU>,
 194                                  <&clks IMX6SX_CLK_GPU>,
 195                                  <&clks IMX6SX_CLK_GPU>;
 196                         clock-names = "bus", "core", "shader";
 197                         power-domains = <&pd_pu>;
 198                 };
 199
 200                 dma_apbh: dma-apbh@1804000 {
 201                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 202                         reg = <0x01804000 0x2000>;
 203                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 207                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 208                         #dma-cells = <1>;
 209                         dma-channels = <4>;
 210                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 211                 };
 212
 213                 gpmi: gpmi-nand@1806000{
 214                         compatible = "fsl,imx6sx-gpmi-nand";
 215                         #address-cells = <1>;
 216                         #size-cells = <1>;
 217                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 218                         reg-names = "gpmi-nand", "bch";
 219                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 220                         interrupt-names = "bch";
 221                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 222                                  <&clks IMX6SX_CLK_GPMI_APB>,
 223                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 224                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 225                                  <&clks IMX6SX_CLK_PER1_BCH>;
 226                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 227                                       "gpmi_bch_apb", "per1_bch";
 228                         dmas = <&dma_apbh 0>;
 229                         dma-names = "rx-tx";
 230                         status = "disabled";
 231                 };
 232
 233                 aips1: aips-bus@2000000 {
 234                         compatible = "fsl,aips-bus", "simple-bus";
 235                         #address-cells = <1>;
 236                         #size-cells = <1>;
 237                         reg = <0x02000000 0x100000>;
 238                         ranges;
 239
 240                         spba-bus@2000000 {
 241                                 compatible = "fsl,spba-bus", "simple-bus";
 242                                 #address-cells = <1>;
 243                                 #size-cells = <1>;
 244                                 reg = <0x02000000 0x40000>;
 245                                 ranges;
 246
 247                                 spdif: spdif@2004000 {
 248                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 249                                         reg = <0x02004000 0x4000>;
 250                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 251                                         dmas = <&sdma 14 18 0>,
 252                                                <&sdma 15 18 0>;
 253                                         dma-names = "rx", "tx";
 254                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 255                                                  <&clks IMX6SX_CLK_OSC>,
 256                                                  <&clks IMX6SX_CLK_SPDIF>,
 257                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 258                                                  <&clks IMX6SX_CLK_IPG>,
 259                                                  <&clks 0>, <&clks 0>,
 260                                                  <&clks IMX6SX_CLK_SPBA>;
 261                                         clock-names = "core", "rxtx0",
 262                                                       "rxtx1", "rxtx2",
 263                                                       "rxtx3", "rxtx4",
 264                                                       "rxtx5", "rxtx6",
 265                                                       "rxtx7", "spba";
 266                                         status = "disabled";
 267                                 };
 268
 269                                 ecspi1: ecspi@2008000 {
 270                                         #address-cells = <1>;
 271                                         #size-cells = <0>;
 272                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 273                                         reg = <0x02008000 0x4000>;
 274                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 275                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 276                                                  <&clks IMX6SX_CLK_ECSPI1>;
 277                                         clock-names = "ipg", "per";
 278                                         status = "disabled";
 279                                 };
 280
 281                                 ecspi2: ecspi@200c000 {
 282                                         #address-cells = <1>;
 283                                         #size-cells = <0>;
 284                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 285                                         reg = <0x0200c000 0x4000>;
 286                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 287                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 288                                                  <&clks IMX6SX_CLK_ECSPI2>;
 289                                         clock-names = "ipg", "per";
 290                                         status = "disabled";
 291                                 };
 292
 293                                 ecspi3: ecspi@2010000 {
 294                                         #address-cells = <1>;
 295                                         #size-cells = <0>;
 296                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 297                                         reg = <0x02010000 0x4000>;
 298                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 299                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 300                                                  <&clks IMX6SX_CLK_ECSPI3>;
 301                                         clock-names = "ipg", "per";
 302                                         status = "disabled";
 303                                 };
 304
 305                                 ecspi4: ecspi@2014000 {
 306                                         #address-cells = <1>;
 307                                         #size-cells = <0>;
 308                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 309                                         reg = <0x02014000 0x4000>;
 310                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 311                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 312                                                  <&clks IMX6SX_CLK_ECSPI4>;
 313                                         clock-names = "ipg", "per";
 314                                         status = "disabled";
 315                                 };
 316
 317                                 uart1: serial@2020000 {
 318                                         compatible = "fsl,imx6sx-uart",
 319                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 320                                         reg = <0x02020000 0x4000>;
 321                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 322                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 323                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 324                                         clock-names = "ipg", "per";
 325                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 326                                         dma-names = "rx", "tx";
 327                                         status = "disabled";
 328                                 };
 329
 330                                 esai: esai@2024000 {
 331                                         reg = <0x02024000 0x4000>;
 332                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 333                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 334                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 335                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 336                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 337                                                  <&clks IMX6SX_CLK_SPBA>;
 338                                         clock-names = "core", "mem", "extal",
 339                                                       "fsys", "spba";
 340                                         status = "disabled";
 341                                 };
 342
 343                                 ssi1: ssi@2028000 {
 344                                         #sound-dai-cells = <0>;
 345                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 346                                         reg = <0x02028000 0x4000>;
 347                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 348                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 349                                                  <&clks IMX6SX_CLK_SSI1>;
 350                                         clock-names = "ipg", "baud";
 351                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 352                                         dma-names = "rx", "tx";
 353                                         fsl,fifo-depth = <15>;
 354                                         status = "disabled";
 355                                 };
 356
 357                                 ssi2: ssi@202c000 {
 358                                         #sound-dai-cells = <0>;
 359                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 360                                         reg = <0x0202c000 0x4000>;
 361                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 362                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 363                                                  <&clks IMX6SX_CLK_SSI2>;
 364                                         clock-names = "ipg", "baud";
 365                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 366                                         dma-names = "rx", "tx";
 367                                         fsl,fifo-depth = <15>;
 368                                         status = "disabled";
 369                                 };
 370
 371                                 ssi3: ssi@2030000 {
 372                                         #sound-dai-cells = <0>;
 373                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 374                                         reg = <0x02030000 0x4000>;
 375                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 376                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 377                                                  <&clks IMX6SX_CLK_SSI3>;
 378                                         clock-names = "ipg", "baud";
 379                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 380                                         dma-names = "rx", "tx";
 381                                         fsl,fifo-depth = <15>;
 382                                         status = "disabled";
 383                                 };
 384
 385                                 asrc: asrc@2034000 {
 386                                         reg = <0x02034000 0x4000>;
 387                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 388                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
 389                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
 390                                                  <&clks IMX6SX_CLK_SPDIF>,
 391                                                  <&clks IMX6SX_CLK_SPBA>;
 392                                         clock-names = "mem", "ipg", "asrck", "spba";
 393                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
 394                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
 395                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
 396                                         dma-names = "rxa", "rxb", "rxc",
 397                                                     "txa", "txb", "txc";
 398                                         status = "okay";
 399                                 };
 400                         };
 401
 402                         pwm1: pwm@2080000 {
 403                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 404                                 reg = <0x02080000 0x4000>;
 405                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 407                                          <&clks IMX6SX_CLK_PWM1>;
 408                                 clock-names = "ipg", "per";
 409                                 #pwm-cells = <2>;
 410                         };
 411
 412                         pwm2: pwm@2084000 {
 413                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 414                                 reg = <0x02084000 0x4000>;
 415                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 416                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 417                                          <&clks IMX6SX_CLK_PWM2>;
 418                                 clock-names = "ipg", "per";
 419                                 #pwm-cells = <2>;
 420                         };
 421
 422                         pwm3: pwm@2088000 {
 423                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 424                                 reg = <0x02088000 0x4000>;
 425                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 426                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 427                                          <&clks IMX6SX_CLK_PWM3>;
 428                                 clock-names = "ipg", "per";
 429                                 #pwm-cells = <2>;
 430                         };
 431
 432                         pwm4: pwm@208c000 {
 433                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 434                                 reg = <0x0208c000 0x4000>;
 435                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 436                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 437                                          <&clks IMX6SX_CLK_PWM4>;
 438                                 clock-names = "ipg", "per";
 439                                 #pwm-cells = <2>;
 440                         };
 441
 442                         flexcan1: can@2090000 {
 443                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 444                                 reg = <0x02090000 0x4000>;
 445                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 446                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 447                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 448                                 clock-names = "ipg", "per";
 449                                 status = "disabled";
 450                         };
 451
 452                         flexcan2: can@2094000 {
 453                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 454                                 reg = <0x02094000 0x4000>;
 455                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 456                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 457                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 458                                 clock-names = "ipg", "per";
 459                                 status = "disabled";
 460                         };
 461
 462                         gpt: gpt@2098000 {
 463                                 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
 464                                 reg = <0x02098000 0x4000>;
 465                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 466                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 467                                          <&clks IMX6SX_CLK_GPT_3M>;
 468                                 clock-names = "ipg", "per";
 469                         };
 470
 471                         gpio1: gpio@209c000 {
 472                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 473                                 reg = <0x0209c000 0x4000>;
 474                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 475                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 476                                 gpio-controller;
 477                                 #gpio-cells = <2>;
 478                                 interrupt-controller;
 479                                 #interrupt-cells = <2>;
 480                                 gpio-ranges = <&iomuxc 0 5 26>;
 481                         };
 482
 483                         gpio2: gpio@20a0000 {
 484                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 485                                 reg = <0x020a0000 0x4000>;
 486                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 487                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 488                                 gpio-controller;
 489                                 #gpio-cells = <2>;
 490                                 interrupt-controller;
 491                                 #interrupt-cells = <2>;
 492                                 gpio-ranges = <&iomuxc 0 31 20>;
 493                         };
 494
 495                         gpio3: gpio@20a4000 {
 496                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 497                                 reg = <0x020a4000 0x4000>;
 498                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 499                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 500                                 gpio-controller;
 501                                 #gpio-cells = <2>;
 502                                 interrupt-controller;
 503                                 #interrupt-cells = <2>;
 504                                 gpio-ranges = <&iomuxc 0 51 29>;
 505                         };
 506
 507                         gpio4: gpio@20a8000 {
 508                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 509                                 reg = <0x020a8000 0x4000>;
 510                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 511                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 512                                 gpio-controller;
 513                                 #gpio-cells = <2>;
 514                                 interrupt-controller;
 515                                 #interrupt-cells = <2>;
 516                                 gpio-ranges = <&iomuxc 0 80 32>;
 517                         };
 518
 519                         gpio5: gpio@20ac000 {
 520                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 521                                 reg = <0x020ac000 0x4000>;
 522                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 523                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 524                                 gpio-controller;
 525                                 #gpio-cells = <2>;
 526                                 interrupt-controller;
 527                                 #interrupt-cells = <2>;
 528                                 gpio-ranges = <&iomuxc 0 112 24>;
 529                         };
 530
 531                         gpio6: gpio@20b0000 {
 532                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 533                                 reg = <0x020b0000 0x4000>;
 534                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 535                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 536                                 gpio-controller;
 537                                 #gpio-cells = <2>;
 538                                 interrupt-controller;
 539                                 #interrupt-cells = <2>;
 540                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
 541                         };
 542
 543                         gpio7: gpio@20b4000 {
 544                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 545                                 reg = <0x020b4000 0x4000>;
 546                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 547                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 548                                 gpio-controller;
 549                                 #gpio-cells = <2>;
 550                                 interrupt-controller;
 551                                 #interrupt-cells = <2>;
 552                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
 553                         };
 554
 555                         kpp: kpp@20b8000 {
 556                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 557                                 reg = <0x020b8000 0x4000>;
 558                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 559                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 560                                 status = "disabled";
 561                         };
 562
 563                         wdog1: wdog@20bc000 {
 564                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 565                                 reg = <0x020bc000 0x4000>;
 566                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 567                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 568                         };
 569
 570                         wdog2: wdog@20c0000 {
 571                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 572                                 reg = <0x020c0000 0x4000>;
 573                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 574                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 575                                 status = "disabled";
 576                         };
 577
 578                         clks: ccm@20c4000 {
 579                                 compatible = "fsl,imx6sx-ccm";
 580                                 reg = <0x020c4000 0x4000>;
 581                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 582                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 583                                 #clock-cells = <1>;
 584                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
 585                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
 586                         };
 587
 588                         anatop: anatop@20c8000 {
 589                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 590                                              "syscon", "simple-bus";
 591                                 reg = <0x020c8000 0x1000>;
 592                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 593                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 594                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 595
 596                                 regulator-1p1 {
 597                                         compatible = "fsl,anatop-regulator";
 598                                         regulator-name = "vdd1p1";
 599                                         regulator-min-microvolt = <1000000>;
 600                                         regulator-max-microvolt = <1200000>;
 601                                         regulator-always-on;
 602                                         anatop-reg-offset = <0x110>;
 603                                         anatop-vol-bit-shift = <8>;
 604                                         anatop-vol-bit-width = <5>;
 605                                         anatop-min-bit-val = <4>;
 606                                         anatop-min-voltage = <800000>;
 607                                         anatop-max-voltage = <1375000>;
 608                                         anatop-enable-bit = <0>;
 609                                 };
 610
 611                                 regulator-3p0 {
 612                                         compatible = "fsl,anatop-regulator";
 613                                         regulator-name = "vdd3p0";
 614                                         regulator-min-microvolt = <2800000>;
 615                                         regulator-max-microvolt = <3150000>;
 616                                         regulator-always-on;
 617                                         anatop-reg-offset = <0x120>;
 618                                         anatop-vol-bit-shift = <8>;
 619                                         anatop-vol-bit-width = <5>;
 620                                         anatop-min-bit-val = <0>;
 621                                         anatop-min-voltage = <2625000>;
 622                                         anatop-max-voltage = <3400000>;
 623                                         anatop-enable-bit = <0>;
 624                                 };
 625
 626                                 regulator-2p5 {
 627                                         compatible = "fsl,anatop-regulator";
 628                                         regulator-name = "vdd2p5";
 629                                         regulator-min-microvolt = <2250000>;
 630                                         regulator-max-microvolt = <2750000>;
 631                                         regulator-always-on;
 632                                         anatop-reg-offset = <0x130>;
 633                                         anatop-vol-bit-shift = <8>;
 634                                         anatop-vol-bit-width = <5>;
 635                                         anatop-min-bit-val = <0>;
 636                                         anatop-min-voltage = <2100000>;
 637                                         anatop-max-voltage = <2875000>;
 638                                         anatop-enable-bit = <0>;
 639                                 };
 640
 641                                 reg_arm: regulator-vddcore {
 642                                         compatible = "fsl,anatop-regulator";
 643                                         regulator-name = "vddarm";
 644                                         regulator-min-microvolt = <725000>;
 645                                         regulator-max-microvolt = <1450000>;
 646                                         regulator-always-on;
 647                                         anatop-reg-offset = <0x140>;
 648                                         anatop-vol-bit-shift = <0>;
 649                                         anatop-vol-bit-width = <5>;
 650                                         anatop-delay-reg-offset = <0x170>;
 651                                         anatop-delay-bit-shift = <24>;
 652                                         anatop-delay-bit-width = <2>;
 653                                         anatop-min-bit-val = <1>;
 654                                         anatop-min-voltage = <725000>;
 655                                         anatop-max-voltage = <1450000>;
 656                                 };
 657
 658                                 reg_pcie: regulator-vddpcie {
 659                                         compatible = "fsl,anatop-regulator";
 660                                         regulator-name = "vddpcie";
 661                                         regulator-min-microvolt = <725000>;
 662                                         regulator-max-microvolt = <1450000>;
 663                                         anatop-reg-offset = <0x140>;
 664                                         anatop-vol-bit-shift = <9>;
 665                                         anatop-vol-bit-width = <5>;
 666                                         anatop-delay-reg-offset = <0x170>;
 667                                         anatop-delay-bit-shift = <26>;
 668                                         anatop-delay-bit-width = <2>;
 669                                         anatop-min-bit-val = <1>;
 670                                         anatop-min-voltage = <725000>;
 671                                         anatop-max-voltage = <1450000>;
 672                                 };
 673
 674                                 reg_soc: regulator-vddsoc {
 675                                         compatible = "fsl,anatop-regulator";
 676                                         regulator-name = "vddsoc";
 677                                         regulator-min-microvolt = <725000>;
 678                                         regulator-max-microvolt = <1450000>;
 679                                         regulator-always-on;
 680                                         anatop-reg-offset = <0x140>;
 681                                         anatop-vol-bit-shift = <18>;
 682                                         anatop-vol-bit-width = <5>;
 683                                         anatop-delay-reg-offset = <0x170>;
 684                                         anatop-delay-bit-shift = <28>;
 685                                         anatop-delay-bit-width = <2>;
 686                                         anatop-min-bit-val = <1>;
 687                                         anatop-min-voltage = <725000>;
 688                                         anatop-max-voltage = <1450000>;
 689                                 };
 690                         };
 691
 692                         usbphy1: usbphy@20c9000 {
 693                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 694                                 reg = <0x020c9000 0x1000>;
 695                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 696                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 697                                 fsl,anatop = <&anatop>;
 698                         };
 699
 700                         usbphy2: usbphy@20ca000 {
 701                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 702                                 reg = <0x020ca000 0x1000>;
 703                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 705                                 fsl,anatop = <&anatop>;
 706                         };
 707
 708                         snvs: snvs@20cc000 {
 709                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 710                                 reg = <0x020cc000 0x4000>;
 711
 712                                 snvs_rtc: snvs-rtc-lp {
 713                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 714                                         regmap = <&snvs>;
 715                                         offset = <0x34>;
 716                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 717                                 };
 718
 719                                 snvs_poweroff: snvs-poweroff {
 720                                         compatible = "syscon-poweroff";
 721                                         regmap = <&snvs>;
 722                                         offset = <0x38>;
 723                                         value = <0x60>;
 724                                         mask = <0x60>;
 725                                         status = "disabled";
 726                                 };
 727
 728                                 snvs_pwrkey: snvs-powerkey {
 729                                         compatible = "fsl,sec-v4.0-pwrkey";
 730                                         regmap = <&snvs>;
 731                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 732                                         linux,keycode = <KEY_POWER>;
 733                                         wakeup-source;
 734                                 };
 735                         };
 736
 737                         epit1: epit@20d0000 {
 738                                 reg = <0x020d0000 0x4000>;
 739                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 740                         };
 741
 742                         epit2: epit@20d4000 {
 743                                 reg = <0x020d4000 0x4000>;
 744                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 745                         };
 746
 747                         src: src@20d8000 {
 748                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 749                                 reg = <0x020d8000 0x4000>;
 750                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 751                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 752                                 #reset-cells = <1>;
 753                         };
 754
 755                         gpc: gpc@20dc000 {
 756                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 757                                 reg = <0x020dc000 0x4000>;
 758                                 interrupt-controller;
 759                                 #interrupt-cells = <3>;
 760                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 761                                 interrupt-parent = <&intc>;
 762                                 clocks = <&clks IMX6SX_CLK_IPG>;
 763                                 clock-names = "ipg";
 764
 765                                 pgc {
 766                                         #address-cells = <1>;
 767                                         #size-cells = <0>;
 768
 769                                         power-domain@0 {
 770                                                 reg = <0>;
 771                                                 #power-domain-cells = <0>;
 772                                         };
 773
 774                                         pd_pu: power-domain@1 {
 775                                                 reg = <1>;
 776                                                 #power-domain-cells = <0>;
 777                                                 power-supply = <&reg_soc>;
 778                                                 clocks = <&clks IMX6SX_CLK_GPU>;
 779                                         };
 780
 781                                         pd_pci: power-domain@3 {
 782                                                 reg = <3>;
 783                                                 #power-domain-cells = <0>;
 784                                                 power-supply = <&reg_pcie>;
 785                                         };
 786                                 };
 787                         };
 788
 789                         iomuxc: iomuxc@20e0000 {
 790                                 compatible = "fsl,imx6sx-iomuxc";
 791                                 reg = <0x020e0000 0x4000>;
 792                         };
 793
 794                         gpr: iomuxc-gpr@20e4000 {
 795                                 compatible = "fsl,imx6sx-iomuxc-gpr",
 796                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 797                                 reg = <0x020e4000 0x4000>;
 798                         };
 799
 800                         sdma: sdma@20ec000 {
 801                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
 802                                 reg = <0x020ec000 0x4000>;
 803                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clks IMX6SX_CLK_IPG>,
 805                                          <&clks IMX6SX_CLK_SDMA>;
 806                                 clock-names = "ipg", "ahb";
 807                                 #dma-cells = <3>;
 808                                 /* imx6sx reuses imx6q sdma firmware */
 809                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 810                         };
 811                 };
 812
 813                 aips2: aips-bus@2100000 {
 814                         compatible = "fsl,aips-bus", "simple-bus";
 815                         #address-cells = <1>;
 816                         #size-cells = <1>;
 817                         reg = <0x02100000 0x100000>;
 818                         ranges;
 819
 820                         crypto: caam@2100000 {
 821                                 compatible = "fsl,sec-v4.0";
 822                                 #address-cells = <1>;
 823                                 #size-cells = <1>;
 824                                 reg = <0x2100000 0x10000>;
 825                                 ranges = <0 0x2100000 0x10000>;
 826                                 interrupt-parent = <&intc>;
 827                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
 828                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
 829                                          <&clks IMX6SX_CLK_CAAM_IPG>,
 830                                          <&clks IMX6SX_CLK_EIM_SLOW>;
 831                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 832
 833                                 sec_jr0: jr0@1000 {
 834                                         compatible = "fsl,sec-v4.0-job-ring";
 835                                         reg = <0x1000 0x1000>;
 836                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 837                                 };
 838
 839                                 sec_jr1: jr1@2000 {
 840                                         compatible = "fsl,sec-v4.0-job-ring";
 841                                         reg = <0x2000 0x1000>;
 842                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 843                                 };
 844                         };
 845
 846                         usbotg1: usb@2184000 {
 847                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 848                                 reg = <0x02184000 0x200>;
 849                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 850                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 851                                 fsl,usbphy = <&usbphy1>;
 852                                 fsl,usbmisc = <&usbmisc 0>;
 853                                 fsl,anatop = <&anatop>;
 854                                 ahb-burst-config = <0x0>;
 855                                 tx-burst-size-dword = <0x10>;
 856                                 rx-burst-size-dword = <0x10>;
 857                                 status = "disabled";
 858                         };
 859
 860                         usbotg2: usb@2184200 {
 861                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 862                                 reg = <0x02184200 0x200>;
 863                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 864                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 865                                 fsl,usbphy = <&usbphy2>;
 866                                 fsl,usbmisc = <&usbmisc 1>;
 867                                 ahb-burst-config = <0x0>;
 868                                 tx-burst-size-dword = <0x10>;
 869                                 rx-burst-size-dword = <0x10>;
 870                                 status = "disabled";
 871                         };
 872
 873                         usbh: usb@2184400 {
 874                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 875                                 reg = <0x02184400 0x200>;
 876                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 877                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 878                                 fsl,usbmisc = <&usbmisc 2>;
 879                                 phy_type = "hsic";
 880                                 fsl,anatop = <&anatop>;
 881                                 dr_mode = "host";
 882                                 ahb-burst-config = <0x0>;
 883                                 tx-burst-size-dword = <0x10>;
 884                                 rx-burst-size-dword = <0x10>;
 885                                 status = "disabled";
 886                         };
 887
 888                         usbmisc: usbmisc@2184800 {
 889                                 #index-cells = <1>;
 890                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 891                                 reg = <0x02184800 0x200>;
 892                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 893                         };
 894
 895                         fec1: ethernet@2188000 {
 896                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 897                                 reg = <0x02188000 0x4000>;
 898                                 interrupt-names = "int0", "pps";
 899                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 900                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clks IMX6SX_CLK_ENET>,
 902                                          <&clks IMX6SX_CLK_ENET_AHB>,
 903                                          <&clks IMX6SX_CLK_ENET_PTP>,
 904                                          <&clks IMX6SX_CLK_ENET_REF>,
 905                                          <&clks IMX6SX_CLK_ENET_PTP>;
 906                                 clock-names = "ipg", "ahb", "ptp",
 907                                               "enet_clk_ref", "enet_out";
 908                                 fsl,num-tx-queues=<3>;
 909                                 fsl,num-rx-queues=<3>;
 910                                 status = "disabled";
 911                         };
 912
 913                         mlb: mlb@218c000 {
 914                                 reg = <0x0218c000 0x4000>;
 915                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 916                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 917                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 918                                 clocks = <&clks IMX6SX_CLK_MLB>;
 919                                 status = "disabled";
 920                         };
 921
 922                         usdhc1: usdhc@2190000 {
 923                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 924                                 reg = <0x02190000 0x4000>;
 925                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 926                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 927                                          <&clks IMX6SX_CLK_USDHC1>,
 928                                          <&clks IMX6SX_CLK_USDHC1>;
 929                                 clock-names = "ipg", "ahb", "per";
 930                                 bus-width = <4>;
 931                                 status = "disabled";
 932                         };
 933
 934                         usdhc2: usdhc@2194000 {
 935                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 936                                 reg = <0x02194000 0x4000>;
 937                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 938                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 939                                          <&clks IMX6SX_CLK_USDHC2>,
 940                                          <&clks IMX6SX_CLK_USDHC2>;
 941                                 clock-names = "ipg", "ahb", "per";
 942                                 bus-width = <4>;
 943                                 status = "disabled";
 944                         };
 945
 946                         usdhc3: usdhc@2198000 {
 947                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 948                                 reg = <0x02198000 0x4000>;
 949                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 950                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 951                                          <&clks IMX6SX_CLK_USDHC3>,
 952                                          <&clks IMX6SX_CLK_USDHC3>;
 953                                 clock-names = "ipg", "ahb", "per";
 954                                 bus-width = <4>;
 955                                 status = "disabled";
 956                         };
 957
 958                         usdhc4: usdhc@219c000 {
 959                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 960                                 reg = <0x0219c000 0x4000>;
 961                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 962                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 963                                          <&clks IMX6SX_CLK_USDHC4>,
 964                                          <&clks IMX6SX_CLK_USDHC4>;
 965                                 clock-names = "ipg", "ahb", "per";
 966                                 bus-width = <4>;
 967                                 status = "disabled";
 968                         };
 969
 970                         i2c1: i2c@21a0000 {
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 974                                 reg = <0x021a0000 0x4000>;
 975                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 976                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 977                                 status = "disabled";
 978                         };
 979
 980                         i2c2: i2c@21a4000 {
 981                                 #address-cells = <1>;
 982                                 #size-cells = <0>;
 983                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 984                                 reg = <0x021a4000 0x4000>;
 985                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 986                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 987                                 status = "disabled";
 988                         };
 989
 990                         i2c3: i2c@21a8000 {
 991                                 #address-cells = <1>;
 992                                 #size-cells = <0>;
 993                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 994                                 reg = <0x021a8000 0x4000>;
 995                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 996                                 clocks = <&clks IMX6SX_CLK_I2C3>;
 997                                 status = "disabled";
 998                         };
 999
1000                         mmdc: mmdc@21b0000 {
1001                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1002                                 reg = <0x021b0000 0x4000>;
1003                         };
1004
1005                         fec2: ethernet@21b4000 {
1006                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1007                                 reg = <0x021b4000 0x4000>;
1008                                 interrupt-names = "int0", "pps";
1009                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1010                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1011                                 clocks = <&clks IMX6SX_CLK_ENET>,
1012                                          <&clks IMX6SX_CLK_ENET_AHB>,
1013                                          <&clks IMX6SX_CLK_ENET_PTP>,
1014                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1015                                          <&clks IMX6SX_CLK_ENET_PTP>;
1016                                 clock-names = "ipg", "ahb", "ptp",
1017                                               "enet_clk_ref", "enet_out";
1018                                 status = "disabled";
1019                         };
1020
1021                         weim: weim@21b8000 {
1022                                 #address-cells = <2>;
1023                                 #size-cells = <1>;
1024                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1025                                 reg = <0x021b8000 0x4000>;
1026                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1027                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1028                                 fsl,weim-cs-gpr = <&gpr>;
1029                                 status = "disabled";
1030                         };
1031
1032                         ocotp: ocotp@21bc000 {
1033                                 #address-cells = <1>;
1034                                 #size-cells = <1>;
1035                                 compatible = "fsl,imx6sx-ocotp", "syscon";
1036                                 reg = <0x021bc000 0x4000>;
1037                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1038
1039                                 tempmon_calib: calib@38 {
1040                                         reg = <0x38 4>;
1041                                 };
1042
1043                                 tempmon_temp_grade: temp-grade@20 {
1044                                         reg = <0x20 4>;
1045                                 };
1046                         };
1047
1048                         sai1: sai@21d4000 {
1049                                 compatible = "fsl,imx6sx-sai";
1050                                 reg = <0x021d4000 0x4000>;
1051                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1052                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1053                                          <&clks IMX6SX_CLK_SAI1>,
1054                                          <&clks 0>, <&clks 0>;
1055                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1056                                 dma-names = "rx", "tx";
1057                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1058                                 status = "disabled";
1059                         };
1060
1061                         audmux: audmux@21d8000 {
1062                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1063                                 reg = <0x021d8000 0x4000>;
1064                                 status = "disabled";
1065                         };
1066
1067                         sai2: sai@21dc000 {
1068                                 compatible = "fsl,imx6sx-sai";
1069                                 reg = <0x021dc000 0x4000>;
1070                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1071                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1072                                          <&clks IMX6SX_CLK_SAI2>,
1073                                          <&clks 0>, <&clks 0>;
1074                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1075                                 dma-names = "rx", "tx";
1076                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1077                                 status = "disabled";
1078                         };
1079
1080                         qspi1: qspi@21e0000 {
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083                                 compatible = "fsl,imx6sx-qspi";
1084                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1085                                 reg-names = "QuadSPI", "QuadSPI-memory";
1086                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1087                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1088                                          <&clks IMX6SX_CLK_QSPI1>;
1089                                 clock-names = "qspi_en", "qspi";
1090                                 status = "disabled";
1091                         };
1092
1093                         qspi2: qspi@21e4000 {
1094                                 #address-cells = <1>;
1095                                 #size-cells = <0>;
1096                                 compatible = "fsl,imx6sx-qspi";
1097                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1098                                 reg-names = "QuadSPI", "QuadSPI-memory";
1099                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1100                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1101                                          <&clks IMX6SX_CLK_QSPI2>;
1102                                 clock-names = "qspi_en", "qspi";
1103                                 status = "disabled";
1104                         };
1105
1106                         uart2: serial@21e8000 {
1107                                 compatible = "fsl,imx6sx-uart",
1108                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1109                                 reg = <0x021e8000 0x4000>;
1110                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1111                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1112                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1113                                 clock-names = "ipg", "per";
1114                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1115                                 dma-names = "rx", "tx";
1116                                 status = "disabled";
1117                         };
1118
1119                         uart3: serial@21ec000 {
1120                                 compatible = "fsl,imx6sx-uart",
1121                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1122                                 reg = <0x021ec000 0x4000>;
1123                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1124                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1125                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1126                                 clock-names = "ipg", "per";
1127                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1128                                 dma-names = "rx", "tx";
1129                                 status = "disabled";
1130                         };
1131
1132                         uart4: serial@21f0000 {
1133                                 compatible = "fsl,imx6sx-uart",
1134                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1135                                 reg = <0x021f0000 0x4000>;
1136                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1137                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1138                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1139                                 clock-names = "ipg", "per";
1140                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1141                                 dma-names = "rx", "tx";
1142                                 status = "disabled";
1143                         };
1144
1145                         uart5: serial@21f4000 {
1146                                 compatible = "fsl,imx6sx-uart",
1147                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1148                                 reg = <0x021f4000 0x4000>;
1149                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1150                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1151                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1152                                 clock-names = "ipg", "per";
1153                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1154                                 dma-names = "rx", "tx";
1155                                 status = "disabled";
1156                         };
1157
1158                         i2c4: i2c@21f8000 {
1159                                 #address-cells = <1>;
1160                                 #size-cells = <0>;
1161                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1162                                 reg = <0x021f8000 0x4000>;
1163                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1164                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1165                                 status = "disabled";
1166                         };
1167                 };
1168
1169                 aips3: aips-bus@2200000 {
1170                         compatible = "fsl,aips-bus", "simple-bus";
1171                         #address-cells = <1>;
1172                         #size-cells = <1>;
1173                         reg = <0x02200000 0x100000>;
1174                         ranges;
1175
1176                         spba-bus@2240000 {
1177                                 compatible = "fsl,spba-bus", "simple-bus";
1178                                 #address-cells = <1>;
1179                                 #size-cells = <1>;
1180                                 reg = <0x02240000 0x40000>;
1181                                 ranges;
1182
1183                                 csi1: csi@2214000 {
1184                                         reg = <0x02214000 0x4000>;
1185                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1186                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1187                                                  <&clks IMX6SX_CLK_CSI>,
1188                                                  <&clks IMX6SX_CLK_DCIC1>;
1189                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1190                                         status = "disabled";
1191                                 };
1192
1193                                 pxp: pxp@2218000 {
1194                                         reg = <0x02218000 0x4000>;
1195                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1196                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1197                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1198                                         clock-names = "pxp-axi", "disp-axi";
1199                                         status = "disabled";
1200                                 };
1201
1202                                 csi2: csi@221c000 {
1203                                         reg = <0x0221c000 0x4000>;
1204                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1205                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1206                                                  <&clks IMX6SX_CLK_CSI>,
1207                                                  <&clks IMX6SX_CLK_DCIC2>;
1208                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1209                                         status = "disabled";
1210                                 };
1211
1212                                 lcdif1: lcdif@2220000 {
1213                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1214                                         reg = <0x02220000 0x4000>;
1215                                         interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1216                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1217                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1218                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1219                                         clock-names = "pix", "axi", "disp_axi";
1220                                         status = "disabled";
1221                                 };
1222
1223                                 lcdif2: lcdif@2224000 {
1224                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1225                                         reg = <0x02224000 0x4000>;
1226                                         interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1227                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1228                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1229                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1230                                         clock-names = "pix", "axi", "disp_axi";
1231                                         status = "disabled";
1232                                 };
1233
1234                                 vadc: vadc@2228000 {
1235                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1236                                         reg-names = "vadc-vafe", "vadc-vdec";
1237                                         clocks = <&clks IMX6SX_CLK_VADC>,
1238                                                  <&clks IMX6SX_CLK_CSI>;
1239                                         clock-names = "vadc", "csi";
1240                                         status = "disabled";
1241                                 };
1242                         };
1243
1244                         adc1: adc@2280000 {
1245                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1246                                 reg = <0x02280000 0x4000>;
1247                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1248                                 clocks = <&clks IMX6SX_CLK_IPG>;
1249                                 clock-names = "adc";
1250                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1251                                                          <20000000>;
1252                                 status = "disabled";
1253                         };
1254
1255                         adc2: adc@2284000 {
1256                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1257                                 reg = <0x02284000 0x4000>;
1258                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1259                                 clocks = <&clks IMX6SX_CLK_IPG>;
1260                                 clock-names = "adc";
1261                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1262                                                          <20000000>;
1263                                 status = "disabled";
1264                         };
1265
1266                         wdog3: wdog@2288000 {
1267                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1268                                 reg = <0x02288000 0x4000>;
1269                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1270                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1271                                 status = "disabled";
1272                         };
1273
1274                         ecspi5: ecspi@228c000 {
1275                                 #address-cells = <1>;
1276                                 #size-cells = <0>;
1277                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1278                                 reg = <0x0228c000 0x4000>;
1279                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1280                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1281                                          <&clks IMX6SX_CLK_ECSPI5>;
1282                                 clock-names = "ipg", "per";
1283                                 status = "disabled";
1284                         };
1285
1286                         uart6: serial@22a0000 {
1287                                 compatible = "fsl,imx6sx-uart",
1288                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1289                                 reg = <0x022a0000 0x4000>;
1290                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1291                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1292                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1293                                 clock-names = "ipg", "per";
1294                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1295                                 dma-names = "rx", "tx";
1296                                 status = "disabled";
1297                         };
1298
1299                         pwm5: pwm@22a4000 {
1300                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1301                                 reg = <0x022a4000 0x4000>;
1302                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1303                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1304                                          <&clks IMX6SX_CLK_PWM5>;
1305                                 clock-names = "ipg", "per";
1306                                 #pwm-cells = <2>;
1307                         };
1308
1309                         pwm6: pwm@22a8000 {
1310                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1311                                 reg = <0x022a8000 0x4000>;
1312                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1313                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1314                                          <&clks IMX6SX_CLK_PWM6>;
1315                                 clock-names = "ipg", "per";
1316                                 #pwm-cells = <2>;
1317                         };
1318
1319                         pwm7: pwm@22ac000 {
1320                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1321                                 reg = <0x022ac000 0x4000>;
1322                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1323                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1324                                          <&clks IMX6SX_CLK_PWM7>;
1325                                 clock-names = "ipg", "per";
1326                                 #pwm-cells = <2>;
1327                         };
1328
1329                         pwm8: pwm@22b0000 {
1330                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1331                                 reg = <0x0022b0000 0x4000>;
1332                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1333                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1334                                          <&clks IMX6SX_CLK_PWM8>;
1335                                 clock-names = "ipg", "per";
1336                                 #pwm-cells = <2>;
1337                         };
1338                 };
1339
1340                 pcie: pcie@8ffc000 {
1341                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1342                         reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1343                         reg-names = "dbi", "config";
1344                         #address-cells = <3>;
1345                         #size-cells = <2>;
1346                         device_type = "pci";
1347                         bus-range = <0x00 0xff>;
1348                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1349                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1350                         num-lanes = <1>;
1351                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1352                         interrupt-names = "msi";
1353                         #interrupt-cells = <1>;
1354                         interrupt-map-mask = <0 0 0 0x7>;
1355                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1356                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1357                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1358                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1359                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1360                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1361                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1362                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1363                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1364                         power-domains = <&pd_pci>;
1365                         status = "disabled";
1366                 };
1367         };
1368 };