arch/arm/boot/dts/imx6sx-sdb.dtsi

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13 #include "imx6sx.dtsi"
  14
  15 / {
  16         model = "Freescale i.MX6 SoloX SDB Board";
  17         compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         memory@80000000 {
  24                 device_type = "memory";
  25                 reg = <0x80000000 0x40000000>;
  26         };
  27
  28         backlight_display: backlight-display {
  29                 compatible = "pwm-backlight";
  30                 pwms = <&pwm3 0 5000000>;
  31                 brightness-levels = <0 4 8 16 32 64 128 255>;
  32                 default-brightness-level = <6>;
  33         };
  34
  35         gpio-keys {
  36                 compatible = "gpio-keys";
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&pinctrl_gpio_keys>;
  39
  40                 volume-up {
  41                         label = "Volume Up";
  42                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  43                         linux,code = <KEY_VOLUMEUP>;
  44                 };
  45
  46                 volume-down {
  47                         label = "Volume Down";
  48                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  49                         linux,code = <KEY_VOLUMEDOWN>;
  50                 };
  51         };
  52
  53         vcc_sd3: regulator-vcc-sd3 {
  54                 compatible = "regulator-fixed";
  55                 pinctrl-names = "default";
  56                 pinctrl-0 = <&pinctrl_vcc_sd3>;
  57                 regulator-name = "VCC_SD3";
  58                 regulator-min-microvolt = <3000000>;
  59                 regulator-max-microvolt = <3000000>;
  60                 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  61                 enable-active-high;
  62         };
  63
  64         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  65                 compatible = "regulator-fixed";
  66                 pinctrl-names = "default";
  67                 pinctrl-0 = <&pinctrl_usb_otg1>;
  68                 regulator-name = "usb_otg1_vbus";
  69                 regulator-min-microvolt = <5000000>;
  70                 regulator-max-microvolt = <5000000>;
  71                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  72                 enable-active-high;
  73         };
  74
  75         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  76                 compatible = "regulator-fixed";
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&pinctrl_usb_otg2>;
  79                 regulator-name = "usb_otg2_vbus";
  80                 regulator-min-microvolt = <5000000>;
  81                 regulator-max-microvolt = <5000000>;
  82                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  83                 enable-active-high;
  84         };
  85
  86         reg_psu_5v: regulator-psu-5v {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "PSU-5V0";
  89                 regulator-min-microvolt = <5000000>;
  90                 regulator-max-microvolt = <5000000>;
  91         };
  92
  93         reg_lcd_3v3: regulator-lcd-3v3 {
  94                 compatible = "regulator-fixed";
  95                 regulator-name = "lcd-3v3";
  96                 gpio = <&gpio3 27 0>;
  97                 enable-active-high;
  98         };
  99
 100         reg_peri_3v3: regulator-peri-3v3 {
 101                 compatible = "regulator-fixed";
 102                 pinctrl-names = "default";
 103                 pinctrl-0 = <&pinctrl_peri_3v3>;
 104                 regulator-name = "peri_3v3";
 105                 regulator-min-microvolt = <3300000>;
 106                 regulator-max-microvolt = <3300000>;
 107                 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 108                 enable-active-high;
 109                 regulator-always-on;
 110         };
 111
 112         reg_enet_3v3: regulator-enet-3v3 {
 113                 compatible = "regulator-fixed";
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_enet_3v3>;
 116                 regulator-name = "enet_3v3";
 117                 regulator-min-microvolt = <3300000>;
 118                 regulator-max-microvolt = <3300000>;
 119                 gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
 120                 regulator-boot-on;
 121                 regulator-always-on;
 122         };
 123
 124         reg_pcie_gpio: regulator-pcie-gpio {
 125                 compatible = "regulator-fixed";
 126                 pinctrl-names = "default";
 127                 pinctrl-0 = <&pinctrl_pcie_reg>;
 128                 regulator-name = "MPCIE_3V3";
 129                 regulator-min-microvolt = <3300000>;
 130                 regulator-max-microvolt = <3300000>;
 131                 gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 132                 enable-active-high;
 133         };
 134
 135         reg_lcd_5v: regulator-lcd-5v {
 136                 compatible = "regulator-fixed";
 137                 regulator-name = "lcd-5v0";
 138                 regulator-min-microvolt = <5000000>;
 139                 regulator-max-microvolt = <5000000>;
 140         };
 141
 142         sound {
 143                 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
 144                 model = "wm8962-audio";
 145                 ssi-controller = <&ssi2>;
 146                 audio-codec = <&codec>;
 147                 audio-routing =
 148                         "Headphone Jack", "HPOUTL",
 149                         "Headphone Jack", "HPOUTR",
 150                         "Ext Spk", "SPKOUTL",
 151                         "Ext Spk", "SPKOUTR",
 152                         "AMIC", "MICBIAS",
 153                         "IN3R", "AMIC";
 154                 mux-int-port = <2>;
 155                 mux-ext-port = <6>;
 156         };
 157
 158         panel {
 159                 compatible = "sii,43wvf1g";
 160                 backlight = <&backlight_display>;
 161                 dvdd-supply = <&reg_lcd_3v3>;
 162                 avdd-supply = <&reg_lcd_5v>;
 163
 164                 port {
 165                         panel_in: endpoint {
 166                                 remote-endpoint = <&display_out>;
 167                         };
 168                 };
 169         };
 170 };
 171
 172 &audmux {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_audmux>;
 175         status = "okay";
 176 };
 177
 178 &fec1 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_enet1>;
 181         phy-supply = <&reg_enet_3v3>;
 182         phy-mode = "rgmii";
 183         phy-handle = <&ethphy1>;
 184         phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
 185         status = "okay";
 186
 187         mdio {
 188                 #address-cells = <1>;
 189                 #size-cells = <0>;
 190
 191                 ethphy1: ethernet-phy@1 {
 192                         reg = <1>;
 193                 };
 194
 195                 ethphy2: ethernet-phy@2 {
 196                         reg = <2>;
 197                 };
 198         };
 199 };
 200
 201 &fec2 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_enet2>;
 204         phy-mode = "rgmii";
 205         phy-handle = <&ethphy2>;
 206         status = "okay";
 207 };
 208
 209 &i2c3 {
 210         clock-frequency = <100000>;
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_i2c3>;
 213         status = "okay";
 214 };
 215
 216 &i2c4 {
 217         clock-frequency = <100000>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_i2c4>;
 220         status = "okay";
 221
 222         codec: wm8962@1a {
 223                 compatible = "wlf,wm8962";
 224                 reg = <0x1a>;
 225                 clocks = <&clks IMX6SX_CLK_AUDIO>;
 226                 DCVDD-supply = <&vgen4_reg>;
 227                 DBVDD-supply = <&vgen4_reg>;
 228                 AVDD-supply = <&vgen4_reg>;
 229                 CPVDD-supply = <&vgen4_reg>;
 230                 MICVDD-supply = <&vgen3_reg>;
 231                 PLLVDD-supply = <&vgen4_reg>;
 232                 SPKVDD1-supply = <&reg_psu_5v>;
 233                 SPKVDD2-supply = <&reg_psu_5v>;
 234         };
 235 };
 236
 237 &pcie {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pinctrl_pcie>;
 240         reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
 241         vpcie-supply = <&reg_pcie_gpio>;
 242         status = "okay";
 243 };
 244
 245 &lcdif1 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_lcd>;
 248         status = "okay";
 249
 250         port {
 251                 display_out: endpoint {
 252                         remote-endpoint = <&panel_in>;
 253                 };
 254         };
 255 };
 256
 257 &pwm3 {
 258         pinctrl-names = "default";
 259         pinctrl-0 = <&pinctrl_pwm3>;
 260         status = "okay";
 261 };
 262
 263 &snvs_poweroff {
 264         status = "okay";
 265 };
 266
 267 &sai1 {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_sai1>;
 270         status = "disabled";
 271 };
 272
 273 &ssi2 {
 274         status = "okay";
 275 };
 276
 277 &uart1 {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_uart1>;
 280         status = "okay";
 281 };
 282
 283 &uart5 { /* for bluetooth */
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_uart5>;
 286         uart-has-rtscts;
 287         status = "okay";
 288 };
 289
 290 &usbotg1 {
 291         vbus-supply = <&reg_usb_otg1_vbus>;
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 294         status = "okay";
 295 };
 296
 297 &usbotg2 {
 298         vbus-supply = <&reg_usb_otg2_vbus>;
 299         dr_mode = "host";
 300         status = "okay";
 301 };
 302
 303 &usbphy1 {
 304         fsl,tx-d-cal = <106>;
 305 };
 306
 307 &usbphy2 {
 308         fsl,tx-d-cal = <106>;
 309 };
 310
 311 &usdhc2 {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&pinctrl_usdhc2>;
 314         non-removable;
 315         no-1-8-v;
 316         keep-power-in-suspend;
 317         wakeup-source;
 318         status = "okay";
 319 };
 320
 321 &usdhc3 {
 322         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 323         pinctrl-0 = <&pinctrl_usdhc3>;
 324         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 325         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 326         bus-width = <8>;
 327         cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 328         wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 329         keep-power-in-suspend;
 330         wakeup-source;
 331         vmmc-supply = <&vcc_sd3>;
 332         status = "okay";
 333 };
 334
 335 &usdhc4 {
 336         pinctrl-names = "default";
 337         pinctrl-0 = <&pinctrl_usdhc4>;
 338         cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
 339         wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
 340         status = "okay";
 341 };
 342
 343 &wdog1 {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_wdog>;
 346         fsl,ext-reset-output;
 347 };
 348
 349 &iomuxc {
 350         imx6x-sdb {
 351                 pinctrl_audmux: audmuxgrp {
 352                         fsl,pins = <
 353                                 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
 354                                 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
 355                                 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
 356                                 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
 357                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 358                         >;
 359                 };
 360
 361                 pinctrl_enet1: enet1grp {
 362                         fsl,pins = <
 363                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 364                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 365                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
 366                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 367                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 368                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 369                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 370                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 371                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 372                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 373                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 374                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 375                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 376                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 377                                 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
 378                                 /* phy reset */
 379                                 MX6SX_PAD_ENET2_CRS__GPIO2_IO_7         0x10b0
 380                         >;
 381                 };
 382
 383                 pinctrl_enet_3v3: enet3v3grp {
 384                         fsl,pins = <
 385                                 MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
 386                         >;
 387                 };
 388
 389                 pinctrl_enet2: enet2grp {
 390                         fsl,pins = <
 391                                 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 392                                 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 393                                 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 394                                 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 395                                 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 396                                 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 397                                 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 398                                 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 399                                 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 400                                 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 401                                 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 402                                 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 403                         >;
 404                 };
 405
 406                 pinctrl_gpio_keys: gpio_keysgrp {
 407                         fsl,pins = <
 408                                 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 409                                 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 410                         >;
 411                 };
 412
 413                 pinctrl_i2c1: i2c1grp {
 414                         fsl,pins = <
 415                                 MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
 416                                 MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
 417                         >;
 418                 };
 419
 420                 pinctrl_i2c3: i2c3grp {
 421                         fsl,pins = <
 422                                 MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
 423                                 MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
 424                         >;
 425                 };
 426
 427                 pinctrl_i2c4: i2c4grp {
 428                         fsl,pins = <
 429                                 MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
 430                                 MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
 431                         >;
 432                 };
 433
 434                 pinctrl_lcd: lcdgrp {
 435                         fsl,pins = <
 436                                 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
 437                                 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
 438                                 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
 439                                 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
 440                                 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
 441                                 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
 442                                 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
 443                                 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
 444                                 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
 445                                 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
 446                                 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
 447                                 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
 448                                 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
 449                                 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
 450                                 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
 451                                 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
 452                                 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
 453                                 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
 454                                 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
 455                                 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
 456                                 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
 457                                 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
 458                                 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
 459                                 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
 460                                 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
 461                                 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
 462                                 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
 463                                 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
 464                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
 465                         >;
 466                 };
 467
 468                 pinctrl_pcie: pciegrp {
 469                         fsl,pins = <
 470                                 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
 471                         >;
 472                 };
 473
 474                 pinctrl_pcie_reg: pciereggrp {
 475                         fsl,pins = <
 476                                 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
 477                         >;
 478                 };
 479
 480                 pinctrl_peri_3v3: peri3v3grp {
 481                         fsl,pins = <
 482                                 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
 483                         >;
 484                 };
 485
 486                 pinctrl_pwm3: pwm3grp-1 {
 487                         fsl,pins = <
 488                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
 489                         >;
 490                 };
 491
 492                 pinctrl_qspi2: qspi2grp {
 493                         fsl,pins = <
 494                                 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
 495                                 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
 496                                 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
 497                                 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
 498                                 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
 499                                 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
 500                                 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
 501                                 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
 502                                 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
 503                                 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
 504                                 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
 505                                 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
 506                         >;
 507                 };
 508
 509                 pinctrl_vcc_sd3: vccsd3grp {
 510                         fsl,pins = <
 511                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 512                         >;
 513                 };
 514
 515                 pinctrl_sai1: sai1grp {
 516                         fsl,pins = <
 517                                 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK      0x130b0
 518                                 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC      0x130b0
 519                                 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0     0x120b0
 520                                 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0     0x130b0
 521                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 522                         >;
 523                 };
 524
 525                 pinctrl_uart1: uart1grp {
 526                         fsl,pins = <
 527                                 MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 528                                 MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 529                         >;
 530                 };
 531
 532                 pinctrl_uart5: uart5grp {
 533                         fsl,pins = <
 534                                 MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
 535                                 MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
 536                                 MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
 537                                 MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
 538                         >;
 539                 };
 540
 541                 pinctrl_usb_otg1: usbotg1grp {
 542                         fsl,pins = <
 543                                 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 544                         >;
 545                 };
 546
 547                 pinctrl_usb_otg1_id: usbotg1idgrp {
 548                         fsl,pins = <
 549                                 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 550                         >;
 551                 };
 552
 553                 pinctrl_usb_otg2: usbot2ggrp {
 554                         fsl,pins = <
 555                                 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
 556                         >;
 557                 };
 558
 559                 pinctrl_usdhc2: usdhc2grp {
 560                         fsl,pins = <
 561                                 MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 562                                 MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 563                                 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 564                                 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 565                                 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 566                                 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 567                         >;
 568                 };
 569
 570                 pinctrl_usdhc3: usdhc3grp {
 571                         fsl,pins = <
 572                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
 573                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
 574                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
 575                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
 576                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
 577                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
 578                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
 579                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
 580                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
 581                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
 582                                 MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
 583                                 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
 584                         >;
 585                 };
 586
 587                 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
 588                         fsl,pins = <
 589                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
 590                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
 591                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
 592                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
 593                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
 594                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
 595                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
 596                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
 597                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
 598                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
 599                         >;
 600                 };
 601
 602                 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
 603                         fsl,pins = <
 604                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
 605                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
 606                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
 607                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
 608                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
 609                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
 610                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
 611                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
 612                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
 613                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
 614                         >;
 615                 };
 616
 617                 pinctrl_usdhc4: usdhc4grp {
 618                         fsl,pins = <
 619                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
 620                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
 621                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
 622                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
 623                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
 624                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
 625                                 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
 626                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
 627                         >;
 628                 };
 629
 630                 pinctrl_wdog: wdoggrp {
 631                         fsl,pins = <
 632                                 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
 633                         >;
 634                 };
 635         };
 636 };