arch/arm/boot/dts/imx6sx-sabreauto.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2014 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6
   7 #include "imx6sx.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX6 SoloX Sabre Auto Board";
  11         compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
  12
  13         memory@80000000 {
  14                 device_type = "memory";
  15                 reg = <0x80000000 0x80000000>;
  16         };
  17
  18         leds {
  19                 compatible = "gpio-leds";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_led>;
  22
  23                 user {
  24                         label = "debug";
  25                         gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
  26                         linux,default-trigger = "heartbeat";
  27                 };
  28         };
  29
  30         vcc_sd3: regulator-vcc-sd3 {
  31                 compatible = "regulator-fixed";
  32                 pinctrl-names = "default";
  33                 pinctrl-0 = <&pinctrl_vcc_sd3>;
  34                 regulator-name = "VCC_SD3";
  35                 regulator-min-microvolt = <3000000>;
  36                 regulator-max-microvolt = <3000000>;
  37                 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  38                 enable-active-high;
  39         };
  40 };
  41
  42 &anaclk2 {
  43         clock-frequency = <24576000>;
  44 };
  45
  46 &fec1 {
  47         pinctrl-names = "default";
  48         pinctrl-0 = <&pinctrl_enet1>;
  49         phy-mode = "rgmii";
  50         phy-handle = <&ethphy1>;
  51         fsl,magic-packet;
  52         status = "okay";
  53
  54         mdio {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 ethphy0: ethernet-phy@0 {
  59                         compatible = "ethernet-phy-ieee802.3-c22";
  60                         reg = <0>;
  61                 };
  62
  63                 ethphy1: ethernet-phy@1 {
  64                         compatible = "ethernet-phy-ieee802.3-c22";
  65                         reg = <1>;
  66                 };
  67         };
  68 };
  69
  70 &fec2 {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_enet2>;
  73         phy-mode = "rgmii";
  74         phy-handle = <&ethphy0>;
  75         fsl,magic-packet;
  76         status = "okay";
  77 };
  78
  79 &uart1 {
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_uart1>;
  82         status = "okay";
  83 };
  84
  85 &usdhc3 {
  86         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  87         pinctrl-0 = <&pinctrl_usdhc3>;
  88         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  89         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  90         bus-width = <8>;
  91         cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
  92         wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  93         keep-power-in-suspend;
  94         wakeup-source;
  95         vmmc-supply = <&vcc_sd3>;
  96         status = "okay";
  97 };
  98
  99 &usdhc4 {
 100         pinctrl-names = "default";
 101         pinctrl-0 = <&pinctrl_usdhc4>;
 102         bus-width = <8>;
 103         cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
 104         no-1-8-v;
 105         keep-power-in-suspend;
 106         wakeup-source;
 107         status = "okay";
 108 };
 109
 110 &iomuxc {
 111         pinctrl_egalax_int: egalax-intgrp {
 112                 fsl,pins = <
 113                         MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22      0x10b0
 114                 >;
 115         };
 116
 117         pinctrl_enet1: enet1grp {
 118                 fsl,pins = <
 119                         MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 120                         MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 121                         MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
 122                         MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 123                         MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 124                         MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 125                         MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 126                         MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 127                         MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 128                         MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 129                         MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 130                         MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 131                         MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 132                         MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 133                 >;
 134         };
 135
 136         pinctrl_enet2: enet2grp {
 137                 fsl,pins = <
 138                         MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 139                         MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 140                         MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 141                         MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 142                         MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 143                         MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 144                         MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 145                         MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 146                         MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 147                         MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 148                         MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 149                         MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 150                 >;
 151         };
 152
 153         pinctrl_i2c2: i2c2grp {
 154                 fsl,pins = <
 155                         MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
 156                         MX6SX_PAD_GPIO1_IO02__I2C2_SCL          0x4001b8b1
 157                 >;
 158         };
 159
 160         pinctrl_i2c3: i2c3grp {
 161                 fsl,pins = <
 162                         MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
 163                         MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
 164                 >;
 165         };
 166
 167         pinctrl_led: ledgrp {
 168                 fsl,pins = <
 169                         MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
 170                 >;
 171         };
 172
 173         pinctrl_uart1: uart1grp {
 174                 fsl,pins = <
 175                         MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 176                         MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 177                 >;
 178         };
 179
 180         pinctrl_usdhc3: usdhc3grp {
 181                 fsl,pins = <
 182                         MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
 183                         MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
 184                         MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
 185                         MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
 186                         MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
 187                         MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
 188                         MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
 189                         MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
 190                         MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
 191                         MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
 192                         MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
 193                         MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
 194                 >;
 195         };
 196
 197         pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
 198                 fsl,pins = <
 199                         MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
 200                         MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
 201                         MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
 202                         MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
 203                         MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
 204                         MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
 205                         MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
 206                         MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
 207                         MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
 208                         MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
 209                 >;
 210         };
 211
 212         pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
 213                 fsl,pins = <
 214                         MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
 215                         MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
 216                         MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
 217                         MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
 218                         MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
 219                         MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
 220                         MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
 221                         MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
 222                         MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
 223                         MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
 224                 >;
 225         };
 226
 227         pinctrl_usdhc4: usdhc4grp {
 228                 fsl,pins = <
 229                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
 230                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
 231                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
 232                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
 233                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
 234                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
 235                         MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
 236                         MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
 237                 >;
 238         };
 239
 240         pinctrl_vcc_sd3: vccsd3grp {
 241                 fsl,pins = <
 242                         MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 243                 >;
 244         };
 245
 246         pinctrl_wdog: wdoggrp {
 247                 fsl,pins = <
 248                         MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY    0x30b0
 249                 >;
 250         };
 251 };
 252
 253 &i2c2 {
 254         clock-frequency = <100000>;
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_i2c2>;
 257         status = "okay";
 258
 259         touchscreen@4 {
 260                 compatible = "eeti,egalax_ts";
 261                 reg = <0x04>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&pinctrl_egalax_int>;
 264                 interrupt-parent = <&gpio6>;
 265                 interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
 266                 wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
 267         };
 268
 269         pfuze100: pmic@8 {
 270                 compatible = "fsl,pfuze100";
 271                 reg = <0x08>;
 272
 273                 regulators {
 274                         sw1a_reg: sw1ab {
 275                                 regulator-min-microvolt = <300000>;
 276                                 regulator-max-microvolt = <1875000>;
 277                                 regulator-boot-on;
 278                                 regulator-always-on;
 279                                 regulator-ramp-delay = <6250>;
 280                         };
 281
 282                         sw1c_reg: sw1c {
 283                                 regulator-min-microvolt = <300000>;
 284                                 regulator-max-microvolt = <1875000>;
 285                                 regulator-boot-on;
 286                                 regulator-always-on;
 287                                 regulator-ramp-delay = <6250>;
 288                         };
 289
 290                         sw2_reg: sw2 {
 291                                 regulator-min-microvolt = <800000>;
 292                                 regulator-max-microvolt = <3300000>;
 293                                 regulator-boot-on;
 294                                 regulator-always-on;
 295                         };
 296
 297                         sw3a_reg: sw3a {
 298                                 regulator-min-microvolt = <400000>;
 299                                 regulator-max-microvolt = <1975000>;
 300                                 regulator-boot-on;
 301                                 regulator-always-on;
 302                         };
 303
 304                         sw3b_reg: sw3b {
 305                                 regulator-min-microvolt = <400000>;
 306                                 regulator-max-microvolt = <1975000>;
 307                                 regulator-boot-on;
 308                                 regulator-always-on;
 309                         };
 310
 311                         sw4_reg: sw4 {
 312                                 regulator-min-microvolt = <800000>;
 313                                 regulator-max-microvolt = <3300000>;
 314                                 regulator-always-on;
 315                         };
 316
 317                         swbst_reg: swbst {
 318                                 regulator-min-microvolt = <5000000>;
 319                                 regulator-max-microvolt = <5150000>;
 320                         };
 321
 322                         snvs_reg: vsnvs {
 323                                 regulator-min-microvolt = <1000000>;
 324                                 regulator-max-microvolt = <3000000>;
 325                                 regulator-boot-on;
 326                                 regulator-always-on;
 327                         };
 328
 329                         vref_reg: vrefddr {
 330                                 regulator-boot-on;
 331                                 regulator-always-on;
 332                         };
 333
 334                         vgen1_reg: vgen1 {
 335                                 regulator-min-microvolt = <800000>;
 336                                 regulator-max-microvolt = <1550000>;
 337                                 regulator-always-on;
 338                         };
 339
 340                         vgen2_reg: vgen2 {
 341                                 regulator-min-microvolt = <800000>;
 342                                 regulator-max-microvolt = <1550000>;
 343                         };
 344
 345                         vgen3_reg: vgen3 {
 346                                 regulator-min-microvolt = <1800000>;
 347                                 regulator-max-microvolt = <3300000>;
 348                                 regulator-always-on;
 349                         };
 350
 351                         vgen4_reg: vgen4 {
 352                                 regulator-min-microvolt = <1800000>;
 353                                 regulator-max-microvolt = <3300000>;
 354                                 regulator-always-on;
 355                         };
 356
 357                         vgen5_reg: vgen5 {
 358                                 regulator-min-microvolt = <1800000>;
 359                                 regulator-max-microvolt = <3300000>;
 360                                 regulator-always-on;
 361                         };
 362
 363                         vgen6_reg: vgen6 {
 364                                 regulator-min-microvolt = <1800000>;
 365                                 regulator-max-microvolt = <3300000>;
 366                                 regulator-always-on;
 367                         };
 368                 };
 369         };
 370
 371         max7322: gpio@68 {
 372                 compatible = "maxim,max7322";
 373                 reg = <0x68>;
 374                 gpio-controller;
 375                 #gpio-cells = <2>;
 376         };
 377 };
 378
 379 &i2c3 {
 380         clock-frequency = <100000>;
 381         pinctrl-names = "default";
 382         pinctrl-0 = <&pinctrl_i2c3>;
 383         status = "okay";
 384
 385         max7310_a: gpio@30 {
 386                 compatible = "maxim,max7310";
 387                 reg = <0x30>;
 388                 gpio-controller;
 389                 #gpio-cells = <2>;
 390         };
 391
 392         max7310_b: gpio@32 {
 393                 compatible = "maxim,max7310";
 394                 reg = <0x32>;
 395                 gpio-controller;
 396                 #gpio-cells = <2>;
 397         };
 398 };
 399
 400 &wdog1 {
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_wdog>;
 403         fsl,ext-reset-output;
 404 };