arch/arm/boot/dts/imx6sl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6sl-pinfunc.h"
   7 #include <dt-bindings/clock/imx6sl-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          */
  17         chosen {};
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 spi0 = &ecspi1;
  32                 spi1 = &ecspi2;
  33                 spi2 = &ecspi3;
  34                 spi3 = &ecspi4;
  35                 usbphy0 = &usbphy1;
  36                 usbphy1 = &usbphy2;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu@0 {
  44                         compatible = "arm,cortex-a9";
  45                         device_type = "cpu";
  46                         reg = <0x0>;
  47                         next-level-cache = <&L2>;
  48                         operating-points = <
  49                                 /* kHz    uV */
  50                                 996000  1275000
  51                                 792000  1175000
  52                                 396000  975000
  53                         >;
  54                         fsl,soc-operating-points = <
  55                                 /* ARM kHz      SOC-PU uV */
  56                                 996000          1225000
  57                                 792000          1175000
  58                                 396000          1175000
  59                         >;
  60                         clock-latency = <61036>; /* two CLK32 periods */
  61                         #cooling-cells = <2>;
  62                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  63                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  64                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  65                         clock-names = "arm", "pll2_pfd2_396m", "step",
  66                                       "pll1_sw", "pll1_sys";
  67                         arm-supply = <&reg_arm>;
  68                         pu-supply = <&reg_pu>;
  69                         soc-supply = <&reg_soc>;
  70                 };
  71         };
  72
  73         intc: interrupt-controller@a01000 {
  74                 compatible = "arm,cortex-a9-gic";
  75                 #interrupt-cells = <3>;
  76                 interrupt-controller;
  77                 reg = <0x00a01000 0x1000>,
  78                       <0x00a00100 0x100>;
  79                 interrupt-parent = <&intc>;
  80         };
  81
  82         clocks {
  83                 ckil {
  84                         compatible = "fixed-clock";
  85                         #clock-cells = <0>;
  86                         clock-frequency = <32768>;
  87                 };
  88
  89                 osc {
  90                         compatible = "fixed-clock";
  91                         #clock-cells = <0>;
  92                         clock-frequency = <24000000>;
  93                 };
  94         };
  95
  96         tempmon: tempmon {
  97                 compatible = "fsl,imx6q-tempmon";
  98                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
  99                 interrupt-parent = <&gpc>;
 100                 fsl,tempmon = <&anatop>;
 101                 fsl,tempmon-data = <&ocotp>;
 102                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 103         };
 104
 105         pmu {
 106                 compatible = "arm,cortex-a9-pmu";
 107                 interrupt-parent = <&gpc>;
 108                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 109         };
 110
 111         soc {
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 compatible = "simple-bus";
 115                 interrupt-parent = <&gpc>;
 116                 ranges;
 117
 118                 ocram: sram@900000 {
 119                         compatible = "mmio-sram";
 120                         reg = <0x00900000 0x20000>;
 121                         ranges = <0 0x00900000 0x20000>;
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 125                 };
 126
 127                 L2: l2-cache@a02000 {
 128                         compatible = "arm,pl310-cache";
 129                         reg = <0x00a02000 0x1000>;
 130                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 131                         cache-unified;
 132                         cache-level = <2>;
 133                         arm,tag-latency = <4 2 3>;
 134                         arm,data-latency = <4 2 3>;
 135                 };
 136
 137                 aips1: aips-bus@2000000 {
 138                         compatible = "fsl,aips-bus", "simple-bus";
 139                         #address-cells = <1>;
 140                         #size-cells = <1>;
 141                         reg = <0x02000000 0x100000>;
 142                         ranges;
 143
 144                         spba: spba-bus@2000000 {
 145                                 compatible = "fsl,spba-bus", "simple-bus";
 146                                 #address-cells = <1>;
 147                                 #size-cells = <1>;
 148                                 reg = <0x02000000 0x40000>;
 149                                 ranges;
 150
 151                                 spdif: spdif@2004000 {
 152                                         compatible = "fsl,imx6sl-spdif",
 153                                                 "fsl,imx35-spdif";
 154                                         reg = <0x02004000 0x4000>;
 155                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 156                                         dmas = <&sdma 14 18 0>,
 157                                                 <&sdma 15 18 0>;
 158                                         dma-names = "rx", "tx";
 159                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 160                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 161                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 162                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 163                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 164                                         clock-names = "core", "rxtx0",
 165                                                 "rxtx1", "rxtx2",
 166                                                 "rxtx3", "rxtx4",
 167                                                 "rxtx5", "rxtx6",
 168                                                 "rxtx7", "spba";
 169                                         status = "disabled";
 170                                 };
 171
 172                                 ecspi1: ecspi@2008000 {
 173                                         #address-cells = <1>;
 174                                         #size-cells = <0>;
 175                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 176                                         reg = <0x02008000 0x4000>;
 177                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 178                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 179                                                  <&clks IMX6SL_CLK_ECSPI1>;
 180                                         clock-names = "ipg", "per";
 181                                         status = "disabled";
 182                                 };
 183
 184                                 ecspi2: ecspi@200c000 {
 185                                         #address-cells = <1>;
 186                                         #size-cells = <0>;
 187                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 188                                         reg = <0x0200c000 0x4000>;
 189                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 190                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 191                                                  <&clks IMX6SL_CLK_ECSPI2>;
 192                                         clock-names = "ipg", "per";
 193                                         status = "disabled";
 194                                 };
 195
 196                                 ecspi3: ecspi@2010000 {
 197                                         #address-cells = <1>;
 198                                         #size-cells = <0>;
 199                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 200                                         reg = <0x02010000 0x4000>;
 201                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 202                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 203                                                  <&clks IMX6SL_CLK_ECSPI3>;
 204                                         clock-names = "ipg", "per";
 205                                         status = "disabled";
 206                                 };
 207
 208                                 ecspi4: ecspi@2014000 {
 209                                         #address-cells = <1>;
 210                                         #size-cells = <0>;
 211                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 212                                         reg = <0x02014000 0x4000>;
 213                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 214                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 215                                                  <&clks IMX6SL_CLK_ECSPI4>;
 216                                         clock-names = "ipg", "per";
 217                                         status = "disabled";
 218                                 };
 219
 220                                 uart5: serial@2018000 {
 221                                         compatible = "fsl,imx6sl-uart",
 222                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 223                                         reg = <0x02018000 0x4000>;
 224                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 225                                         clocks = <&clks IMX6SL_CLK_UART>,
 226                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 227                                         clock-names = "ipg", "per";
 228                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 229                                         dma-names = "rx", "tx";
 230                                         status = "disabled";
 231                                 };
 232
 233                                 uart1: serial@2020000 {
 234                                         compatible = "fsl,imx6sl-uart",
 235                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 236                                         reg = <0x02020000 0x4000>;
 237                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 238                                         clocks = <&clks IMX6SL_CLK_UART>,
 239                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 240                                         clock-names = "ipg", "per";
 241                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 242                                         dma-names = "rx", "tx";
 243                                         status = "disabled";
 244                                 };
 245
 246                                 uart2: serial@2024000 {
 247                                         compatible = "fsl,imx6sl-uart",
 248                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 249                                         reg = <0x02024000 0x4000>;
 250                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 251                                         clocks = <&clks IMX6SL_CLK_UART>,
 252                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 253                                         clock-names = "ipg", "per";
 254                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 255                                         dma-names = "rx", "tx";
 256                                         status = "disabled";
 257                                 };
 258
 259                                 ssi1: ssi@2028000 {
 260                                         #sound-dai-cells = <0>;
 261                                         compatible = "fsl,imx6sl-ssi",
 262                                                         "fsl,imx51-ssi";
 263                                         reg = <0x02028000 0x4000>;
 264                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 265                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 266                                                  <&clks IMX6SL_CLK_SSI1>;
 267                                         clock-names = "ipg", "baud";
 268                                         dmas = <&sdma 37 1 0>,
 269                                                <&sdma 38 1 0>;
 270                                         dma-names = "rx", "tx";
 271                                         fsl,fifo-depth = <15>;
 272                                         status = "disabled";
 273                                 };
 274
 275                                 ssi2: ssi@202c000 {
 276                                         #sound-dai-cells = <0>;
 277                                         compatible = "fsl,imx6sl-ssi",
 278                                                         "fsl,imx51-ssi";
 279                                         reg = <0x0202c000 0x4000>;
 280                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 281                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 282                                                  <&clks IMX6SL_CLK_SSI2>;
 283                                         clock-names = "ipg", "baud";
 284                                         dmas = <&sdma 41 1 0>,
 285                                                <&sdma 42 1 0>;
 286                                         dma-names = "rx", "tx";
 287                                         fsl,fifo-depth = <15>;
 288                                         status = "disabled";
 289                                 };
 290
 291                                 ssi3: ssi@2030000 {
 292                                         #sound-dai-cells = <0>;
 293                                         compatible = "fsl,imx6sl-ssi",
 294                                                         "fsl,imx51-ssi";
 295                                         reg = <0x02030000 0x4000>;
 296                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 297                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 298                                                  <&clks IMX6SL_CLK_SSI3>;
 299                                         clock-names = "ipg", "baud";
 300                                         dmas = <&sdma 45 1 0>,
 301                                                <&sdma 46 1 0>;
 302                                         dma-names = "rx", "tx";
 303                                         fsl,fifo-depth = <15>;
 304                                         status = "disabled";
 305                                 };
 306
 307                                 uart3: serial@2034000 {
 308                                         compatible = "fsl,imx6sl-uart",
 309                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 310                                         reg = <0x02034000 0x4000>;
 311                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 312                                         clocks = <&clks IMX6SL_CLK_UART>,
 313                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 314                                         clock-names = "ipg", "per";
 315                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 316                                         dma-names = "rx", "tx";
 317                                         status = "disabled";
 318                                 };
 319
 320                                 uart4: serial@2038000 {
 321                                         compatible = "fsl,imx6sl-uart",
 322                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 323                                         reg = <0x02038000 0x4000>;
 324                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 325                                         clocks = <&clks IMX6SL_CLK_UART>,
 326                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 327                                         clock-names = "ipg", "per";
 328                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 329                                         dma-names = "rx", "tx";
 330                                         status = "disabled";
 331                                 };
 332                         };
 333
 334                         pwm1: pwm@2080000 {
 335                                 #pwm-cells = <2>;
 336                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 337                                 reg = <0x02080000 0x4000>;
 338                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 339                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 340                                          <&clks IMX6SL_CLK_PWM1>;
 341                                 clock-names = "ipg", "per";
 342                         };
 343
 344                         pwm2: pwm@2084000 {
 345                                 #pwm-cells = <2>;
 346                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 347                                 reg = <0x02084000 0x4000>;
 348                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 349                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 350                                          <&clks IMX6SL_CLK_PWM2>;
 351                                 clock-names = "ipg", "per";
 352                         };
 353
 354                         pwm3: pwm@2088000 {
 355                                 #pwm-cells = <2>;
 356                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x02088000 0x4000>;
 358                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 360                                          <&clks IMX6SL_CLK_PWM3>;
 361                                 clock-names = "ipg", "per";
 362                         };
 363
 364                         pwm4: pwm@208c000 {
 365                                 #pwm-cells = <2>;
 366                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 367                                 reg = <0x0208c000 0x4000>;
 368                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 369                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 370                                          <&clks IMX6SL_CLK_PWM4>;
 371                                 clock-names = "ipg", "per";
 372                         };
 373
 374                         gpt: gpt@2098000 {
 375                                 compatible = "fsl,imx6sl-gpt";
 376                                 reg = <0x02098000 0x4000>;
 377                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 378                                 clocks = <&clks IMX6SL_CLK_GPT>,
 379                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 380                                 clock-names = "ipg", "per";
 381                         };
 382
 383                         gpio1: gpio@209c000 {
 384                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 385                                 reg = <0x0209c000 0x4000>;
 386                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 387                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 388                                 gpio-controller;
 389                                 #gpio-cells = <2>;
 390                                 interrupt-controller;
 391                                 #interrupt-cells = <2>;
 392                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 393                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 394                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 395                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 396                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 397                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 398                         };
 399
 400                         gpio2: gpio@20a0000 {
 401                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 402                                 reg = <0x020a0000 0x4000>;
 403                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 404                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 405                                 gpio-controller;
 406                                 #gpio-cells = <2>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <2>;
 409                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 410                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 411                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 412                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 413                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 414                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 415                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 416                         };
 417
 418                         gpio3: gpio@20a4000 {
 419                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 420                                 reg = <0x020a4000 0x4000>;
 421                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 423                                 gpio-controller;
 424                                 #gpio-cells = <2>;
 425                                 interrupt-controller;
 426                                 #interrupt-cells = <2>;
 427                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 428                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 429                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 430                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 431                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 432                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 433                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 434                                               <&iomuxc 31 102 1>;
 435                         };
 436
 437                         gpio4: gpio@20a8000 {
 438                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 439                                 reg = <0x020a8000 0x4000>;
 440                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 441                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 442                                 gpio-controller;
 443                                 #gpio-cells = <2>;
 444                                 interrupt-controller;
 445                                 #interrupt-cells = <2>;
 446                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 447                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 448                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 449                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 450                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 451                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 452                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 453                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 454                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 455                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 456                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 457                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 458                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 459                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 460                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 461                         };
 462
 463                         gpio5: gpio@20ac000 {
 464                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x020ac000 0x4000>;
 466                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 468                                 gpio-controller;
 469                                 #gpio-cells = <2>;
 470                                 interrupt-controller;
 471                                 #interrupt-cells = <2>;
 472                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 473                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 474                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 475                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 476                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 477                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 478                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 479                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 480                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 481                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 482                                               <&iomuxc 21 161 1>;
 483                         };
 484
 485                         kpp: kpp@20b8000 {
 486                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 487                                 reg = <0x020b8000 0x4000>;
 488                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 489                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 490                                 status = "disabled";
 491                         };
 492
 493                         wdog1: wdog@20bc000 {
 494                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 495                                 reg = <0x020bc000 0x4000>;
 496                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 497                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 498                         };
 499
 500                         wdog2: wdog@20c0000 {
 501                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 502                                 reg = <0x020c0000 0x4000>;
 503                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 505                                 status = "disabled";
 506                         };
 507
 508                         clks: ccm@20c4000 {
 509                                 compatible = "fsl,imx6sl-ccm";
 510                                 reg = <0x020c4000 0x4000>;
 511                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 512                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 513                                 #clock-cells = <1>;
 514                         };
 515
 516                         anatop: anatop@20c8000 {
 517                                 compatible = "fsl,imx6sl-anatop",
 518                                              "fsl,imx6q-anatop",
 519                                              "syscon", "simple-bus";
 520                                 reg = <0x020c8000 0x1000>;
 521                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 522                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 523                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 524
 525                                 regulator-1p1 {
 526                                         compatible = "fsl,anatop-regulator";
 527                                         regulator-name = "vdd1p1";
 528                                         regulator-min-microvolt = <1000000>;
 529                                         regulator-max-microvolt = <1200000>;
 530                                         regulator-always-on;
 531                                         anatop-reg-offset = <0x110>;
 532                                         anatop-vol-bit-shift = <8>;
 533                                         anatop-vol-bit-width = <5>;
 534                                         anatop-min-bit-val = <4>;
 535                                         anatop-min-voltage = <800000>;
 536                                         anatop-max-voltage = <1375000>;
 537                                         anatop-enable-bit = <0>;
 538                                 };
 539
 540                                 regulator-3p0 {
 541                                         compatible = "fsl,anatop-regulator";
 542                                         regulator-name = "vdd3p0";
 543                                         regulator-min-microvolt = <2800000>;
 544                                         regulator-max-microvolt = <3150000>;
 545                                         regulator-always-on;
 546                                         anatop-reg-offset = <0x120>;
 547                                         anatop-vol-bit-shift = <8>;
 548                                         anatop-vol-bit-width = <5>;
 549                                         anatop-min-bit-val = <0>;
 550                                         anatop-min-voltage = <2625000>;
 551                                         anatop-max-voltage = <3400000>;
 552                                         anatop-enable-bit = <0>;
 553                                 };
 554
 555                                 regulator-2p5 {
 556                                         compatible = "fsl,anatop-regulator";
 557                                         regulator-name = "vdd2p5";
 558                                         regulator-min-microvolt = <2250000>;
 559                                         regulator-max-microvolt = <2750000>;
 560                                         regulator-always-on;
 561                                         anatop-reg-offset = <0x130>;
 562                                         anatop-vol-bit-shift = <8>;
 563                                         anatop-vol-bit-width = <5>;
 564                                         anatop-min-bit-val = <0>;
 565                                         anatop-min-voltage = <2100000>;
 566                                         anatop-max-voltage = <2850000>;
 567                                         anatop-enable-bit = <0>;
 568                                 };
 569
 570                                 reg_arm: regulator-vddcore {
 571                                         compatible = "fsl,anatop-regulator";
 572                                         regulator-name = "vddarm";
 573                                         regulator-min-microvolt = <725000>;
 574                                         regulator-max-microvolt = <1450000>;
 575                                         regulator-always-on;
 576                                         anatop-reg-offset = <0x140>;
 577                                         anatop-vol-bit-shift = <0>;
 578                                         anatop-vol-bit-width = <5>;
 579                                         anatop-delay-reg-offset = <0x170>;
 580                                         anatop-delay-bit-shift = <24>;
 581                                         anatop-delay-bit-width = <2>;
 582                                         anatop-min-bit-val = <1>;
 583                                         anatop-min-voltage = <725000>;
 584                                         anatop-max-voltage = <1450000>;
 585                                 };
 586
 587                                 reg_pu: regulator-vddpu {
 588                                         compatible = "fsl,anatop-regulator";
 589                                         regulator-name = "vddpu";
 590                                         regulator-min-microvolt = <725000>;
 591                                         regulator-max-microvolt = <1450000>;
 592                                         regulator-always-on;
 593                                         anatop-reg-offset = <0x140>;
 594                                         anatop-vol-bit-shift = <9>;
 595                                         anatop-vol-bit-width = <5>;
 596                                         anatop-delay-reg-offset = <0x170>;
 597                                         anatop-delay-bit-shift = <26>;
 598                                         anatop-delay-bit-width = <2>;
 599                                         anatop-min-bit-val = <1>;
 600                                         anatop-min-voltage = <725000>;
 601                                         anatop-max-voltage = <1450000>;
 602                                 };
 603
 604                                 reg_soc: regulator-vddsoc {
 605                                         compatible = "fsl,anatop-regulator";
 606                                         regulator-name = "vddsoc";
 607                                         regulator-min-microvolt = <725000>;
 608                                         regulator-max-microvolt = <1450000>;
 609                                         regulator-always-on;
 610                                         anatop-reg-offset = <0x140>;
 611                                         anatop-vol-bit-shift = <18>;
 612                                         anatop-vol-bit-width = <5>;
 613                                         anatop-delay-reg-offset = <0x170>;
 614                                         anatop-delay-bit-shift = <28>;
 615                                         anatop-delay-bit-width = <2>;
 616                                         anatop-min-bit-val = <1>;
 617                                         anatop-min-voltage = <725000>;
 618                                         anatop-max-voltage = <1450000>;
 619                                 };
 620                         };
 621
 622                         usbphy1: usbphy@20c9000 {
 623                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 624                                 reg = <0x020c9000 0x1000>;
 625                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 626                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 627                                 fsl,anatop = <&anatop>;
 628                         };
 629
 630                         usbphy2: usbphy@20ca000 {
 631                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 632                                 reg = <0x020ca000 0x1000>;
 633                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 634                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 635                                 fsl,anatop = <&anatop>;
 636                         };
 637
 638                         snvs: snvs@20cc000 {
 639                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 640                                 reg = <0x020cc000 0x4000>;
 641
 642                                 snvs_rtc: snvs-rtc-lp {
 643                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 644                                         regmap = <&snvs>;
 645                                         offset = <0x34>;
 646                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 647                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 648                                 };
 649
 650                                 snvs_poweroff: snvs-poweroff {
 651                                         compatible = "syscon-poweroff";
 652                                         regmap = <&snvs>;
 653                                         offset = <0x38>;
 654                                         value = <0x60>;
 655                                         mask = <0x60>;
 656                                         status = "disabled";
 657                                 };
 658                         };
 659
 660                         epit1: epit@20d0000 {
 661                                 reg = <0x020d0000 0x4000>;
 662                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 663                         };
 664
 665                         epit2: epit@20d4000 {
 666                                 reg = <0x020d4000 0x4000>;
 667                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 668                         };
 669
 670                         src: src@20d8000 {
 671                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 672                                 reg = <0x020d8000 0x4000>;
 673                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 674                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 675                                 #reset-cells = <1>;
 676                         };
 677
 678                         gpc: gpc@20dc000 {
 679                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 680                                 reg = <0x020dc000 0x4000>;
 681                                 interrupt-controller;
 682                                 #interrupt-cells = <3>;
 683                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 684                                 interrupt-parent = <&intc>;
 685                                 clocks = <&clks IMX6SL_CLK_IPG>;
 686                                 clock-names = "ipg";
 687
 688                                 pgc {
 689                                         #address-cells = <1>;
 690                                         #size-cells = <0>;
 691
 692                                         power-domain@0 {
 693                                                 reg = <0>;
 694                                                 #power-domain-cells = <0>;
 695                                         };
 696
 697                                         pd_pu: power-domain@1 {
 698                                                 reg = <1>;
 699                                                 #power-domain-cells = <0>;
 700                                                 power-supply = <&reg_pu>;
 701                                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 702                                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 703                                         };
 704
 705                                         pd_disp: power-domain@2 {
 706                                                 reg = <2>;
 707                                                 #power-domain-cells = <0>;
 708                                                 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
 709                                                          <&clks IMX6SL_CLK_LCDIF_PIX>,
 710                                                          <&clks IMX6SL_CLK_EPDC_AXI>,
 711                                                          <&clks IMX6SL_CLK_EPDC_PIX>,
 712                                                          <&clks IMX6SL_CLK_PXP_AXI>;
 713                                         };
 714                                 };
 715                         };
 716
 717                         gpr: iomuxc-gpr@20e0000 {
 718                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 719                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 720                                 reg = <0x020e0000 0x38>;
 721                         };
 722
 723                         iomuxc: iomuxc@20e0000 {
 724                                 compatible = "fsl,imx6sl-iomuxc";
 725                                 reg = <0x020e0000 0x4000>;
 726                         };
 727
 728                         csi: csi@20e4000 {
 729                                 reg = <0x020e4000 0x4000>;
 730                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 731                         };
 732
 733                         spdc: spdc@20e8000 {
 734                                 reg = <0x020e8000 0x4000>;
 735                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 736                         };
 737
 738                         sdma: sdma@20ec000 {
 739                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 740                                 reg = <0x020ec000 0x4000>;
 741                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 742                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 743                                          <&clks IMX6SL_CLK_AHB>;
 744                                 clock-names = "ipg", "ahb";
 745                                 #dma-cells = <3>;
 746                                 /* imx6sl reuses imx6q sdma firmware */
 747                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 748                         };
 749
 750                         pxp: pxp@20f0000 {
 751                                 reg = <0x020f0000 0x4000>;
 752                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 753                         };
 754
 755                         epdc: epdc@20f4000 {
 756                                 reg = <0x020f4000 0x4000>;
 757                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 758                         };
 759
 760                         lcdif: lcdif@20f8000 {
 761                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 762                                 reg = <0x020f8000 0x4000>;
 763                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 764                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 765                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 766                                          <&clks IMX6SL_CLK_DUMMY>;
 767                                 clock-names = "pix", "axi", "disp_axi";
 768                                 status = "disabled";
 769                                 power-domains = <&pd_disp>;
 770                         };
 771
 772                         dcp: dcp@20fc000 {
 773                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 774                                 reg = <0x020fc000 0x4000>;
 775                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 776                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 777                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 778                         };
 779                 };
 780
 781                 aips2: aips-bus@2100000 {
 782                         compatible = "fsl,aips-bus", "simple-bus";
 783                         #address-cells = <1>;
 784                         #size-cells = <1>;
 785                         reg = <0x02100000 0x100000>;
 786                         ranges;
 787
 788                         usbotg1: usb@2184000 {
 789                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 790                                 reg = <0x02184000 0x200>;
 791                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 792                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 793                                 fsl,usbphy = <&usbphy1>;
 794                                 fsl,usbmisc = <&usbmisc 0>;
 795                                 ahb-burst-config = <0x0>;
 796                                 tx-burst-size-dword = <0x10>;
 797                                 rx-burst-size-dword = <0x10>;
 798                                 status = "disabled";
 799                         };
 800
 801                         usbotg2: usb@2184200 {
 802                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 803                                 reg = <0x02184200 0x200>;
 804                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 805                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 806                                 fsl,usbphy = <&usbphy2>;
 807                                 fsl,usbmisc = <&usbmisc 1>;
 808                                 ahb-burst-config = <0x0>;
 809                                 tx-burst-size-dword = <0x10>;
 810                                 rx-burst-size-dword = <0x10>;
 811                                 status = "disabled";
 812                         };
 813
 814                         usbh: usb@2184400 {
 815                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 816                                 reg = <0x02184400 0x200>;
 817                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 818                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 819                                 fsl,usbmisc = <&usbmisc 2>;
 820                                 dr_mode = "host";
 821                                 ahb-burst-config = <0x0>;
 822                                 tx-burst-size-dword = <0x10>;
 823                                 rx-burst-size-dword = <0x10>;
 824                                 status = "disabled";
 825                         };
 826
 827                         usbmisc: usbmisc@2184800 {
 828                                 #index-cells = <1>;
 829                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 830                                 reg = <0x02184800 0x200>;
 831                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 832                         };
 833
 834                         fec: ethernet@2188000 {
 835                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 836                                 reg = <0x02188000 0x4000>;
 837                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 838                                 clocks = <&clks IMX6SL_CLK_ENET>,
 839                                          <&clks IMX6SL_CLK_ENET_REF>;
 840                                 clock-names = "ipg", "ahb";
 841                                 status = "disabled";
 842                         };
 843
 844                         usdhc1: usdhc@2190000 {
 845                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 846                                 reg = <0x02190000 0x4000>;
 847                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 848                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 849                                          <&clks IMX6SL_CLK_USDHC1>,
 850                                          <&clks IMX6SL_CLK_USDHC1>;
 851                                 clock-names = "ipg", "ahb", "per";
 852                                 bus-width = <4>;
 853                                 status = "disabled";
 854                         };
 855
 856                         usdhc2: usdhc@2194000 {
 857                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 858                                 reg = <0x02194000 0x4000>;
 859                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 860                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 861                                          <&clks IMX6SL_CLK_USDHC2>,
 862                                          <&clks IMX6SL_CLK_USDHC2>;
 863                                 clock-names = "ipg", "ahb", "per";
 864                                 bus-width = <4>;
 865                                 status = "disabled";
 866                         };
 867
 868                         usdhc3: usdhc@2198000 {
 869                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 870                                 reg = <0x02198000 0x4000>;
 871                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 872                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 873                                          <&clks IMX6SL_CLK_USDHC3>,
 874                                          <&clks IMX6SL_CLK_USDHC3>;
 875                                 clock-names = "ipg", "ahb", "per";
 876                                 bus-width = <4>;
 877                                 status = "disabled";
 878                         };
 879
 880                         usdhc4: usdhc@219c000 {
 881                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 882                                 reg = <0x0219c000 0x4000>;
 883                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 885                                          <&clks IMX6SL_CLK_USDHC4>,
 886                                          <&clks IMX6SL_CLK_USDHC4>;
 887                                 clock-names = "ipg", "ahb", "per";
 888                                 bus-width = <4>;
 889                                 status = "disabled";
 890                         };
 891
 892                         i2c1: i2c@21a0000 {
 893                                 #address-cells = <1>;
 894                                 #size-cells = <0>;
 895                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 896                                 reg = <0x021a0000 0x4000>;
 897                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 898                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 899                                 status = "disabled";
 900                         };
 901
 902                         i2c2: i2c@21a4000 {
 903                                 #address-cells = <1>;
 904                                 #size-cells = <0>;
 905                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 906                                 reg = <0x021a4000 0x4000>;
 907                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 908                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 909                                 status = "disabled";
 910                         };
 911
 912                         i2c3: i2c@21a8000 {
 913                                 #address-cells = <1>;
 914                                 #size-cells = <0>;
 915                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 916                                 reg = <0x021a8000 0x4000>;
 917                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 918                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 919                                 status = "disabled";
 920                         };
 921
 922                         mmdc: mmdc@21b0000 {
 923                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 924                                 reg = <0x021b0000 0x4000>;
 925                         };
 926
 927                         rngb: rngb@21b4000 {
 928                                 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
 929                                 reg = <0x021b4000 0x4000>;
 930                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 931                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 932                         };
 933
 934                         weim: weim@21b8000 {
 935                                 #address-cells = <2>;
 936                                 #size-cells = <1>;
 937                                 reg = <0x021b8000 0x4000>;
 938                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 939                                 fsl,weim-cs-gpr = <&gpr>;
 940                                 status = "disabled";
 941                         };
 942
 943                         ocotp: ocotp@21bc000 {
 944                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 945                                 reg = <0x021bc000 0x4000>;
 946                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 947                         };
 948
 949                         audmux: audmux@21d8000 {
 950                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 951                                 reg = <0x021d8000 0x4000>;
 952                                 status = "disabled";
 953                         };
 954                 };
 955
 956                 gpu_2d: gpu@2200000 {
 957                         compatible = "vivante,gc";
 958                         reg = <0x02200000 0x4000>;
 959                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 960                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 961                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 962                         clock-names = "bus", "core";
 963                         power-domains = <&pd_pu>;
 964                 };
 965
 966                 gpu_vg: gpu@2204000 {
 967                         compatible = "vivante,gc";
 968                         reg = <0x02204000 0x4000>;
 969                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 970                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 971                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 972                         clock-names = "bus", "core";
 973                         power-domains = <&pd_pu>;
 974                 };
 975         };
 976 };