arch/arm/boot/dts/imx6sl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6sl-pinfunc.h"
   7 #include <dt-bindings/clock/imx6sl-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          */
  17         chosen {};
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 mmc2 = &usdhc3;
  32                 mmc3 = &usdhc4;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &ecspi3;
  41                 spi3 = &ecspi4;
  42                 usb0 = &usbotg1;
  43                 usb1 = &usbotg2;
  44                 usb2 = &usbh;
  45                 usbphy0 = &usbphy1;
  46                 usbphy1 = &usbphy2;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu@0 {
  54                         compatible = "arm,cortex-a9";
  55                         device_type = "cpu";
  56                         reg = <0x0>;
  57                         next-level-cache = <&L2>;
  58                         operating-points = <
  59                                 /* kHz    uV */
  60                                 996000  1275000
  61                                 792000  1175000
  62                                 396000  975000
  63                         >;
  64                         fsl,soc-operating-points = <
  65                                 /* ARM kHz      SOC-PU uV */
  66                                 996000          1225000
  67                                 792000          1175000
  68                                 396000          1175000
  69                         >;
  70                         clock-latency = <61036>; /* two CLK32 periods */
  71                         #cooling-cells = <2>;
  72                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  73                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  74                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  75                         clock-names = "arm", "pll2_pfd2_396m", "step",
  76                                       "pll1_sw", "pll1_sys";
  77                         arm-supply = <&reg_arm>;
  78                         pu-supply = <&reg_pu>;
  79                         soc-supply = <&reg_soc>;
  80                 };
  81         };
  82
  83         clocks {
  84                 ckil {
  85                         compatible = "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <32768>;
  88                 };
  89
  90                 osc {
  91                         compatible = "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <24000000>;
  94                 };
  95         };
  96
  97         tempmon: tempmon {
  98                 compatible = "fsl,imx6q-tempmon";
  99                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 100                 interrupt-parent = <&gpc>;
 101                 fsl,tempmon = <&anatop>;
 102                 fsl,tempmon-data = <&ocotp>;
 103                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 104         };
 105
 106         pmu {
 107                 compatible = "arm,cortex-a9-pmu";
 108                 interrupt-parent = <&gpc>;
 109                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 110         };
 111
 112         usbphynop1: usbphynop1 {
 113                 compatible = "usb-nop-xceiv";
 114                 #phy-cells = <0>;
 115         };
 116
 117         soc {
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 compatible = "simple-bus";
 121                 interrupt-parent = <&gpc>;
 122                 ranges;
 123
 124                 ocram: sram@900000 {
 125                         compatible = "mmio-sram";
 126                         reg = <0x00900000 0x20000>;
 127                         ranges = <0 0x00900000 0x20000>;
 128                         #address-cells = <1>;
 129                         #size-cells = <1>;
 130                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 131                 };
 132
 133                 intc: interrupt-controller@a01000 {
 134                         compatible = "arm,cortex-a9-gic";
 135                         #interrupt-cells = <3>;
 136                         interrupt-controller;
 137                         reg = <0x00a01000 0x1000>,
 138                               <0x00a00100 0x100>;
 139                         interrupt-parent = <&intc>;
 140                 };
 141
 142                 L2: cache-controller@a02000 {
 143                         compatible = "arm,pl310-cache";
 144                         reg = <0x00a02000 0x1000>;
 145                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 146                         cache-unified;
 147                         cache-level = <2>;
 148                         arm,tag-latency = <4 2 3>;
 149                         arm,data-latency = <4 2 3>;
 150                 };
 151
 152                 aips1: aips-bus@2000000 {
 153                         compatible = "fsl,aips-bus", "simple-bus";
 154                         #address-cells = <1>;
 155                         #size-cells = <1>;
 156                         reg = <0x02000000 0x100000>;
 157                         ranges;
 158
 159                         spba: spba-bus@2000000 {
 160                                 compatible = "fsl,spba-bus", "simple-bus";
 161                                 #address-cells = <1>;
 162                                 #size-cells = <1>;
 163                                 reg = <0x02000000 0x40000>;
 164                                 ranges;
 165
 166                                 spdif: spdif@2004000 {
 167                                         compatible = "fsl,imx6sl-spdif",
 168                                                 "fsl,imx35-spdif";
 169                                         reg = <0x02004000 0x4000>;
 170                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 171                                         dmas = <&sdma 14 18 0>,
 172                                                 <&sdma 15 18 0>;
 173                                         dma-names = "rx", "tx";
 174                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 175                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 176                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 177                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 178                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 179                                         clock-names = "core", "rxtx0",
 180                                                 "rxtx1", "rxtx2",
 181                                                 "rxtx3", "rxtx4",
 182                                                 "rxtx5", "rxtx6",
 183                                                 "rxtx7", "spba";
 184                                         status = "disabled";
 185                                 };
 186
 187                                 ecspi1: spi@2008000 {
 188                                         #address-cells = <1>;
 189                                         #size-cells = <0>;
 190                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 191                                         reg = <0x02008000 0x4000>;
 192                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 193                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 194                                                  <&clks IMX6SL_CLK_ECSPI1>;
 195                                         clock-names = "ipg", "per";
 196                                         status = "disabled";
 197                                 };
 198
 199                                 ecspi2: spi@200c000 {
 200                                         #address-cells = <1>;
 201                                         #size-cells = <0>;
 202                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 203                                         reg = <0x0200c000 0x4000>;
 204                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 205                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 206                                                  <&clks IMX6SL_CLK_ECSPI2>;
 207                                         clock-names = "ipg", "per";
 208                                         status = "disabled";
 209                                 };
 210
 211                                 ecspi3: spi@2010000 {
 212                                         #address-cells = <1>;
 213                                         #size-cells = <0>;
 214                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 215                                         reg = <0x02010000 0x4000>;
 216                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 217                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 218                                                  <&clks IMX6SL_CLK_ECSPI3>;
 219                                         clock-names = "ipg", "per";
 220                                         status = "disabled";
 221                                 };
 222
 223                                 ecspi4: spi@2014000 {
 224                                         #address-cells = <1>;
 225                                         #size-cells = <0>;
 226                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 227                                         reg = <0x02014000 0x4000>;
 228                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 229                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 230                                                  <&clks IMX6SL_CLK_ECSPI4>;
 231                                         clock-names = "ipg", "per";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 uart5: serial@2018000 {
 236                                         compatible = "fsl,imx6sl-uart",
 237                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 238                                         reg = <0x02018000 0x4000>;
 239                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 240                                         clocks = <&clks IMX6SL_CLK_UART>,
 241                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 242                                         clock-names = "ipg", "per";
 243                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 244                                         dma-names = "rx", "tx";
 245                                         status = "disabled";
 246                                 };
 247
 248                                 uart1: serial@2020000 {
 249                                         compatible = "fsl,imx6sl-uart",
 250                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 251                                         reg = <0x02020000 0x4000>;
 252                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 253                                         clocks = <&clks IMX6SL_CLK_UART>,
 254                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 255                                         clock-names = "ipg", "per";
 256                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 257                                         dma-names = "rx", "tx";
 258                                         status = "disabled";
 259                                 };
 260
 261                                 uart2: serial@2024000 {
 262                                         compatible = "fsl,imx6sl-uart",
 263                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 264                                         reg = <0x02024000 0x4000>;
 265                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 266                                         clocks = <&clks IMX6SL_CLK_UART>,
 267                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 270                                         dma-names = "rx", "tx";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 ssi1: ssi@2028000 {
 275                                         #sound-dai-cells = <0>;
 276                                         compatible = "fsl,imx6sl-ssi",
 277                                                         "fsl,imx51-ssi";
 278                                         reg = <0x02028000 0x4000>;
 279                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 280                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 281                                                  <&clks IMX6SL_CLK_SSI1>;
 282                                         clock-names = "ipg", "baud";
 283                                         dmas = <&sdma 37 1 0>,
 284                                                <&sdma 38 1 0>;
 285                                         dma-names = "rx", "tx";
 286                                         fsl,fifo-depth = <15>;
 287                                         status = "disabled";
 288                                 };
 289
 290                                 ssi2: ssi@202c000 {
 291                                         #sound-dai-cells = <0>;
 292                                         compatible = "fsl,imx6sl-ssi",
 293                                                         "fsl,imx51-ssi";
 294                                         reg = <0x0202c000 0x4000>;
 295                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 296                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 297                                                  <&clks IMX6SL_CLK_SSI2>;
 298                                         clock-names = "ipg", "baud";
 299                                         dmas = <&sdma 41 1 0>,
 300                                                <&sdma 42 1 0>;
 301                                         dma-names = "rx", "tx";
 302                                         fsl,fifo-depth = <15>;
 303                                         status = "disabled";
 304                                 };
 305
 306                                 ssi3: ssi@2030000 {
 307                                         #sound-dai-cells = <0>;
 308                                         compatible = "fsl,imx6sl-ssi",
 309                                                         "fsl,imx51-ssi";
 310                                         reg = <0x02030000 0x4000>;
 311                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 312                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 313                                                  <&clks IMX6SL_CLK_SSI3>;
 314                                         clock-names = "ipg", "baud";
 315                                         dmas = <&sdma 45 1 0>,
 316                                                <&sdma 46 1 0>;
 317                                         dma-names = "rx", "tx";
 318                                         fsl,fifo-depth = <15>;
 319                                         status = "disabled";
 320                                 };
 321
 322                                 uart3: serial@2034000 {
 323                                         compatible = "fsl,imx6sl-uart",
 324                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 325                                         reg = <0x02034000 0x4000>;
 326                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 327                                         clocks = <&clks IMX6SL_CLK_UART>,
 328                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 329                                         clock-names = "ipg", "per";
 330                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 331                                         dma-names = "rx", "tx";
 332                                         status = "disabled";
 333                                 };
 334
 335                                 uart4: serial@2038000 {
 336                                         compatible = "fsl,imx6sl-uart",
 337                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 338                                         reg = <0x02038000 0x4000>;
 339                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 340                                         clocks = <&clks IMX6SL_CLK_UART>,
 341                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 342                                         clock-names = "ipg", "per";
 343                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 344                                         dma-names = "rx", "tx";
 345                                         status = "disabled";
 346                                 };
 347                         };
 348
 349                         pwm1: pwm@2080000 {
 350                                 #pwm-cells = <2>;
 351                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 352                                 reg = <0x02080000 0x4000>;
 353                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 354                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 355                                          <&clks IMX6SL_CLK_PWM1>;
 356                                 clock-names = "ipg", "per";
 357                         };
 358
 359                         pwm2: pwm@2084000 {
 360                                 #pwm-cells = <2>;
 361                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 362                                 reg = <0x02084000 0x4000>;
 363                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 364                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 365                                          <&clks IMX6SL_CLK_PWM2>;
 366                                 clock-names = "ipg", "per";
 367                         };
 368
 369                         pwm3: pwm@2088000 {
 370                                 #pwm-cells = <2>;
 371                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 372                                 reg = <0x02088000 0x4000>;
 373                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 374                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 375                                          <&clks IMX6SL_CLK_PWM3>;
 376                                 clock-names = "ipg", "per";
 377                         };
 378
 379                         pwm4: pwm@208c000 {
 380                                 #pwm-cells = <2>;
 381                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 382                                 reg = <0x0208c000 0x4000>;
 383                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 385                                          <&clks IMX6SL_CLK_PWM4>;
 386                                 clock-names = "ipg", "per";
 387                         };
 388
 389                         gpt: timer@2098000 {
 390                                 compatible = "fsl,imx6sl-gpt";
 391                                 reg = <0x02098000 0x4000>;
 392                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 393                                 clocks = <&clks IMX6SL_CLK_GPT>,
 394                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 395                                 clock-names = "ipg", "per";
 396                         };
 397
 398                         gpio1: gpio@209c000 {
 399                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 400                                 reg = <0x0209c000 0x4000>;
 401                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 402                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 403                                 gpio-controller;
 404                                 #gpio-cells = <2>;
 405                                 interrupt-controller;
 406                                 #interrupt-cells = <2>;
 407                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 408                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 409                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 410                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 411                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 412                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 413                         };
 414
 415                         gpio2: gpio@20a0000 {
 416                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 417                                 reg = <0x020a0000 0x4000>;
 418                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 419                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 420                                 gpio-controller;
 421                                 #gpio-cells = <2>;
 422                                 interrupt-controller;
 423                                 #interrupt-cells = <2>;
 424                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 425                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 426                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 427                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 428                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 429                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 430                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 431                         };
 432
 433                         gpio3: gpio@20a4000 {
 434                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 435                                 reg = <0x020a4000 0x4000>;
 436                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 437                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 438                                 gpio-controller;
 439                                 #gpio-cells = <2>;
 440                                 interrupt-controller;
 441                                 #interrupt-cells = <2>;
 442                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 443                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 444                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 445                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 446                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 447                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 448                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 449                                               <&iomuxc 31 102 1>;
 450                         };
 451
 452                         gpio4: gpio@20a8000 {
 453                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 454                                 reg = <0x020a8000 0x4000>;
 455                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 456                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 457                                 gpio-controller;
 458                                 #gpio-cells = <2>;
 459                                 interrupt-controller;
 460                                 #interrupt-cells = <2>;
 461                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 462                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 463                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 464                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 465                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 466                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 467                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 468                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 469                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 470                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 471                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 472                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 473                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 474                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 475                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 476                         };
 477
 478                         gpio5: gpio@20ac000 {
 479                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 480                                 reg = <0x020ac000 0x4000>;
 481                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 482                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 483                                 gpio-controller;
 484                                 #gpio-cells = <2>;
 485                                 interrupt-controller;
 486                                 #interrupt-cells = <2>;
 487                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 488                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 489                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 490                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 491                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 492                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 493                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 494                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 495                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 496                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 497                                               <&iomuxc 21 161 1>;
 498                         };
 499
 500                         kpp: kpp@20b8000 {
 501                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 502                                 reg = <0x020b8000 0x4000>;
 503                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6SL_CLK_IPG>;
 505                                 status = "disabled";
 506                         };
 507
 508                         wdog1: wdog@20bc000 {
 509                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 510                                 reg = <0x020bc000 0x4000>;
 511                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 512                                 clocks = <&clks IMX6SL_CLK_IPG>;
 513                         };
 514
 515                         wdog2: wdog@20c0000 {
 516                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 517                                 reg = <0x020c0000 0x4000>;
 518                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 519                                 clocks = <&clks IMX6SL_CLK_IPG>;
 520                                 status = "disabled";
 521                         };
 522
 523                         clks: ccm@20c4000 {
 524                                 compatible = "fsl,imx6sl-ccm";
 525                                 reg = <0x020c4000 0x4000>;
 526                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 527                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 528                                 #clock-cells = <1>;
 529                         };
 530
 531                         anatop: anatop@20c8000 {
 532                                 compatible = "fsl,imx6sl-anatop",
 533                                              "fsl,imx6q-anatop",
 534                                              "syscon", "simple-bus";
 535                                 reg = <0x020c8000 0x1000>;
 536                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 537                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 538                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 539
 540                                 reg_vdd1p1: regulator-1p1 {
 541                                         compatible = "fsl,anatop-regulator";
 542                                         regulator-name = "vdd1p1";
 543                                         regulator-min-microvolt = <1000000>;
 544                                         regulator-max-microvolt = <1200000>;
 545                                         regulator-always-on;
 546                                         anatop-reg-offset = <0x110>;
 547                                         anatop-vol-bit-shift = <8>;
 548                                         anatop-vol-bit-width = <5>;
 549                                         anatop-min-bit-val = <4>;
 550                                         anatop-min-voltage = <800000>;
 551                                         anatop-max-voltage = <1375000>;
 552                                         anatop-enable-bit = <0>;
 553                                 };
 554
 555                                 reg_vdd3p0: regulator-3p0 {
 556                                         compatible = "fsl,anatop-regulator";
 557                                         regulator-name = "vdd3p0";
 558                                         regulator-min-microvolt = <2800000>;
 559                                         regulator-max-microvolt = <3150000>;
 560                                         regulator-always-on;
 561                                         anatop-reg-offset = <0x120>;
 562                                         anatop-vol-bit-shift = <8>;
 563                                         anatop-vol-bit-width = <5>;
 564                                         anatop-min-bit-val = <0>;
 565                                         anatop-min-voltage = <2625000>;
 566                                         anatop-max-voltage = <3400000>;
 567                                         anatop-enable-bit = <0>;
 568                                 };
 569
 570                                 reg_vdd2p5: regulator-2p5 {
 571                                         compatible = "fsl,anatop-regulator";
 572                                         regulator-name = "vdd2p5";
 573                                         regulator-min-microvolt = <2250000>;
 574                                         regulator-max-microvolt = <2750000>;
 575                                         regulator-always-on;
 576                                         anatop-reg-offset = <0x130>;
 577                                         anatop-vol-bit-shift = <8>;
 578                                         anatop-vol-bit-width = <5>;
 579                                         anatop-min-bit-val = <0>;
 580                                         anatop-min-voltage = <2100000>;
 581                                         anatop-max-voltage = <2850000>;
 582                                         anatop-enable-bit = <0>;
 583                                 };
 584
 585                                 reg_arm: regulator-vddcore {
 586                                         compatible = "fsl,anatop-regulator";
 587                                         regulator-name = "vddarm";
 588                                         regulator-min-microvolt = <725000>;
 589                                         regulator-max-microvolt = <1450000>;
 590                                         regulator-always-on;
 591                                         anatop-reg-offset = <0x140>;
 592                                         anatop-vol-bit-shift = <0>;
 593                                         anatop-vol-bit-width = <5>;
 594                                         anatop-delay-reg-offset = <0x170>;
 595                                         anatop-delay-bit-shift = <24>;
 596                                         anatop-delay-bit-width = <2>;
 597                                         anatop-min-bit-val = <1>;
 598                                         anatop-min-voltage = <725000>;
 599                                         anatop-max-voltage = <1450000>;
 600                                 };
 601
 602                                 reg_pu: regulator-vddpu {
 603                                         compatible = "fsl,anatop-regulator";
 604                                         regulator-name = "vddpu";
 605                                         regulator-min-microvolt = <725000>;
 606                                         regulator-max-microvolt = <1450000>;
 607                                         anatop-reg-offset = <0x140>;
 608                                         anatop-vol-bit-shift = <9>;
 609                                         anatop-vol-bit-width = <5>;
 610                                         anatop-delay-reg-offset = <0x170>;
 611                                         anatop-delay-bit-shift = <26>;
 612                                         anatop-delay-bit-width = <2>;
 613                                         anatop-min-bit-val = <1>;
 614                                         anatop-min-voltage = <725000>;
 615                                         anatop-max-voltage = <1450000>;
 616                                 };
 617
 618                                 reg_soc: regulator-vddsoc {
 619                                         compatible = "fsl,anatop-regulator";
 620                                         regulator-name = "vddsoc";
 621                                         regulator-min-microvolt = <725000>;
 622                                         regulator-max-microvolt = <1450000>;
 623                                         regulator-always-on;
 624                                         anatop-reg-offset = <0x140>;
 625                                         anatop-vol-bit-shift = <18>;
 626                                         anatop-vol-bit-width = <5>;
 627                                         anatop-delay-reg-offset = <0x170>;
 628                                         anatop-delay-bit-shift = <28>;
 629                                         anatop-delay-bit-width = <2>;
 630                                         anatop-min-bit-val = <1>;
 631                                         anatop-min-voltage = <725000>;
 632                                         anatop-max-voltage = <1450000>;
 633                                 };
 634                         };
 635
 636                         usbphy1: usbphy@20c9000 {
 637                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 638                                 reg = <0x020c9000 0x1000>;
 639                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 640                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 641                                 fsl,anatop = <&anatop>;
 642                         };
 643
 644                         usbphy2: usbphy@20ca000 {
 645                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 646                                 reg = <0x020ca000 0x1000>;
 647                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 648                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 649                                 fsl,anatop = <&anatop>;
 650                         };
 651
 652                         snvs: snvs@20cc000 {
 653                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 654                                 reg = <0x020cc000 0x4000>;
 655
 656                                 snvs_rtc: snvs-rtc-lp {
 657                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 658                                         regmap = <&snvs>;
 659                                         offset = <0x34>;
 660                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 661                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 662                                 };
 663
 664                                 snvs_poweroff: snvs-poweroff {
 665                                         compatible = "syscon-poweroff";
 666                                         regmap = <&snvs>;
 667                                         offset = <0x38>;
 668                                         value = <0x60>;
 669                                         mask = <0x60>;
 670                                         status = "disabled";
 671                                 };
 672                         };
 673
 674                         epit1: epit@20d0000 {
 675                                 reg = <0x020d0000 0x4000>;
 676                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 677                         };
 678
 679                         epit2: epit@20d4000 {
 680                                 reg = <0x020d4000 0x4000>;
 681                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 682                         };
 683
 684                         src: src@20d8000 {
 685                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 686                                 reg = <0x020d8000 0x4000>;
 687                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 688                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 689                                 #reset-cells = <1>;
 690                         };
 691
 692                         gpc: gpc@20dc000 {
 693                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 694                                 reg = <0x020dc000 0x4000>;
 695                                 interrupt-controller;
 696                                 #interrupt-cells = <3>;
 697                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 698                                 interrupt-parent = <&intc>;
 699                                 clocks = <&clks IMX6SL_CLK_IPG>;
 700                                 clock-names = "ipg";
 701
 702                                 pgc {
 703                                         #address-cells = <1>;
 704                                         #size-cells = <0>;
 705
 706                                         power-domain@0 {
 707                                                 reg = <0>;
 708                                                 #power-domain-cells = <0>;
 709                                         };
 710
 711                                         pd_pu: power-domain@1 {
 712                                                 reg = <1>;
 713                                                 #power-domain-cells = <0>;
 714                                                 power-supply = <&reg_pu>;
 715                                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 716                                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 717                                         };
 718
 719                                         pd_disp: power-domain@2 {
 720                                                 reg = <2>;
 721                                                 #power-domain-cells = <0>;
 722                                                 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
 723                                                          <&clks IMX6SL_CLK_LCDIF_PIX>,
 724                                                          <&clks IMX6SL_CLK_EPDC_AXI>,
 725                                                          <&clks IMX6SL_CLK_EPDC_PIX>,
 726                                                          <&clks IMX6SL_CLK_PXP_AXI>;
 727                                         };
 728                                 };
 729                         };
 730
 731                         gpr: iomuxc-gpr@20e0000 {
 732                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 733                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 734                                 reg = <0x020e0000 0x38>;
 735                         };
 736
 737                         iomuxc: iomuxc@20e0000 {
 738                                 compatible = "fsl,imx6sl-iomuxc";
 739                                 reg = <0x020e0000 0x4000>;
 740                         };
 741
 742                         csi: csi@20e4000 {
 743                                 reg = <0x020e4000 0x4000>;
 744                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 745                         };
 746
 747                         spdc: spdc@20e8000 {
 748                                 reg = <0x020e8000 0x4000>;
 749                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 750                         };
 751
 752                         sdma: sdma@20ec000 {
 753                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 754                                 reg = <0x020ec000 0x4000>;
 755                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 756                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 757                                          <&clks IMX6SL_CLK_AHB>;
 758                                 clock-names = "ipg", "ahb";
 759                                 #dma-cells = <3>;
 760                                 /* imx6sl reuses imx6q sdma firmware */
 761                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 762                         };
 763
 764                         pxp: pxp@20f0000 {
 765                                 reg = <0x020f0000 0x4000>;
 766                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 767                         };
 768
 769                         epdc: epdc@20f4000 {
 770                                 reg = <0x020f4000 0x4000>;
 771                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 772                         };
 773
 774                         lcdif: lcdif@20f8000 {
 775                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 776                                 reg = <0x020f8000 0x4000>;
 777                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 778                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 779                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 780                                          <&clks IMX6SL_CLK_DUMMY>;
 781                                 clock-names = "pix", "axi", "disp_axi";
 782                                 status = "disabled";
 783                                 power-domains = <&pd_disp>;
 784                         };
 785
 786                         dcp: dcp@20fc000 {
 787                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 788                                 reg = <0x020fc000 0x4000>;
 789                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 790                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 791                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 792                         };
 793                 };
 794
 795                 aips2: aips-bus@2100000 {
 796                         compatible = "fsl,aips-bus", "simple-bus";
 797                         #address-cells = <1>;
 798                         #size-cells = <1>;
 799                         reg = <0x02100000 0x100000>;
 800                         ranges;
 801
 802                         usbotg1: usb@2184000 {
 803                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 804                                 reg = <0x02184000 0x200>;
 805                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 806                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 807                                 fsl,usbphy = <&usbphy1>;
 808                                 fsl,usbmisc = <&usbmisc 0>;
 809                                 ahb-burst-config = <0x0>;
 810                                 tx-burst-size-dword = <0x10>;
 811                                 rx-burst-size-dword = <0x10>;
 812                                 status = "disabled";
 813                         };
 814
 815                         usbotg2: usb@2184200 {
 816                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 817                                 reg = <0x02184200 0x200>;
 818                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 820                                 fsl,usbphy = <&usbphy2>;
 821                                 fsl,usbmisc = <&usbmisc 1>;
 822                                 ahb-burst-config = <0x0>;
 823                                 tx-burst-size-dword = <0x10>;
 824                                 rx-burst-size-dword = <0x10>;
 825                                 status = "disabled";
 826                         };
 827
 828                         usbh: usb@2184400 {
 829                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 830                                 reg = <0x02184400 0x200>;
 831                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 833                                 fsl,usbphy = <&usbphynop1>;
 834                                 phy_type = "hsic";
 835                                 fsl,usbmisc = <&usbmisc 2>;
 836                                 dr_mode = "host";
 837                                 ahb-burst-config = <0x0>;
 838                                 tx-burst-size-dword = <0x10>;
 839                                 rx-burst-size-dword = <0x10>;
 840                                 status = "disabled";
 841                         };
 842
 843                         usbmisc: usbmisc@2184800 {
 844                                 #index-cells = <1>;
 845                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 846                                 reg = <0x02184800 0x200>;
 847                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 848                         };
 849
 850                         fec: ethernet@2188000 {
 851                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 852                                 reg = <0x02188000 0x4000>;
 853                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 854                                 clocks = <&clks IMX6SL_CLK_ENET>,
 855                                          <&clks IMX6SL_CLK_ENET_REF>;
 856                                 clock-names = "ipg", "ahb";
 857                                 status = "disabled";
 858                         };
 859
 860                         usdhc1: usdhc@2190000 {
 861                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 862                                 reg = <0x02190000 0x4000>;
 863                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 864                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 865                                          <&clks IMX6SL_CLK_USDHC1>,
 866                                          <&clks IMX6SL_CLK_USDHC1>;
 867                                 clock-names = "ipg", "ahb", "per";
 868                                 bus-width = <4>;
 869                                 status = "disabled";
 870                         };
 871
 872                         usdhc2: usdhc@2194000 {
 873                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 874                                 reg = <0x02194000 0x4000>;
 875                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 876                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 877                                          <&clks IMX6SL_CLK_USDHC2>,
 878                                          <&clks IMX6SL_CLK_USDHC2>;
 879                                 clock-names = "ipg", "ahb", "per";
 880                                 bus-width = <4>;
 881                                 status = "disabled";
 882                         };
 883
 884                         usdhc3: usdhc@2198000 {
 885                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 886                                 reg = <0x02198000 0x4000>;
 887                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 888                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 889                                          <&clks IMX6SL_CLK_USDHC3>,
 890                                          <&clks IMX6SL_CLK_USDHC3>;
 891                                 clock-names = "ipg", "ahb", "per";
 892                                 bus-width = <4>;
 893                                 status = "disabled";
 894                         };
 895
 896                         usdhc4: usdhc@219c000 {
 897                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 898                                 reg = <0x0219c000 0x4000>;
 899                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 900                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 901                                          <&clks IMX6SL_CLK_USDHC4>,
 902                                          <&clks IMX6SL_CLK_USDHC4>;
 903                                 clock-names = "ipg", "ahb", "per";
 904                                 bus-width = <4>;
 905                                 status = "disabled";
 906                         };
 907
 908                         i2c1: i2c@21a0000 {
 909                                 #address-cells = <1>;
 910                                 #size-cells = <0>;
 911                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 912                                 reg = <0x021a0000 0x4000>;
 913                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 914                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 915                                 status = "disabled";
 916                         };
 917
 918                         i2c2: i2c@21a4000 {
 919                                 #address-cells = <1>;
 920                                 #size-cells = <0>;
 921                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 922                                 reg = <0x021a4000 0x4000>;
 923                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 924                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 925                                 status = "disabled";
 926                         };
 927
 928                         i2c3: i2c@21a8000 {
 929                                 #address-cells = <1>;
 930                                 #size-cells = <0>;
 931                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 932                                 reg = <0x021a8000 0x4000>;
 933                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 934                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 935                                 status = "disabled";
 936                         };
 937
 938                         memory-controller@21b0000 {
 939                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 940                                 reg = <0x021b0000 0x4000>;
 941                                 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
 942                         };
 943
 944                         rngb: rngb@21b4000 {
 945                                 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
 946                                 reg = <0x021b4000 0x4000>;
 947                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 948                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 949                         };
 950
 951                         weim: weim@21b8000 {
 952                                 #address-cells = <2>;
 953                                 #size-cells = <1>;
 954                                 reg = <0x021b8000 0x4000>;
 955                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 956                                 fsl,weim-cs-gpr = <&gpr>;
 957                                 status = "disabled";
 958                         };
 959
 960                         ocotp: ocotp@21bc000 {
 961                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 962                                 reg = <0x021bc000 0x4000>;
 963                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 964                         };
 965
 966                         audmux: audmux@21d8000 {
 967                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 968                                 reg = <0x021d8000 0x4000>;
 969                                 status = "disabled";
 970                         };
 971                 };
 972
 973                 gpu_2d: gpu@2200000 {
 974                         compatible = "vivante,gc";
 975                         reg = <0x02200000 0x4000>;
 976                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 977                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 978                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 979                         clock-names = "bus", "core";
 980                         power-domains = <&pd_pu>;
 981                 };
 982
 983                 gpu_vg: gpu@2204000 {
 984                         compatible = "vivante,gc";
 985                         reg = <0x02204000 0x4000>;
 986                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 987                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 988                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 989                         clock-names = "bus", "core";
 990                         power-domains = <&pd_pu>;
 991                 };
 992         };
 993 };