arch/arm/boot/dts/imx6sl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6sl-pinfunc.h"
   7 #include <dt-bindings/clock/imx6sl-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          */
  17         chosen {};
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 mmc2 = &usdhc3;
  32                 mmc3 = &usdhc4;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &ecspi3;
  41                 spi3 = &ecspi4;
  42                 usb0 = &usbotg1;
  43                 usb1 = &usbotg2;
  44                 usb2 = &usbh;
  45                 usbphy0 = &usbphy1;
  46                 usbphy1 = &usbphy2;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         compatible = "arm,cortex-a9";
  55                         device_type = "cpu";
  56                         reg = <0x0>;
  57                         next-level-cache = <&L2>;
  58                         operating-points =
  59                                 /* kHz    uV */
  60                                 <996000  1275000>,
  61                                 <792000  1175000>,
  62                                 <396000  975000>;
  63                         fsl,soc-operating-points =
  64                                 /* ARM kHz      SOC-PU uV */
  65                                 <996000         1225000>,
  66                                 <792000         1175000>,
  67                                 <396000         1175000>;
  68                         clock-latency = <61036>; /* two CLK32 periods */
  69                         #cooling-cells = <2>;
  70                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  71                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  72                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  73                         clock-names = "arm", "pll2_pfd2_396m", "step",
  74                                       "pll1_sw", "pll1_sys";
  75                         arm-supply = <&reg_arm>;
  76                         pu-supply = <&reg_pu>;
  77                         soc-supply = <&reg_soc>;
  78                         nvmem-cells = <&cpu_speed_grade>;
  79                         nvmem-cell-names = "speed_grade";
  80                 };
  81         };
  82
  83         clocks {
  84                 ckil {
  85                         compatible = "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <32768>;
  88                 };
  89
  90                 osc {
  91                         compatible = "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <24000000>;
  94                 };
  95         };
  96
  97         pmu {
  98                 compatible = "arm,cortex-a9-pmu";
  99                 interrupt-parent = <&gpc>;
 100                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 101         };
 102
 103         usbphynop1: usbphynop1 {
 104                 compatible = "usb-nop-xceiv";
 105                 #phy-cells = <0>;
 106         };
 107
 108         soc {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 compatible = "simple-bus";
 112                 interrupt-parent = <&gpc>;
 113                 ranges;
 114
 115                 ocram: sram@900000 {
 116                         compatible = "mmio-sram";
 117                         reg = <0x00900000 0x20000>;
 118                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 119                 };
 120
 121                 intc: interrupt-controller@a01000 {
 122                         compatible = "arm,cortex-a9-gic";
 123                         #interrupt-cells = <3>;
 124                         interrupt-controller;
 125                         reg = <0x00a01000 0x1000>,
 126                               <0x00a00100 0x100>;
 127                         interrupt-parent = <&intc>;
 128                 };
 129
 130                 L2: cache-controller@a02000 {
 131                         compatible = "arm,pl310-cache";
 132                         reg = <0x00a02000 0x1000>;
 133                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 134                         cache-unified;
 135                         cache-level = <2>;
 136                         arm,tag-latency = <4 2 3>;
 137                         arm,data-latency = <4 2 3>;
 138                 };
 139
 140                 aips1: bus@2000000 {
 141                         compatible = "fsl,aips-bus", "simple-bus";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         reg = <0x02000000 0x100000>;
 145                         ranges;
 146
 147                         spba: spba-bus@2000000 {
 148                                 compatible = "fsl,spba-bus", "simple-bus";
 149                                 #address-cells = <1>;
 150                                 #size-cells = <1>;
 151                                 reg = <0x02000000 0x40000>;
 152                                 ranges;
 153
 154                                 spdif: spdif@2004000 {
 155                                         compatible = "fsl,imx6sl-spdif",
 156                                                 "fsl,imx35-spdif";
 157                                         reg = <0x02004000 0x4000>;
 158                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 159                                         dmas = <&sdma 14 18 0>,
 160                                                 <&sdma 15 18 0>;
 161                                         dma-names = "rx", "tx";
 162                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 163                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 164                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 165                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 166                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 167                                         clock-names = "core", "rxtx0",
 168                                                 "rxtx1", "rxtx2",
 169                                                 "rxtx3", "rxtx4",
 170                                                 "rxtx5", "rxtx6",
 171                                                 "rxtx7", "spba";
 172                                         status = "disabled";
 173                                 };
 174
 175                                 ecspi1: spi@2008000 {
 176                                         #address-cells = <1>;
 177                                         #size-cells = <0>;
 178                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 179                                         reg = <0x02008000 0x4000>;
 180                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 181                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 182                                                  <&clks IMX6SL_CLK_ECSPI1>;
 183                                         clock-names = "ipg", "per";
 184                                         status = "disabled";
 185                                 };
 186
 187                                 ecspi2: spi@200c000 {
 188                                         #address-cells = <1>;
 189                                         #size-cells = <0>;
 190                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 191                                         reg = <0x0200c000 0x4000>;
 192                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 193                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 194                                                  <&clks IMX6SL_CLK_ECSPI2>;
 195                                         clock-names = "ipg", "per";
 196                                         status = "disabled";
 197                                 };
 198
 199                                 ecspi3: spi@2010000 {
 200                                         #address-cells = <1>;
 201                                         #size-cells = <0>;
 202                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 203                                         reg = <0x02010000 0x4000>;
 204                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 205                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 206                                                  <&clks IMX6SL_CLK_ECSPI3>;
 207                                         clock-names = "ipg", "per";
 208                                         status = "disabled";
 209                                 };
 210
 211                                 ecspi4: spi@2014000 {
 212                                         #address-cells = <1>;
 213                                         #size-cells = <0>;
 214                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 215                                         reg = <0x02014000 0x4000>;
 216                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 217                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 218                                                  <&clks IMX6SL_CLK_ECSPI4>;
 219                                         clock-names = "ipg", "per";
 220                                         status = "disabled";
 221                                 };
 222
 223                                 uart5: serial@2018000 {
 224                                         compatible = "fsl,imx6sl-uart",
 225                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 226                                         reg = <0x02018000 0x4000>;
 227                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 228                                         clocks = <&clks IMX6SL_CLK_UART>,
 229                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 230                                         clock-names = "ipg", "per";
 231                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 232                                         dma-names = "rx", "tx";
 233                                         status = "disabled";
 234                                 };
 235
 236                                 uart1: serial@2020000 {
 237                                         compatible = "fsl,imx6sl-uart",
 238                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 239                                         reg = <0x02020000 0x4000>;
 240                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 241                                         clocks = <&clks IMX6SL_CLK_UART>,
 242                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 243                                         clock-names = "ipg", "per";
 244                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 245                                         dma-names = "rx", "tx";
 246                                         status = "disabled";
 247                                 };
 248
 249                                 uart2: serial@2024000 {
 250                                         compatible = "fsl,imx6sl-uart",
 251                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 252                                         reg = <0x02024000 0x4000>;
 253                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 254                                         clocks = <&clks IMX6SL_CLK_UART>,
 255                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 256                                         clock-names = "ipg", "per";
 257                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 258                                         dma-names = "rx", "tx";
 259                                         status = "disabled";
 260                                 };
 261
 262                                 ssi1: ssi@2028000 {
 263                                         #sound-dai-cells = <0>;
 264                                         compatible = "fsl,imx6sl-ssi",
 265                                                         "fsl,imx51-ssi";
 266                                         reg = <0x02028000 0x4000>;
 267                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 268                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 269                                                  <&clks IMX6SL_CLK_SSI1>;
 270                                         clock-names = "ipg", "baud";
 271                                         dmas = <&sdma 37 1 0>,
 272                                                <&sdma 38 1 0>;
 273                                         dma-names = "rx", "tx";
 274                                         fsl,fifo-depth = <15>;
 275                                         status = "disabled";
 276                                 };
 277
 278                                 ssi2: ssi@202c000 {
 279                                         #sound-dai-cells = <0>;
 280                                         compatible = "fsl,imx6sl-ssi",
 281                                                         "fsl,imx51-ssi";
 282                                         reg = <0x0202c000 0x4000>;
 283                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 284                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 285                                                  <&clks IMX6SL_CLK_SSI2>;
 286                                         clock-names = "ipg", "baud";
 287                                         dmas = <&sdma 41 1 0>,
 288                                                <&sdma 42 1 0>;
 289                                         dma-names = "rx", "tx";
 290                                         fsl,fifo-depth = <15>;
 291                                         status = "disabled";
 292                                 };
 293
 294                                 ssi3: ssi@2030000 {
 295                                         #sound-dai-cells = <0>;
 296                                         compatible = "fsl,imx6sl-ssi",
 297                                                         "fsl,imx51-ssi";
 298                                         reg = <0x02030000 0x4000>;
 299                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 300                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 301                                                  <&clks IMX6SL_CLK_SSI3>;
 302                                         clock-names = "ipg", "baud";
 303                                         dmas = <&sdma 45 1 0>,
 304                                                <&sdma 46 1 0>;
 305                                         dma-names = "rx", "tx";
 306                                         fsl,fifo-depth = <15>;
 307                                         status = "disabled";
 308                                 };
 309
 310                                 uart3: serial@2034000 {
 311                                         compatible = "fsl,imx6sl-uart",
 312                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 313                                         reg = <0x02034000 0x4000>;
 314                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 315                                         clocks = <&clks IMX6SL_CLK_UART>,
 316                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 317                                         clock-names = "ipg", "per";
 318                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 319                                         dma-names = "rx", "tx";
 320                                         status = "disabled";
 321                                 };
 322
 323                                 uart4: serial@2038000 {
 324                                         compatible = "fsl,imx6sl-uart",
 325                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 326                                         reg = <0x02038000 0x4000>;
 327                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 328                                         clocks = <&clks IMX6SL_CLK_UART>,
 329                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 330                                         clock-names = "ipg", "per";
 331                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 332                                         dma-names = "rx", "tx";
 333                                         status = "disabled";
 334                                 };
 335                         };
 336
 337                         pwm1: pwm@2080000 {
 338                                 #pwm-cells = <3>;
 339                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 340                                 reg = <0x02080000 0x4000>;
 341                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 342                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 343                                          <&clks IMX6SL_CLK_PWM1>;
 344                                 clock-names = "ipg", "per";
 345                         };
 346
 347                         pwm2: pwm@2084000 {
 348                                 #pwm-cells = <3>;
 349                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 350                                 reg = <0x02084000 0x4000>;
 351                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 352                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 353                                          <&clks IMX6SL_CLK_PWM2>;
 354                                 clock-names = "ipg", "per";
 355                         };
 356
 357                         pwm3: pwm@2088000 {
 358                                 #pwm-cells = <3>;
 359                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 360                                 reg = <0x02088000 0x4000>;
 361                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 362                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 363                                          <&clks IMX6SL_CLK_PWM3>;
 364                                 clock-names = "ipg", "per";
 365                         };
 366
 367                         pwm4: pwm@208c000 {
 368                                 #pwm-cells = <3>;
 369                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 370                                 reg = <0x0208c000 0x4000>;
 371                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 372                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 373                                          <&clks IMX6SL_CLK_PWM4>;
 374                                 clock-names = "ipg", "per";
 375                         };
 376
 377                         gpt: timer@2098000 {
 378                                 compatible = "fsl,imx6sl-gpt";
 379                                 reg = <0x02098000 0x4000>;
 380                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 381                                 clocks = <&clks IMX6SL_CLK_GPT>,
 382                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 383                                 clock-names = "ipg", "per";
 384                         };
 385
 386                         gpio1: gpio@209c000 {
 387                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 388                                 reg = <0x0209c000 0x4000>;
 389                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 390                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 391                                 gpio-controller;
 392                                 #gpio-cells = <2>;
 393                                 interrupt-controller;
 394                                 #interrupt-cells = <2>;
 395                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 396                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 397                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 398                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 399                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 400                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 401                         };
 402
 403                         gpio2: gpio@20a0000 {
 404                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 405                                 reg = <0x020a0000 0x4000>;
 406                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 407                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 408                                 gpio-controller;
 409                                 #gpio-cells = <2>;
 410                                 interrupt-controller;
 411                                 #interrupt-cells = <2>;
 412                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 413                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 414                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 415                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 416                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 417                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 418                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 419                         };
 420
 421                         gpio3: gpio@20a4000 {
 422                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 423                                 reg = <0x020a4000 0x4000>;
 424                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 425                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 426                                 gpio-controller;
 427                                 #gpio-cells = <2>;
 428                                 interrupt-controller;
 429                                 #interrupt-cells = <2>;
 430                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 431                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 432                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 433                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 434                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 435                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 436                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 437                                               <&iomuxc 31 102 1>;
 438                         };
 439
 440                         gpio4: gpio@20a8000 {
 441                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 442                                 reg = <0x020a8000 0x4000>;
 443                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 444                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 445                                 gpio-controller;
 446                                 #gpio-cells = <2>;
 447                                 interrupt-controller;
 448                                 #interrupt-cells = <2>;
 449                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 450                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 451                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 452                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 453                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 454                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 455                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 456                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 457                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 458                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 459                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 460                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 461                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 462                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 463                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 464                         };
 465
 466                         gpio5: gpio@20ac000 {
 467                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 468                                 reg = <0x020ac000 0x4000>;
 469                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 470                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 471                                 gpio-controller;
 472                                 #gpio-cells = <2>;
 473                                 interrupt-controller;
 474                                 #interrupt-cells = <2>;
 475                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 476                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 477                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 478                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 479                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 480                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 481                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 482                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 483                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 484                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 485                                               <&iomuxc 21 161 1>;
 486                         };
 487
 488                         kpp: keypad@20b8000 {
 489                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 490                                 reg = <0x020b8000 0x4000>;
 491                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 492                                 clocks = <&clks IMX6SL_CLK_IPG>;
 493                                 status = "disabled";
 494                         };
 495
 496                         wdog1: watchdog@20bc000 {
 497                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 498                                 reg = <0x020bc000 0x4000>;
 499                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 500                                 clocks = <&clks IMX6SL_CLK_IPG>;
 501                         };
 502
 503                         wdog2: watchdog@20c0000 {
 504                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 505                                 reg = <0x020c0000 0x4000>;
 506                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 507                                 clocks = <&clks IMX6SL_CLK_IPG>;
 508                                 status = "disabled";
 509                         };
 510
 511                         clks: clock-controller@20c4000 {
 512                                 compatible = "fsl,imx6sl-ccm";
 513                                 reg = <0x020c4000 0x4000>;
 514                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 515                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 516                                 #clock-cells = <1>;
 517                         };
 518
 519                         anatop: anatop@20c8000 {
 520                                 compatible = "fsl,imx6sl-anatop",
 521                                              "fsl,imx6q-anatop",
 522                                              "syscon", "simple-mfd";
 523                                 reg = <0x020c8000 0x1000>;
 524                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 525                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 526                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 527
 528                                 reg_vdd1p1: regulator-1p1 {
 529                                         compatible = "fsl,anatop-regulator";
 530                                         regulator-name = "vdd1p1";
 531                                         regulator-min-microvolt = <1000000>;
 532                                         regulator-max-microvolt = <1200000>;
 533                                         regulator-always-on;
 534                                         anatop-reg-offset = <0x110>;
 535                                         anatop-vol-bit-shift = <8>;
 536                                         anatop-vol-bit-width = <5>;
 537                                         anatop-min-bit-val = <4>;
 538                                         anatop-min-voltage = <800000>;
 539                                         anatop-max-voltage = <1375000>;
 540                                         anatop-enable-bit = <0>;
 541                                 };
 542
 543                                 reg_vdd3p0: regulator-3p0 {
 544                                         compatible = "fsl,anatop-regulator";
 545                                         regulator-name = "vdd3p0";
 546                                         regulator-min-microvolt = <2800000>;
 547                                         regulator-max-microvolt = <3150000>;
 548                                         regulator-always-on;
 549                                         anatop-reg-offset = <0x120>;
 550                                         anatop-vol-bit-shift = <8>;
 551                                         anatop-vol-bit-width = <5>;
 552                                         anatop-min-bit-val = <0>;
 553                                         anatop-min-voltage = <2625000>;
 554                                         anatop-max-voltage = <3400000>;
 555                                         anatop-enable-bit = <0>;
 556                                 };
 557
 558                                 reg_vdd2p5: regulator-2p5 {
 559                                         compatible = "fsl,anatop-regulator";
 560                                         regulator-name = "vdd2p5";
 561                                         regulator-min-microvolt = <2250000>;
 562                                         regulator-max-microvolt = <2750000>;
 563                                         regulator-always-on;
 564                                         anatop-reg-offset = <0x130>;
 565                                         anatop-vol-bit-shift = <8>;
 566                                         anatop-vol-bit-width = <5>;
 567                                         anatop-min-bit-val = <0>;
 568                                         anatop-min-voltage = <2100000>;
 569                                         anatop-max-voltage = <2850000>;
 570                                         anatop-enable-bit = <0>;
 571                                 };
 572
 573                                 reg_arm: regulator-vddcore {
 574                                         compatible = "fsl,anatop-regulator";
 575                                         regulator-name = "vddarm";
 576                                         regulator-min-microvolt = <725000>;
 577                                         regulator-max-microvolt = <1450000>;
 578                                         regulator-always-on;
 579                                         anatop-reg-offset = <0x140>;
 580                                         anatop-vol-bit-shift = <0>;
 581                                         anatop-vol-bit-width = <5>;
 582                                         anatop-delay-reg-offset = <0x170>;
 583                                         anatop-delay-bit-shift = <24>;
 584                                         anatop-delay-bit-width = <2>;
 585                                         anatop-min-bit-val = <1>;
 586                                         anatop-min-voltage = <725000>;
 587                                         anatop-max-voltage = <1450000>;
 588                                 };
 589
 590                                 reg_pu: regulator-vddpu {
 591                                         compatible = "fsl,anatop-regulator";
 592                                         regulator-name = "vddpu";
 593                                         regulator-min-microvolt = <725000>;
 594                                         regulator-max-microvolt = <1450000>;
 595                                         anatop-reg-offset = <0x140>;
 596                                         anatop-vol-bit-shift = <9>;
 597                                         anatop-vol-bit-width = <5>;
 598                                         anatop-delay-reg-offset = <0x170>;
 599                                         anatop-delay-bit-shift = <26>;
 600                                         anatop-delay-bit-width = <2>;
 601                                         anatop-min-bit-val = <1>;
 602                                         anatop-min-voltage = <725000>;
 603                                         anatop-max-voltage = <1450000>;
 604                                 };
 605
 606                                 reg_soc: regulator-vddsoc {
 607                                         compatible = "fsl,anatop-regulator";
 608                                         regulator-name = "vddsoc";
 609                                         regulator-min-microvolt = <725000>;
 610                                         regulator-max-microvolt = <1450000>;
 611                                         regulator-always-on;
 612                                         anatop-reg-offset = <0x140>;
 613                                         anatop-vol-bit-shift = <18>;
 614                                         anatop-vol-bit-width = <5>;
 615                                         anatop-delay-reg-offset = <0x170>;
 616                                         anatop-delay-bit-shift = <28>;
 617                                         anatop-delay-bit-width = <2>;
 618                                         anatop-min-bit-val = <1>;
 619                                         anatop-min-voltage = <725000>;
 620                                         anatop-max-voltage = <1450000>;
 621                                 };
 622
 623                                 tempmon: tempmon {
 624                                         compatible = "fsl,imx6q-tempmon";
 625                                         interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 626                                         interrupt-parent = <&gpc>;
 627                                         fsl,tempmon = <&anatop>;
 628                                         nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 629                                         nvmem-cell-names = "calib", "temp_grade";
 630                                         clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 631                                 };
 632                         };
 633
 634                         usbphy1: usbphy@20c9000 {
 635                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 636                                 reg = <0x020c9000 0x1000>;
 637                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 638                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 639                                 fsl,anatop = <&anatop>;
 640                         };
 641
 642                         usbphy2: usbphy@20ca000 {
 643                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 644                                 reg = <0x020ca000 0x1000>;
 645                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 646                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 647                                 fsl,anatop = <&anatop>;
 648                         };
 649
 650                         snvs: snvs@20cc000 {
 651                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 652                                 reg = <0x020cc000 0x4000>;
 653
 654                                 snvs_rtc: snvs-rtc-lp {
 655                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 656                                         regmap = <&snvs>;
 657                                         offset = <0x34>;
 658                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 659                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 660                                 };
 661
 662                                 snvs_poweroff: snvs-poweroff {
 663                                         compatible = "syscon-poweroff";
 664                                         regmap = <&snvs>;
 665                                         offset = <0x38>;
 666                                         value = <0x60>;
 667                                         mask = <0x60>;
 668                                         status = "disabled";
 669                                 };
 670                         };
 671
 672                         epit1: epit@20d0000 {
 673                                 reg = <0x020d0000 0x4000>;
 674                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 675                         };
 676
 677                         epit2: epit@20d4000 {
 678                                 reg = <0x020d4000 0x4000>;
 679                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 680                         };
 681
 682                         src: reset-controller@20d8000 {
 683                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 684                                 reg = <0x020d8000 0x4000>;
 685                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 686                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 687                                 #reset-cells = <1>;
 688                         };
 689
 690                         gpc: gpc@20dc000 {
 691                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 692                                 reg = <0x020dc000 0x4000>;
 693                                 interrupt-controller;
 694                                 #interrupt-cells = <3>;
 695                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 696                                 interrupt-parent = <&intc>;
 697                                 clocks = <&clks IMX6SL_CLK_IPG>;
 698                                 clock-names = "ipg";
 699
 700                                 pgc {
 701                                         #address-cells = <1>;
 702                                         #size-cells = <0>;
 703
 704                                         power-domain@0 {
 705                                                 reg = <0>;
 706                                                 #power-domain-cells = <0>;
 707                                         };
 708
 709                                         pd_pu: power-domain@1 {
 710                                                 reg = <1>;
 711                                                 #power-domain-cells = <0>;
 712                                                 power-supply = <&reg_pu>;
 713                                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 714                                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 715                                         };
 716
 717                                         pd_disp: power-domain@2 {
 718                                                 reg = <2>;
 719                                                 #power-domain-cells = <0>;
 720                                                 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
 721                                                          <&clks IMX6SL_CLK_LCDIF_PIX>,
 722                                                          <&clks IMX6SL_CLK_EPDC_AXI>,
 723                                                          <&clks IMX6SL_CLK_EPDC_PIX>,
 724                                                          <&clks IMX6SL_CLK_PXP_AXI>;
 725                                         };
 726                                 };
 727                         };
 728
 729                         gpr: iomuxc-gpr@20e0000 {
 730                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 731                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 732                                 reg = <0x020e0000 0x38>;
 733                         };
 734
 735                         iomuxc: pinctrl@20e0000 {
 736                                 compatible = "fsl,imx6sl-iomuxc";
 737                                 reg = <0x020e0000 0x4000>;
 738                         };
 739
 740                         csi: csi@20e4000 {
 741                                 reg = <0x020e4000 0x4000>;
 742                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 743                         };
 744
 745                         spdc: spdc@20e8000 {
 746                                 reg = <0x020e8000 0x4000>;
 747                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 748                         };
 749
 750                         sdma: sdma@20ec000 {
 751                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 752                                 reg = <0x020ec000 0x4000>;
 753                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 754                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 755                                          <&clks IMX6SL_CLK_AHB>;
 756                                 clock-names = "ipg", "ahb";
 757                                 #dma-cells = <3>;
 758                                 /* imx6sl reuses imx6q sdma firmware */
 759                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 760                         };
 761
 762                         pxp: pxp@20f0000 {
 763                                 reg = <0x020f0000 0x4000>;
 764                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 765                         };
 766
 767                         epdc: epdc@20f4000 {
 768                                 reg = <0x020f4000 0x4000>;
 769                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 770                         };
 771
 772                         lcdif: lcdif@20f8000 {
 773                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 774                                 reg = <0x020f8000 0x4000>;
 775                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 776                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 777                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 778                                          <&clks IMX6SL_CLK_DUMMY>;
 779                                 clock-names = "pix", "axi", "disp_axi";
 780                                 status = "disabled";
 781                                 power-domains = <&pd_disp>;
 782                         };
 783
 784                         dcp: crypto@20fc000 {
 785                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 786                                 reg = <0x020fc000 0x4000>;
 787                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 788                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 789                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 790                         };
 791                 };
 792
 793                 aips2: bus@2100000 {
 794                         compatible = "fsl,aips-bus", "simple-bus";
 795                         #address-cells = <1>;
 796                         #size-cells = <1>;
 797                         reg = <0x02100000 0x100000>;
 798                         ranges;
 799
 800                         usbotg1: usb@2184000 {
 801                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 802                                 reg = <0x02184000 0x200>;
 803                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 805                                 fsl,usbphy = <&usbphy1>;
 806                                 fsl,usbmisc = <&usbmisc 0>;
 807                                 ahb-burst-config = <0x0>;
 808                                 tx-burst-size-dword = <0x10>;
 809                                 rx-burst-size-dword = <0x10>;
 810                                 status = "disabled";
 811                         };
 812
 813                         usbotg2: usb@2184200 {
 814                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 815                                 reg = <0x02184200 0x200>;
 816                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 817                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 818                                 fsl,usbphy = <&usbphy2>;
 819                                 fsl,usbmisc = <&usbmisc 1>;
 820                                 ahb-burst-config = <0x0>;
 821                                 tx-burst-size-dword = <0x10>;
 822                                 rx-burst-size-dword = <0x10>;
 823                                 status = "disabled";
 824                         };
 825
 826                         usbh: usb@2184400 {
 827                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 828                                 reg = <0x02184400 0x200>;
 829                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 830                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 831                                 fsl,usbphy = <&usbphynop1>;
 832                                 phy_type = "hsic";
 833                                 fsl,usbmisc = <&usbmisc 2>;
 834                                 dr_mode = "host";
 835                                 ahb-burst-config = <0x0>;
 836                                 tx-burst-size-dword = <0x10>;
 837                                 rx-burst-size-dword = <0x10>;
 838                                 status = "disabled";
 839                         };
 840
 841                         usbmisc: usbmisc@2184800 {
 842                                 #index-cells = <1>;
 843                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 844                                 reg = <0x02184800 0x200>;
 845                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 846                         };
 847
 848                         fec: ethernet@2188000 {
 849                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 850                                 reg = <0x02188000 0x4000>;
 851                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&clks IMX6SL_CLK_ENET>,
 853                                          <&clks IMX6SL_CLK_ENET_REF>;
 854                                 clock-names = "ipg", "ahb";
 855                                 status = "disabled";
 856                         };
 857
 858                         usdhc1: mmc@2190000 {
 859                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 860                                 reg = <0x02190000 0x4000>;
 861                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 862                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 863                                          <&clks IMX6SL_CLK_USDHC1>,
 864                                          <&clks IMX6SL_CLK_USDHC1>;
 865                                 clock-names = "ipg", "ahb", "per";
 866                                 bus-width = <4>;
 867                                 status = "disabled";
 868                         };
 869
 870                         usdhc2: mmc@2194000 {
 871                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 872                                 reg = <0x02194000 0x4000>;
 873                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 875                                          <&clks IMX6SL_CLK_USDHC2>,
 876                                          <&clks IMX6SL_CLK_USDHC2>;
 877                                 clock-names = "ipg", "ahb", "per";
 878                                 bus-width = <4>;
 879                                 status = "disabled";
 880                         };
 881
 882                         usdhc3: mmc@2198000 {
 883                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 884                                 reg = <0x02198000 0x4000>;
 885                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 886                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 887                                          <&clks IMX6SL_CLK_USDHC3>,
 888                                          <&clks IMX6SL_CLK_USDHC3>;
 889                                 clock-names = "ipg", "ahb", "per";
 890                                 bus-width = <4>;
 891                                 status = "disabled";
 892                         };
 893
 894                         usdhc4: mmc@219c000 {
 895                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 896                                 reg = <0x0219c000 0x4000>;
 897                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 898                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 899                                          <&clks IMX6SL_CLK_USDHC4>,
 900                                          <&clks IMX6SL_CLK_USDHC4>;
 901                                 clock-names = "ipg", "ahb", "per";
 902                                 bus-width = <4>;
 903                                 status = "disabled";
 904                         };
 905
 906                         i2c1: i2c@21a0000 {
 907                                 #address-cells = <1>;
 908                                 #size-cells = <0>;
 909                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 910                                 reg = <0x021a0000 0x4000>;
 911                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 912                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 913                                 status = "disabled";
 914                         };
 915
 916                         i2c2: i2c@21a4000 {
 917                                 #address-cells = <1>;
 918                                 #size-cells = <0>;
 919                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 920                                 reg = <0x021a4000 0x4000>;
 921                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 922                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 923                                 status = "disabled";
 924                         };
 925
 926                         i2c3: i2c@21a8000 {
 927                                 #address-cells = <1>;
 928                                 #size-cells = <0>;
 929                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 930                                 reg = <0x021a8000 0x4000>;
 931                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 932                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 933                                 status = "disabled";
 934                         };
 935
 936                         memory-controller@21b0000 {
 937                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 938                                 reg = <0x021b0000 0x4000>;
 939                                 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
 940                         };
 941
 942                         rngb: rngb@21b4000 {
 943                                 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
 944                                 reg = <0x021b4000 0x4000>;
 945                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 946                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 947                         };
 948
 949                         weim: weim@21b8000 {
 950                                 #address-cells = <2>;
 951                                 #size-cells = <1>;
 952                                 reg = <0x021b8000 0x4000>;
 953                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 954                                 fsl,weim-cs-gpr = <&gpr>;
 955                                 status = "disabled";
 956                         };
 957
 958                         ocotp: efuse@21bc000 {
 959                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 960                                 reg = <0x021bc000 0x4000>;
 961                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 962                                 #address-cells = <1>;
 963                                 #size-cells = <1>;
 964
 965                                 cpu_speed_grade: speed-grade@10 {
 966                                         reg = <0x10 4>;
 967                                 };
 968
 969                                 tempmon_calib: calib@38 {
 970                                         reg = <0x38 4>;
 971                                 };
 972
 973                                 tempmon_temp_grade: temp-grade@20 {
 974                                         reg = <0x20 4>;
 975                                 };
 976                         };
 977
 978                         audmux: audmux@21d8000 {
 979                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 980                                 reg = <0x021d8000 0x4000>;
 981                                 status = "disabled";
 982                         };
 983                 };
 984
 985                 gpu_2d: gpu@2200000 {
 986                         compatible = "vivante,gc";
 987                         reg = <0x02200000 0x4000>;
 988                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 989                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 990                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 991                         clock-names = "bus", "core";
 992                         power-domains = <&pd_pu>;
 993                 };
 994
 995                 gpu_vg: gpu@2204000 {
 996                         compatible = "vivante,gc";
 997                         reg = <0x02204000 0x4000>;
 998                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 999                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
1000                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
1001                         clock-names = "bus", "core";
1002                         power-domains = <&pd_pu>;
1003                 };
1004         };
1005 };