arch/arm/boot/dts/imx6qp.dtsi

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "imx6q.dtsi"
  44
  45 / {
  46         soc {
  47                 ocram2: sram@00940000 {
  48                         compatible = "mmio-sram";
  49                         reg = <0x00940000 0x20000>;
  50                         ranges = <0 0x00940000 0x20000>;
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  54                 };
  55
  56                 ocram3: sram@00960000 {
  57                         compatible = "mmio-sram";
  58                         reg = <0x00960000 0x20000>;
  59                         ranges = <0 0x00960000 0x20000>;
  60                         #address-cells = <1>;
  61                         #size-cells = <1>;
  62                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  63                 };
  64
  65                 aips-bus@02100000 {
  66                         pre1: pre@21c8000 {
  67                                 compatible = "fsl,imx6qp-pre";
  68                                 reg = <0x021c8000 0x1000>;
  69                                 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
  70                                 clocks = <&clks IMX6QDL_CLK_PRE0>;
  71                                 clock-names = "axi";
  72                                 fsl,iram = <&ocram2>;
  73                         };
  74
  75                         pre2: pre@21c9000 {
  76                                 compatible = "fsl,imx6qp-pre";
  77                                 reg = <0x021c9000 0x1000>;
  78                                 interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
  79                                 clocks = <&clks IMX6QDL_CLK_PRE1>;
  80                                 clock-names = "axi";
  81                                 fsl,iram = <&ocram2>;
  82                         };
  83
  84                         pre3: pre@21ca000 {
  85                                 compatible = "fsl,imx6qp-pre";
  86                                 reg = <0x021ca000 0x1000>;
  87                                 interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
  88                                 clocks = <&clks IMX6QDL_CLK_PRE2>;
  89                                 clock-names = "axi";
  90                                 fsl,iram = <&ocram3>;
  91                         };
  92
  93                         pre4: pre@21cb000 {
  94                                 compatible = "fsl,imx6qp-pre";
  95                                 reg = <0x021cb000 0x1000>;
  96                                 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
  97                                 clocks = <&clks IMX6QDL_CLK_PRE3>;
  98                                 clock-names = "axi";
  99                                 fsl,iram = <&ocram3>;
 100                         };
 101
 102                         prg1: prg@21cc000 {
 103                                 compatible = "fsl,imx6qp-prg";
 104                                 reg = <0x021cc000 0x1000>;
 105                                 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
 106                                          <&clks IMX6QDL_CLK_PRG0_AXI>;
 107                                 clock-names = "ipg", "axi";
 108                                 fsl,pres = <&pre1>, <&pre2>, <&pre3>;
 109                         };
 110
 111                         prg2: prg@21cd000 {
 112                                 compatible = "fsl,imx6qp-prg";
 113                                 reg = <0x021cd000 0x1000>;
 114                                 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
 115                                          <&clks IMX6QDL_CLK_PRG1_AXI>;
 116                                 clock-names = "ipg", "axi";
 117                                 fsl,pres = <&pre4>, <&pre2>, <&pre3>;
 118                         };
 119                 };
 120         };
 121 };
 122
 123 &fec {
 124         /delete-property/interrupts-extended;
 125         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
 126                      <0 119 IRQ_TYPE_LEVEL_HIGH>;
 127 };
 128
 129 &gpc {
 130         compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
 131 };
 132
 133 &ipu1 {
 134         compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
 135         fsl,prg = <&prg1>;
 136 };
 137
 138 &ipu2 {
 139         compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
 140         fsl,prg = <&prg2>;
 141 };
 142
 143 &ldb {
 144         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 145                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 146                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 147                  <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
 148         clock-names = "di0_pll", "di1_pll",
 149                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 150                       "di0", "di1";
 151 };
 152
 153 &mmdc0 {
 154         compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
 155 };
 156
 157 &pcie {
 158         compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
 159 };