arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2012 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         chosen {
  10                 stdout-path = &uart4;
  11         };
  12
  13         memory@10000000 {
  14                 reg = <0x10000000 0x80000000>;
  15         };
  16
  17         leds {
  18                 compatible = "gpio-leds";
  19                 pinctrl-names = "default";
  20                 pinctrl-0 = <&pinctrl_gpio_leds>;
  21
  22                 user {
  23                         label = "debug";
  24                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  25                 };
  26         };
  27
  28         clocks {
  29                 codec_osc: anaclk2 {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <24576000>;
  33                 };
  34         };
  35
  36         regulators {
  37                 compatible = "simple-bus";
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 reg_audio: regulator@0 {
  42                         compatible = "regulator-fixed";
  43                         reg = <0>;
  44                         regulator-name = "cs42888_supply";
  45                         regulator-min-microvolt = <3300000>;
  46                         regulator-max-microvolt = <3300000>;
  47                         regulator-always-on;
  48                 };
  49
  50                 reg_usb_h1_vbus: regulator@1 {
  51                         compatible = "regulator-fixed";
  52                         reg = <1>;
  53                         regulator-name = "usb_h1_vbus";
  54                         regulator-min-microvolt = <5000000>;
  55                         regulator-max-microvolt = <5000000>;
  56                         gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
  57                         enable-active-high;
  58                 };
  59
  60                 reg_usb_otg_vbus: regulator@2 {
  61                         compatible = "regulator-fixed";
  62                         reg = <2>;
  63                         regulator-name = "usb_otg_vbus";
  64                         regulator-min-microvolt = <5000000>;
  65                         regulator-max-microvolt = <5000000>;
  66                         gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
  67                         enable-active-high;
  68                 };
  69         };
  70
  71         sound-cs42888 {
  72                 compatible = "fsl,imx6-sabreauto-cs42888",
  73                         "fsl,imx-audio-cs42888";
  74                 model = "imx-cs42888";
  75                 audio-cpu = <&esai>;
  76                 audio-asrc = <&asrc>;
  77                 audio-codec = <&codec>;
  78                 audio-routing =
  79                         "Line Out Jack", "AOUT1L",
  80                         "Line Out Jack", "AOUT1R",
  81                         "Line Out Jack", "AOUT2L",
  82                         "Line Out Jack", "AOUT2R",
  83                         "Line Out Jack", "AOUT3L",
  84                         "Line Out Jack", "AOUT3R",
  85                         "Line Out Jack", "AOUT4L",
  86                         "Line Out Jack", "AOUT4R",
  87                         "AIN1L", "Line In Jack",
  88                         "AIN1R", "Line In Jack",
  89                         "AIN2L", "Line In Jack",
  90                         "AIN2R", "Line In Jack";
  91         };
  92
  93         sound-spdif {
  94                 compatible = "fsl,imx-audio-spdif",
  95                            "fsl,imx-sabreauto-spdif";
  96                 model = "imx-spdif";
  97                 spdif-controller = <&spdif>;
  98                 spdif-in;
  99         };
 100
 101         backlight {
 102                 compatible = "pwm-backlight";
 103                 pwms = <&pwm3 0 5000000>;
 104                 brightness-levels = <0 4 8 16 32 64 128 255>;
 105                 default-brightness-level = <7>;
 106                 status = "okay";
 107         };
 108
 109         i2cmux {
 110                 compatible = "i2c-mux-gpio";
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_i2c3mux>;
 115                 mux-gpios = <&gpio5 4 0>;
 116                 i2c-parent = <&i2c3>;
 117                 idle-state = <0>;
 118
 119                 i2c@1 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         reg = <1>;
 123
 124                         adv7180: camera@21 {
 125                                 compatible = "adi,adv7180";
 126                                 reg = <0x21>;
 127                                 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
 128                                 interrupt-parent = <&gpio1>;
 129                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 130
 131                                 port {
 132                                         adv7180_to_ipu1_csi0_mux: endpoint {
 133                                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 134                                                 bus-width = <8>;
 135                                         };
 136                                 };
 137                         };
 138
 139                         max7310_a: gpio@30 {
 140                                 compatible = "maxim,max7310";
 141                                 reg = <0x30>;
 142                                 gpio-controller;
 143                                 #gpio-cells = <2>;
 144                         };
 145
 146                         max7310_b: gpio@32 {
 147                                 compatible = "maxim,max7310";
 148                                 reg = <0x32>;
 149                                 gpio-controller;
 150                                 #gpio-cells = <2>;
 151                                 pinctrl-names = "default";
 152                                 pinctrl-0 = <&pinctrl_max7310>;
 153                                 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 154                         };
 155
 156                         max7310_c: gpio@34 {
 157                                 compatible = "maxim,max7310";
 158                                 reg = <0x34>;
 159                                 gpio-controller;
 160                                 #gpio-cells = <2>;
 161                         };
 162
 163                         light-sensor@44 {
 164                                 compatible = "isil,isl29023";
 165                                 reg = <0x44>;
 166                                 interrupt-parent = <&gpio5>;
 167                                 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
 168                         };
 169
 170                         magnetometer@e {
 171                                 compatible = "fsl,mag3110";
 172                                 reg = <0x0e>;
 173                                 interrupt-parent = <&gpio2>;
 174                                 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
 175                         };
 176
 177                         accelerometer@1c {
 178                                 compatible = "fsl,mma8451";
 179                                 reg = <0x1c>;
 180                                 pinctrl-names = "default";
 181                                 pinctrl-0 = <&pinctrl_mma8451_int>;
 182                                 interrupt-parent = <&gpio6>;
 183                                 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
 184                         };
 185                 };
 186         };
 187 };
 188
 189 &ipu1_csi0_from_ipu1_csi0_mux {
 190         bus-width = <8>;
 191 };
 192
 193 &ipu1_csi0_mux_from_parallel_sensor {
 194         remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
 195         bus-width = <8>;
 196 };
 197
 198 &ipu1_csi0 {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 201 };
 202
 203 &clks {
 204         assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 205                           <&clks IMX6QDL_PLL4_BYPASS>,
 206                           <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 207                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 208                           <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
 209         assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
 210                                  <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 211                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 212                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 213         assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
 214 };
 215
 216 &ecspi1 {
 217         cs-gpios = <&gpio3 19 0>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
 220         status = "disabled"; /* pin conflict with WEIM NOR */
 221
 222         flash: m25p80@0 {
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 compatible = "st,m25p32", "jedec,spi-nor";
 226                 spi-max-frequency = <20000000>;
 227                 reg = <0>;
 228         };
 229 };
 230
 231 &esai {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_esai>;
 234         assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
 235                           <&clks IMX6QDL_CLK_ESAI_EXTAL>;
 236         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
 237         assigned-clock-rates = <0>, <24576000>;
 238         status = "okay";
 239 };
 240
 241 &fec {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_enet>;
 244         phy-mode = "rgmii";
 245         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 246                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 247         fsl,err006687-workaround-present;
 248         status = "okay";
 249 };
 250
 251 &gpmi {
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pinctrl_gpmi_nand>;
 254         status = "okay";
 255 };
 256
 257 &hdmi {
 258         pinctrl-names = "default";
 259         pinctrl-0 = <&pinctrl_hdmi_cec>;
 260         ddc-i2c-bus = <&i2c2>;
 261         status = "okay";
 262 };
 263
 264 &i2c2 {
 265         clock-frequency = <100000>;
 266         pinctrl-names = "default";
 267         pinctrl-0 = <&pinctrl_i2c2>;
 268         status = "okay";
 269
 270         pmic: pfuze100@8 {
 271                 compatible = "fsl,pfuze100";
 272                 reg = <0x08>;
 273
 274                 regulators {
 275                         sw1a_reg: sw1ab {
 276                                 regulator-min-microvolt = <300000>;
 277                                 regulator-max-microvolt = <1875000>;
 278                                 regulator-boot-on;
 279                                 regulator-always-on;
 280                                 regulator-ramp-delay = <6250>;
 281                         };
 282
 283                         sw1c_reg: sw1c {
 284                                 regulator-min-microvolt = <300000>;
 285                                 regulator-max-microvolt = <1875000>;
 286                                 regulator-boot-on;
 287                                 regulator-always-on;
 288                                 regulator-ramp-delay = <6250>;
 289                         };
 290
 291                         sw2_reg: sw2 {
 292                                 regulator-min-microvolt = <800000>;
 293                                 regulator-max-microvolt = <3300000>;
 294                                 regulator-boot-on;
 295                                 regulator-always-on;
 296                         };
 297
 298                         sw3a_reg: sw3a {
 299                                 regulator-min-microvolt = <400000>;
 300                                 regulator-max-microvolt = <1975000>;
 301                                 regulator-boot-on;
 302                                 regulator-always-on;
 303                         };
 304
 305                         sw3b_reg: sw3b {
 306                                 regulator-min-microvolt = <400000>;
 307                                 regulator-max-microvolt = <1975000>;
 308                                 regulator-boot-on;
 309                                 regulator-always-on;
 310                         };
 311
 312                         sw4_reg: sw4 {
 313                                 regulator-min-microvolt = <800000>;
 314                                 regulator-max-microvolt = <3300000>;
 315                         };
 316
 317                         swbst_reg: swbst {
 318                                 regulator-min-microvolt = <5000000>;
 319                                 regulator-max-microvolt = <5150000>;
 320                         };
 321
 322                         snvs_reg: vsnvs {
 323                                 regulator-min-microvolt = <1000000>;
 324                                 regulator-max-microvolt = <3000000>;
 325                                 regulator-boot-on;
 326                                 regulator-always-on;
 327                         };
 328
 329                         vref_reg: vrefddr {
 330                                 regulator-boot-on;
 331                                 regulator-always-on;
 332                         };
 333
 334                         vgen1_reg: vgen1 {
 335                                 regulator-min-microvolt = <800000>;
 336                                 regulator-max-microvolt = <1550000>;
 337                         };
 338
 339                         vgen2_reg: vgen2 {
 340                                 regulator-min-microvolt = <800000>;
 341                                 regulator-max-microvolt = <1550000>;
 342                         };
 343
 344                         vgen3_reg: vgen3 {
 345                                 regulator-min-microvolt = <1800000>;
 346                                 regulator-max-microvolt = <3300000>;
 347                         };
 348
 349                         vgen4_reg: vgen4 {
 350                                 regulator-min-microvolt = <1800000>;
 351                                 regulator-max-microvolt = <3300000>;
 352                                 regulator-always-on;
 353                         };
 354
 355                         vgen5_reg: vgen5 {
 356                                 regulator-min-microvolt = <1800000>;
 357                                 regulator-max-microvolt = <3300000>;
 358                                 regulator-always-on;
 359                         };
 360
 361                         vgen6_reg: vgen6 {
 362                                 regulator-min-microvolt = <1800000>;
 363                                 regulator-max-microvolt = <3300000>;
 364                                 regulator-always-on;
 365                         };
 366                 };
 367         };
 368
 369         codec: cs42888@48 {
 370                 compatible = "cirrus,cs42888";
 371                 reg = <0x48>;
 372                 clocks = <&codec_osc>;
 373                 clock-names = "mclk";
 374                 VA-supply = <&reg_audio>;
 375                 VD-supply = <&reg_audio>;
 376                 VLS-supply = <&reg_audio>;
 377                 VLC-supply = <&reg_audio>;
 378         };
 379
 380 };
 381
 382 &i2c3 {
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_i2c3>;
 385         status = "okay";
 386 };
 387
 388 &iomuxc {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_hog>;
 391
 392         imx6qdl-sabreauto {
 393                 pinctrl_hog: hoggrp {
 394                         fsl,pins = <
 395                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 396                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 397                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 398                         >;
 399                 };
 400
 401                 pinctrl_ecspi1: ecspi1grp {
 402                         fsl,pins = <
 403                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 404                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 405                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 406                         >;
 407                 };
 408
 409                 pinctrl_ecspi1_cs: ecspi1cs {
 410                         fsl,pins = <
 411                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 412                         >;
 413                 };
 414
 415                 pinctrl_enet: enetgrp {
 416                         fsl,pins = <
 417                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 418                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 419                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 420                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 421                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 422                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 423                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 424                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 425                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 426                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 427                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 428                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 429                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 430                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 431                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 432                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 433                         >;
 434                 };
 435
 436                 pinctrl_esai: esaigrp {
 437                         fsl,pins = <
 438                                 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
 439                                 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
 440                                 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
 441                                 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
 442                                 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
 443                                 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
 444                                 MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
 445                                 MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
 446                                 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
 447                                 MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
 448                         >;
 449                 };
 450
 451                 pinctrl_gpio_leds: gpioledsgrp {
 452                         fsl,pins = <
 453                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 454                         >;
 455                 };
 456
 457                 pinctrl_gpmi_nand: gpminandgrp {
 458                         fsl,pins = <
 459                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 460                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 461                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 462                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 463                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 464                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 465                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 466                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 467                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 468                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 469                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 470                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 471                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 472                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 473                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 474                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 475                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 476                         >;
 477                 };
 478
 479                 pinctrl_hdmi_cec: hdmicecgrp {
 480                         fsl,pins = <
 481                                 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1f8b0
 482                         >;
 483                 };
 484
 485                 pinctrl_i2c2: i2c2grp {
 486                         fsl,pins = <
 487                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 488                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 489                         >;
 490                 };
 491
 492                 pinctrl_i2c3: i2c3grp {
 493                         fsl,pins = <
 494                                 MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 495                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 496                         >;
 497                 };
 498
 499                 pinctrl_i2c3mux: i2c3muxgrp {
 500                         fsl,pins = <
 501                                 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
 502                         >;
 503                 };
 504
 505                 pinctrl_ipu1_csi0: ipu1csi0grp {
 506                         fsl,pins = <
 507                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0
 508                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0
 509                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0
 510                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0
 511                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0
 512                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0
 513                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0
 514                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0
 515                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
 516                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0
 517                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0
 518                         >;
 519                 };
 520
 521                 pinctrl_max7310: max7310grp {
 522                         fsl,pins = <
 523                                 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
 524                         >;
 525                 };
 526
 527                 pinctrl_mma8451_int: mma8451intgrp {
 528                         fsl,pins = <
 529                                 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0xb0b1
 530                         >;
 531                 };
 532
 533                 pinctrl_pwm3: pwm1grp {
 534                         fsl,pins = <
 535                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 536                         >;
 537                 };
 538
 539                 pinctrl_gpt_input_capture0: gptinputcapture0grp {
 540                         fsl,pins = <
 541                                 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1       0x1b0b0
 542                         >;
 543                 };
 544
 545                 pinctrl_gpt_input_capture1: gptinputcapture1grp {
 546                         fsl,pins = <
 547                                 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2       0x1b0b0
 548                         >;
 549                 };
 550
 551                 pinctrl_spdif: spdifgrp {
 552                         fsl,pins = <
 553                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 554                         >;
 555                 };
 556
 557                 pinctrl_uart4: uart4grp {
 558                         fsl,pins = <
 559                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 560                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 561                         >;
 562                 };
 563
 564                 pinctrl_usbotg: usbotggrp {
 565                         fsl,pins = <
 566                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 567                         >;
 568                 };
 569
 570                 pinctrl_usdhc3: usdhc3grp {
 571                         fsl,pins = <
 572                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 573                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 574                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 575                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 576                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 577                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 578                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 579                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 580                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 581                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 582                         >;
 583                 };
 584
 585                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 586                         fsl,pins = <
 587                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 588                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 589                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 590                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 591                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 592                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 593                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 594                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 595                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 596                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 597                         >;
 598                 };
 599
 600                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 601                         fsl,pins = <
 602                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 603                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 604                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 605                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 606                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 607                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 608                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 609                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 610                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 611                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 612                         >;
 613                 };
 614
 615                 pinctrl_weim_cs0: weimcs0grp {
 616                         fsl,pins = <
 617                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 618                         >;
 619                 };
 620
 621                 pinctrl_weim_nor: weimnorgrp {
 622                         fsl,pins = <
 623                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 624                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 625                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 626                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 627                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 628                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 629                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 630                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 631                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 632                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 633                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 634                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 635                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 636                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 637                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 638                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 639                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 640                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 641                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 642                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 643                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 644                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 645                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 646                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 647                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 648                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 649                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 650                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 651                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 652                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 653                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 654                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 655                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 656                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 657                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 658                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 659                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 660                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 661                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 662                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 663                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 664                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 665                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 666                         >;
 667                 };
 668         };
 669 };
 670
 671 &ldb {
 672         status = "okay";
 673
 674         lvds-channel@0 {
 675                 fsl,data-mapping = "spwg";
 676                 fsl,data-width = <18>;
 677                 status = "okay";
 678
 679                 display-timings {
 680                         native-mode = <&timing0>;
 681                         timing0: hsd100pxn1 {
 682                                 clock-frequency = <65000000>;
 683                                 hactive = <1024>;
 684                                 vactive = <768>;
 685                                 hback-porch = <220>;
 686                                 hfront-porch = <40>;
 687                                 vback-porch = <21>;
 688                                 vfront-porch = <7>;
 689                                 hsync-len = <60>;
 690                                 vsync-len = <10>;
 691                         };
 692                 };
 693         };
 694 };
 695
 696 &pwm3 {
 697         pinctrl-names = "default";
 698         pinctrl-0 = <&pinctrl_pwm3>;
 699         status = "okay";
 700 };
 701
 702 &spdif {
 703         pinctrl-names = "default";
 704         pinctrl-0 = <&pinctrl_spdif>;
 705         status = "okay";
 706 };
 707
 708 &uart4 {
 709         pinctrl-names = "default";
 710         pinctrl-0 = <&pinctrl_uart4>;
 711         status = "okay";
 712 };
 713
 714 &usbh1 {
 715         vbus-supply = <&reg_usb_h1_vbus>;
 716         status = "okay";
 717 };
 718
 719 &usbotg {
 720         vbus-supply = <&reg_usb_otg_vbus>;
 721         pinctrl-names = "default";
 722         pinctrl-0 = <&pinctrl_usbotg>;
 723         status = "okay";
 724 };
 725
 726 &usdhc3 {
 727         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 728         pinctrl-0 = <&pinctrl_usdhc3>;
 729         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 730         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 731         cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
 732         wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 733         status = "okay";
 734 };
 735
 736 &weim {
 737         pinctrl-names = "default";
 738         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 739         ranges = <0 0 0x08000000 0x08000000>;
 740         status = "disabled"; /* pin conflict with SPI NOR */
 741
 742         nor@0,0 {
 743                 compatible = "cfi-flash";
 744                 reg = <0 0 0x02000000>;
 745                 #address-cells = <1>;
 746                 #size-cells = <1>;
 747                 bank-width = <2>;
 748                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 749                                 0x0000c000 0x1404a38e 0x00000000>;
 750         };
 751 };