1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Phytec phyFLEX-i.MX6 Quad";
10 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
13 device_type = "memory";
14 reg = <0x10000000 0x80000000>;
18 compatible = "simple-bus";
22 reg_usb_otg_vbus: regulator@0 {
23 compatible = "regulator-fixed";
25 regulator-name = "usb_otg_vbus";
26 regulator-min-microvolt = <5000000>;
27 regulator-max-microvolt = <5000000>;
32 reg_usb_h1_vbus: regulator@1 {
33 compatible = "regulator-fixed";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_usbh1_vbus>;
37 regulator-name = "usb_h1_vbus";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_leds>;
48 compatible = "gpio-leds";
50 led_green: led-green {
51 label = "phyflex:green";
52 gpios = <&gpio1 30 0>;
56 label = "phyflex:red";
57 gpios = <&gpio2 31 0>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_audmux>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_flexcan1>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_ecspi3>;
78 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
81 compatible = "m25p80", "jedec,spi-nor";
82 spi-max-frequency = <20000000>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_enet>;
90 phy-handle = <ðphy>;
92 phy-reset-duration = <10>; /* in msecs */
93 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
94 phy-supply = <&vdd_eth_io_reg>;
101 ethphy: ethernet-phy@0 {
102 compatible = "ethernet-phy-ieee802.3-c22";
104 txc-skew-ps = <1680>;
105 rxc-skew-ps = <1860>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_gpmi_nand>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_i2c1>;
122 som_eeprom: eeprom@50 {
123 compatible = "catalyst,24c32", "atmel,24c32";
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_pmic>;
131 compatible = "dlg,da9063";
133 interrupt-parent = <&gpio2>;
134 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
135 interrupt-controller;
138 vddcore_reg: bcore1 {
139 regulator-min-microvolt = <730000>;
140 regulator-max-microvolt = <1380000>;
145 regulator-min-microvolt = <730000>;
146 regulator-max-microvolt = <1380000>;
151 regulator-min-microvolt = <1500000>;
152 regulator-max-microvolt = <1500000>;
157 regulator-min-microvolt = <3300000>;
158 regulator-max-microvolt = <3300000>;
162 vdd_buckmem_reg: bmem {
163 regulator-min-microvolt = <3300000>;
164 regulator-max-microvolt = <3300000>;
169 regulator-min-microvolt = <1200000>;
170 regulator-max-microvolt = <1200000>;
174 vdd_eth_io_reg: ldo4 {
175 regulator-min-microvolt = <2500000>;
176 regulator-max-microvolt = <2500000>;
180 vdd_mx6_snvs_reg: ldo5 {
181 regulator-min-microvolt = <3000000>;
182 regulator-max-microvolt = <3000000>;
186 vdd_3v3_pmic_io_reg: ldo6 {
187 regulator-min-microvolt = <3300000>;
188 regulator-max-microvolt = <3300000>;
193 regulator-min-microvolt = <3300000>;
194 regulator-max-microvolt = <3300000>;
198 regulator-min-microvolt = <3300000>;
199 regulator-max-microvolt = <3300000>;
202 vdd_mx6_high_reg: ldo11 {
203 regulator-min-microvolt = <3000000>;
204 regulator-max-microvolt = <3000000>;
210 compatible = "dlg,da9063-rtc";
213 da9063_wdog: watchdog {
214 compatible = "dlg,da9063-watchdog";
218 compatible = "dlg,da9063-onkey";
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_i2c2>;
227 clock-frequency = <100000>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c3>;
233 clock-frequency = <100000>;
237 imx6q-phytec-pfla02 {
238 pinctrl_ecspi3: ecspi3grp {
240 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
241 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
242 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
243 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */
247 pinctrl_enet: enetgrp {
249 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
250 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
251 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
252 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
253 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
254 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
255 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
256 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
257 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
258 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
259 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
260 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
261 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
262 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
263 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
264 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
265 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */
269 pinctrl_flexcan1: flexcan1grp {
271 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
272 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
276 pinctrl_gpmi_nand: gpminandgrp {
278 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
279 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
280 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
281 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
282 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
283 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
284 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
285 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
286 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
287 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
288 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
289 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
290 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
291 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
292 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
293 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
294 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
298 pinctrl_i2c1: i2c1grp {
300 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
301 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
305 pinctrl_i2c2: i2c2grp {
307 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
308 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
312 pinctrl_i2c3: i2c3grp {
314 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
315 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
319 pinctrl_leds: ledsgrp {
321 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
322 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
326 pinctrl_pcie: pciegrp {
327 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
330 pinctrl_pmic: pmicgrp {
331 fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */
334 pinctrl_uart3: uart3grp {
336 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
337 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
338 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
339 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
343 pinctrl_uart4: uart4grp {
345 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
346 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
350 pinctrl_usbh1_vbus: usbh1vbusgrp {
352 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
356 pinctrl_usbotg: usbotggrp {
358 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
359 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
360 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
364 pinctrl_usdhc2: usdhc2grp {
366 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
367 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
368 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
369 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
370 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
371 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
375 pinctrl_usdhc3: usdhc3grp {
377 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
378 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
379 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
380 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
381 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
382 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
386 pinctrl_usdhc3_cdwp: usdhc3cdwp {
388 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
389 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
393 pinctrl_audmux: audmuxgrp {
395 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
396 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
397 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
398 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_pcie>;
407 reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
412 vin-supply = <&vddcore_reg>;
416 vin-supply = <&vddsoc_reg>;
420 vin-supply = <&vddsoc_reg>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart3>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_uart4>;
437 vbus-supply = <®_usb_h1_vbus>;
442 vbus-supply = <®_usb_otg_vbus>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_usbotg>;
445 disable-over-current;
450 pinctrl-names = "default";
451 pinctrl-0 = <&pinctrl_usdhc2>;
452 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
453 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
454 vmmc-supply = <&vdd_sd1_reg>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_usdhc3
461 &pinctrl_usdhc3_cdwp>;
462 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
463 wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
464 vmmc-supply = <&vdd_sd0_reg>;