arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         model = "Phytec phyFLEX-i.MX6 Quad";
  10         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
  11
  12         memory@10000000 {
  13                 device_type = "memory";
  14                 reg = <0x10000000 0x80000000>;
  15         };
  16
  17         regulators {
  18                 compatible = "simple-bus";
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 reg_usb_otg_vbus: regulator@0 {
  23                         compatible = "regulator-fixed";
  24                         reg = <0>;
  25                         regulator-name = "usb_otg_vbus";
  26                         regulator-min-microvolt = <5000000>;
  27                         regulator-max-microvolt = <5000000>;
  28                         gpio = <&gpio4 15 0>;
  29                         enable-active-high;
  30                 };
  31
  32                 reg_usb_h1_vbus: regulator@1 {
  33                         compatible = "regulator-fixed";
  34                         pinctrl-names = "default";
  35                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
  36                         reg = <1>;
  37                         regulator-name = "usb_h1_vbus";
  38                         regulator-min-microvolt = <5000000>;
  39                         regulator-max-microvolt = <5000000>;
  40                         gpio = <&gpio1 0 0>;
  41                         enable-active-high;
  42                 };
  43         };
  44
  45         gpio_leds: leds {
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_leds>;
  48                 compatible = "gpio-leds";
  49
  50                 led_green: led-green {
  51                         label = "phyflex:green";
  52                         gpios = <&gpio1 30 0>;
  53                 };
  54
  55                 led_red: led-red {
  56                         label = "phyflex:red";
  57                         gpios = <&gpio2 31 0>;
  58                 };
  59         };
  60 };
  61
  62 &audmux {
  63         pinctrl-names = "default";
  64         pinctrl-0 = <&pinctrl_audmux>;
  65         status = "disabled";
  66 };
  67
  68 &can1 {
  69         pinctrl-names = "default";
  70         pinctrl-0 = <&pinctrl_flexcan1>;
  71         status = "disabled";
  72 };
  73
  74 &ecspi3 {
  75         pinctrl-names = "default";
  76         pinctrl-0 = <&pinctrl_ecspi3>;
  77         status = "okay";
  78         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  79
  80         som_flash: flash@0 {
  81                 compatible = "m25p80", "jedec,spi-nor";
  82                 spi-max-frequency = <20000000>;
  83                 reg = <0>;
  84         };
  85 };
  86
  87 &fec {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_enet>;
  90         phy-handle = <&ethphy>;
  91         phy-mode = "rgmii";
  92         phy-reset-duration = <10>; /* in msecs */
  93         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
  94         phy-supply = <&vdd_eth_io_reg>;
  95         status = "disabled";
  96
  97         fec_mdio: mdio {
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100
 101                 ethphy: ethernet-phy@0 {
 102                         compatible = "ethernet-phy-ieee802.3-c22";
 103                         reg = <0>;
 104                         txc-skew-ps = <1680>;
 105                         rxc-skew-ps = <1860>;
 106                 };
 107         };
 108 };
 109
 110 &gpmi {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_gpmi_nand>;
 113         nand-on-flash-bbt;
 114         status = "okay";
 115 };
 116
 117 &i2c1 {
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pinctrl_i2c1>;
 120         status = "okay";
 121
 122         som_eeprom: eeprom@50 {
 123                 compatible = "catalyst,24c32", "atmel,24c32";
 124                 pagesize = <32>;
 125                 reg = <0x50>;
 126         };
 127
 128         pmic@58 {
 129                 pinctrl-names = "default";
 130                 pinctrl-0 = <&pinctrl_pmic>;
 131                 compatible = "dlg,da9063";
 132                 reg = <0x58>;
 133                 interrupt-parent = <&gpio2>;
 134                 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
 135                 interrupt-controller;
 136
 137                 regulators {
 138                         vddcore_reg: bcore1 {
 139                                 regulator-min-microvolt = <730000>;
 140                                 regulator-max-microvolt = <1380000>;
 141                                 regulator-always-on;
 142                         };
 143
 144                         vddsoc_reg: bcore2 {
 145                                 regulator-min-microvolt = <730000>;
 146                                 regulator-max-microvolt = <1380000>;
 147                                 regulator-always-on;
 148                         };
 149
 150                         vdd_ddr3_reg: bpro {
 151                                 regulator-min-microvolt = <1500000>;
 152                                 regulator-max-microvolt = <1500000>;
 153                                 regulator-always-on;
 154                         };
 155
 156                         vdd_3v3_reg: bperi {
 157                                 regulator-min-microvolt = <3300000>;
 158                                 regulator-max-microvolt = <3300000>;
 159                                 regulator-always-on;
 160                         };
 161
 162                         vdd_buckmem_reg: bmem {
 163                                 regulator-min-microvolt = <3300000>;
 164                                 regulator-max-microvolt = <3300000>;
 165                                 regulator-always-on;
 166                         };
 167
 168                         vdd_eth_reg: bio {
 169                                 regulator-min-microvolt = <1200000>;
 170                                 regulator-max-microvolt = <1200000>;
 171                                 regulator-always-on;
 172                         };
 173
 174                         vdd_eth_io_reg: ldo4 {
 175                                 regulator-min-microvolt = <2500000>;
 176                                 regulator-max-microvolt = <2500000>;
 177                                 regulator-always-on;
 178                         };
 179
 180                         vdd_mx6_snvs_reg: ldo5 {
 181                                 regulator-min-microvolt = <3000000>;
 182                                 regulator-max-microvolt = <3000000>;
 183                                 regulator-always-on;
 184                         };
 185
 186                         vdd_3v3_pmic_io_reg: ldo6 {
 187                                 regulator-min-microvolt = <3300000>;
 188                                 regulator-max-microvolt = <3300000>;
 189                                 regulator-always-on;
 190                         };
 191
 192                         vdd_sd0_reg: ldo9 {
 193                                 regulator-min-microvolt = <3300000>;
 194                                 regulator-max-microvolt = <3300000>;
 195                         };
 196
 197                         vdd_sd1_reg: ldo10 {
 198                                 regulator-min-microvolt = <3300000>;
 199                                 regulator-max-microvolt = <3300000>;
 200                         };
 201
 202                         vdd_mx6_high_reg: ldo11 {
 203                                 regulator-min-microvolt = <3000000>;
 204                                 regulator-max-microvolt = <3000000>;
 205                                 regulator-always-on;
 206                         };
 207                 };
 208
 209                 da9063_rtc: rtc {
 210                         compatible = "dlg,da9063-rtc";
 211                 };
 212
 213                 da9063_wdog: watchdog {
 214                         compatible = "dlg,da9063-watchdog";
 215                 };
 216
 217                 onkey {
 218                         compatible = "dlg,da9063-onkey";
 219                         status = "disabled";
 220                 };
 221         };
 222 };
 223
 224 &i2c2 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_i2c2>;
 227         clock-frequency = <100000>;
 228 };
 229
 230 &i2c3 {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_i2c3>;
 233         clock-frequency = <100000>;
 234 };
 235
 236 &iomuxc {
 237         imx6q-phytec-pfla02 {
 238                 pinctrl_ecspi3: ecspi3grp {
 239                         fsl,pins = <
 240                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 241                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 242                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 243                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x80000000 /* CS0 */
 244                         >;
 245                 };
 246
 247                 pinctrl_enet: enetgrp {
 248                         fsl,pins = <
 249                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 250                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 251                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 252                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 253                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 254                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 255                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 256                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 257                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 258                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 259                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 260                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 261                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 262                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 263                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 264                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 265                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x80000000 /* Reset GPIO */
 266                         >;
 267                 };
 268
 269                 pinctrl_flexcan1: flexcan1grp {
 270                         fsl,pins = <
 271                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 272                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 273                         >;
 274                 };
 275
 276                 pinctrl_gpmi_nand: gpminandgrp {
 277                         fsl,pins = <
 278                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 279                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 280                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 281                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 282                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 283                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 284                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 285                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 286                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 287                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 288                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 289                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 290                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 291                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 292                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 293                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 294                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 295                         >;
 296                 };
 297
 298                 pinctrl_i2c1: i2c1grp {
 299                         fsl,pins = <
 300                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 301                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 302                         >;
 303                 };
 304
 305                 pinctrl_i2c2: i2c2grp {
 306                         fsl,pins = <
 307                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
 308                                 MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
 309                         >;
 310                 };
 311
 312                 pinctrl_i2c3: i2c3grp {
 313                         fsl,pins = <
 314                                 MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
 315                                 MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
 316                         >;
 317                 };
 318
 319                 pinctrl_leds: ledsgrp {
 320                         fsl,pins = <
 321                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x80000000 /* Green LED */
 322                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x80000000 /* Red LED */
 323                         >;
 324                 };
 325
 326                 pinctrl_pcie: pciegrp {
 327                         fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
 328                 };
 329
 330                 pinctrl_pmic: pmicgrp {
 331                         fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09     0x80000000>; /* PMIC interrupt */
 332                 };
 333
 334                 pinctrl_uart3: uart3grp {
 335                         fsl,pins = <
 336                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 337                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 338                                 MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 339                                 MX6QDL_PAD_EIM_D30__UART3_CTS_B         0x1b0b1
 340                         >;
 341                 };
 342
 343                 pinctrl_uart4: uart4grp {
 344                         fsl,pins = <
 345                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 346                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 347                         >;
 348                 };
 349
 350                 pinctrl_usbh1_vbus: usbh1vbusgrp {
 351                         fsl,pins = <
 352                                 MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 353                         >;
 354                 };
 355
 356                 pinctrl_usbotg: usbotggrp {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 359                                 MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
 360                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
 361                         >;
 362                 };
 363
 364                 pinctrl_usdhc2: usdhc2grp {
 365                         fsl,pins = <
 366                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 367                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 368                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 369                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 370                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 371                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 372                         >;
 373                 };
 374
 375                 pinctrl_usdhc3: usdhc3grp {
 376                         fsl,pins = <
 377                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 378                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 379                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 380                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 381                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 382                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 383                         >;
 384                 };
 385
 386                 pinctrl_usdhc3_cdwp: usdhc3cdwp {
 387                         fsl,pins = <
 388                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 389                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 390                         >;
 391                 };
 392
 393                 pinctrl_audmux: audmuxgrp {
 394                         fsl,pins = <
 395                                 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC        0x130b0
 396                                 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD        0x110b0
 397                                 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS       0x130b0
 398                                 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 399                         >;
 400                 };
 401         };
 402 };
 403
 404 &pcie {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&pinctrl_pcie>;
 407         reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
 408         status = "disabled";
 409 };
 410
 411 &reg_arm {
 412         vin-supply = <&vddcore_reg>;
 413 };
 414
 415 &reg_pu {
 416         vin-supply = <&vddsoc_reg>;
 417 };
 418
 419 &reg_soc {
 420         vin-supply = <&vddsoc_reg>;
 421 };
 422
 423 &uart3 {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_uart3>;
 426         uart-has-rtscts;
 427         status = "disabled";
 428 };
 429
 430 &uart4 {
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&pinctrl_uart4>;
 433         status = "disabled";
 434 };
 435
 436 &usbh1 {
 437         vbus-supply = <&reg_usb_h1_vbus>;
 438         status = "disabled";
 439 };
 440
 441 &usbotg {
 442         vbus-supply = <&reg_usb_otg_vbus>;
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_usbotg>;
 445         disable-over-current;
 446         status = "disabled";
 447 };
 448
 449 &usdhc2 {
 450         pinctrl-names = "default";
 451         pinctrl-0 = <&pinctrl_usdhc2>;
 452         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 453         wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 454         vmmc-supply = <&vdd_sd1_reg>;
 455         status = "disabled";
 456 };
 457
 458 &usdhc3 {
 459         pinctrl-names = "default";
 460         pinctrl-0 = <&pinctrl_usdhc3
 461                      &pinctrl_usdhc3_cdwp>;
 462         cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
 463         wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 464         vmmc-supply = <&vdd_sd0_reg>;
 465         status = "disabled";
 466 };