2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
15 model = "Phytec phyFLEX-i.MX6 Quad";
16 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
19 reg = <0x10000000 0x80000000>;
23 compatible = "simple-bus";
27 reg_usb_otg_vbus: regulator@0 {
28 compatible = "regulator-fixed";
30 regulator-name = "usb_otg_vbus";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
37 reg_usb_h1_vbus: regulator@1 {
38 compatible = "regulator-fixed";
40 regulator-name = "usb_h1_vbus";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
49 compatible = "gpio-leds";
52 label = "phyflex:green";
53 gpios = <&gpio1 30 0>;
57 label = "phyflex:red";
58 gpios = <&gpio2 31 0>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_audmux>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_flexcan1>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_ecspi3>;
79 fsl,spi-num-chipselects = <1>;
80 cs-gpios = <&gpio4 24 0>;
83 compatible = "m25p80", "jedec,spi-nor";
84 spi-max-frequency = <20000000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet>;
93 phy-reset-duration = <10>; /* in msecs */
94 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
95 phy-supply = <&vdd_eth_io_reg>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_gpmi_nand>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_i2c1>;
112 compatible = "atmel,24c32";
117 compatible = "dlg,da9063";
119 interrupt-parent = <&gpio2>;
120 interrupts = <9 0x8>; /* active-low GPIO2_9 */
123 vddcore_reg: bcore1 {
124 regulator-min-microvolt = <730000>;
125 regulator-max-microvolt = <1380000>;
130 regulator-min-microvolt = <730000>;
131 regulator-max-microvolt = <1380000>;
136 regulator-min-microvolt = <1500000>;
137 regulator-max-microvolt = <1500000>;
142 regulator-min-microvolt = <3300000>;
143 regulator-max-microvolt = <3300000>;
147 vdd_buckmem_reg: bmem {
148 regulator-min-microvolt = <3300000>;
149 regulator-max-microvolt = <3300000>;
154 regulator-min-microvolt = <1200000>;
155 regulator-max-microvolt = <1200000>;
159 vdd_eth_io_reg: ldo4 {
160 regulator-min-microvolt = <2500000>;
161 regulator-max-microvolt = <2500000>;
165 vdd_mx6_snvs_reg: ldo5 {
166 regulator-min-microvolt = <3000000>;
167 regulator-max-microvolt = <3000000>;
171 vdd_3v3_pmic_io_reg: ldo6 {
172 regulator-min-microvolt = <3300000>;
173 regulator-max-microvolt = <3300000>;
178 regulator-min-microvolt = <3300000>;
179 regulator-max-microvolt = <3300000>;
183 regulator-min-microvolt = <3300000>;
184 regulator-max-microvolt = <3300000>;
187 vdd_mx6_high_reg: ldo11 {
188 regulator-min-microvolt = <3000000>;
189 regulator-max-microvolt = <3000000>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_i2c2>;
199 clock-frequency = <100000>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_i2c3>;
205 clock-frequency = <100000>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_hog>;
212 imx6q-phytec-pfla02 {
213 pinctrl_hog: hoggrp {
215 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
216 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
217 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
218 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
219 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
223 pinctrl_ecspi3: ecspi3grp {
225 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
226 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
227 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
231 pinctrl_enet: enetgrp {
233 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
234 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
235 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
236 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
237 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
238 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
239 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
240 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
241 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
242 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
243 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
244 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
245 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
246 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
247 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
248 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
252 pinctrl_flexcan1: flexcan1grp {
254 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
255 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
259 pinctrl_gpmi_nand: gpminandgrp {
261 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
262 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
263 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
264 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
265 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
266 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
267 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
268 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
269 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
270 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
271 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
272 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
273 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
274 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
275 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
276 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
277 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
281 pinctrl_i2c1: i2c1grp {
283 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
284 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
288 pinctrl_i2c2: i2c2grp {
290 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
291 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
295 pinctrl_i2c3: i2c3grp {
297 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
298 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
302 pinctrl_pcie: pciegrp {
303 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
306 pinctrl_uart3: uart3grp {
308 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
309 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
310 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
311 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
315 pinctrl_uart4: uart4grp {
317 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
318 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
322 pinctrl_usbh1: usbh1grp {
324 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
328 pinctrl_usbotg: usbotggrp {
330 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
331 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
332 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
336 pinctrl_usdhc2: usdhc2grp {
338 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
339 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
340 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
341 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
342 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
343 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
347 pinctrl_usdhc3: usdhc3grp {
349 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
350 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
351 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
352 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
353 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
354 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
358 pinctrl_usdhc3_cdwp: usdhc3cdwp {
360 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
361 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
365 pinctrl_audmux: audmuxgrp {
367 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
368 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
369 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
370 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_pcie>;
379 reset-gpio = <&gpio4 17 0>;
384 vin-supply = <&vddcore_reg>;
388 vin-supply = <&vddsoc_reg>;
392 vin-supply = <&vddsoc_reg>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_uart3>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_uart4>;
409 vbus-supply = <®_usb_h1_vbus>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_usbh1>;
416 vbus-supply = <®_usb_otg_vbus>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_usbotg>;
419 disable-over-current;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_usdhc2>;
426 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
427 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_usdhc3
434 &pinctrl_usdhc3_cdwp>;
435 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
436 wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;