GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / imx6qdl-nitrogen6_som2.dtsi
1 // SPDX-License-Identifier: GPL-2.0 OR X11
2 /*
3  * Copyright 2016 Boundary Devices, Inc.
4  */
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9         chosen {
10                 stdout-path = &uart2;
11         };
12
13         memory@10000000 {
14                 reg = <0x10000000 0x40000000>;
15         };
16
17         backlight_lcd: backlight-lcd {
18                 compatible = "pwm-backlight";
19                 pwms = <&pwm1 0 5000000>;
20                 brightness-levels = <0 4 8 16 32 64 128 255>;
21                 default-brightness-level = <7>;
22                 power-supply = <&reg_3p3v>;
23                 status = "okay";
24         };
25
26         backlight_lvds0: backlight-lvds0 {
27                 compatible = "pwm-backlight";
28                 pwms = <&pwm4 0 5000000>;
29                 brightness-levels = <0 4 8 16 32 64 128 255>;
30                 default-brightness-level = <7>;
31                 power-supply = <&reg_3p3v>;
32                 status = "okay";
33         };
34
35         backlight_lvds1: backlight-lvds1 {
36                 compatible = "gpio-backlight";
37                 pinctrl-names = "default";
38                 pinctrl-0 = <&pinctrl_backlight_lvds1>;
39                 gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
40                 default-on;
41                 status = "okay";
42         };
43
44         gpio-keys {
45                 compatible = "gpio-keys";
46                 pinctrl-names = "default";
47                 pinctrl-0 = <&pinctrl_gpio_keys>;
48
49                 power {
50                         label = "Power Button";
51                         gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
52                         linux,code = <KEY_POWER>;
53                         wakeup-source;
54                 };
55
56                 menu {
57                         label = "Menu";
58                         gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
59                         linux,code = <KEY_MENU>;
60                 };
61
62                 home {
63                         label = "Home";
64                         gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
65                         linux,code = <KEY_HOME>;
66                 };
67
68                 back {
69                         label = "Back";
70                         gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
71                         linux,code = <KEY_BACK>;
72                 };
73
74                 volume-up {
75                         label = "Volume Up";
76                         gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
77                         linux,code = <KEY_VOLUMEUP>;
78                 };
79
80                 volume-down {
81                         label = "Volume Down";
82                         gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
83                         linux,code = <KEY_VOLUMEDOWN>;
84                 };
85         };
86
87         lcd_display: disp0 {
88                 compatible = "fsl,imx-parallel-display";
89                 #address-cells = <1>;
90                 #size-cells = <0>;
91                 interface-pix-fmt = "bgr666";
92                 pinctrl-names = "default";
93                 pinctrl-0 = <&pinctrl_j15>;
94                 status = "okay";
95
96                 port@0 {
97                         reg = <0>;
98
99                         lcd_display_in: endpoint {
100                                 remote-endpoint = <&ipu1_di0_disp0>;
101                         };
102                 };
103
104                 port@1 {
105                         reg = <1>;
106
107                         lcd_display_out: endpoint {
108                                 remote-endpoint = <&lcd_panel_in>;
109                         };
110                 };
111         };
112
113         panel-lcd {
114                 compatible = "okaya,rs800480t-7x0gp";
115                 backlight = <&backlight_lcd>;
116
117                 port {
118                         lcd_panel_in: endpoint {
119                                 remote-endpoint = <&lcd_display_out>;
120                         };
121                 };
122         };
123
124         panel-lvds0 {
125                 compatible = "hannstar,hsd100pxn1";
126                 backlight = <&backlight_lvds0>;
127
128                 port {
129                         panel_in_lvds0: endpoint {
130                                 remote-endpoint = <&lvds0_out>;
131                         };
132                 };
133         };
134
135         panel-lvds1 {
136                 compatible = "hannstar,hsd100pxn1";
137                 backlight = <&backlight_lvds1>;
138
139                 port {
140                         panel_in_lvds1: endpoint {
141                                 remote-endpoint = <&lvds1_out>;
142                         };
143                 };
144         };
145
146         reg_1p8v: regulator-1v8 {
147                 compatible = "regulator-fixed";
148                 regulator-name = "1P8V";
149                 regulator-min-microvolt = <1800000>;
150                 regulator-max-microvolt = <1800000>;
151                 regulator-always-on;
152         };
153
154         reg_2p5v: regulator-2v5 {
155                 compatible = "regulator-fixed";
156                 regulator-name = "2P5V";
157                 regulator-min-microvolt = <2500000>;
158                 regulator-max-microvolt = <2500000>;
159                 regulator-always-on;
160         };
161
162         reg_3p3v: regulator-3v3 {
163                 compatible = "regulator-fixed";
164                 regulator-name = "3P3V";
165                 regulator-min-microvolt = <3300000>;
166                 regulator-max-microvolt = <3300000>;
167                 regulator-always-on;
168         };
169
170         reg_can_xcvr: regulator-can-xcvr {
171                 compatible = "regulator-fixed";
172                 regulator-name = "CAN XCVR";
173                 regulator-min-microvolt = <3300000>;
174                 regulator-max-microvolt = <3300000>;
175                 pinctrl-names = "default";
176                 pinctrl-0 = <&pinctrl_can_xcvr>;
177                 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
178         };
179
180         reg_usb_h1_vbus: regulator-usb-h1-vbus {
181                 compatible = "regulator-fixed";
182                 pinctrl-names = "default";
183                 pinctrl-0 = <&pinctrl_usbh1>;
184                 regulator-name = "usb_h1_vbus";
185                 regulator-min-microvolt = <3300000>;
186                 regulator-max-microvolt = <3300000>;
187                 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
188                 enable-active-high;
189                 regulator-always-on;
190         };
191
192         reg_usb_otg_vbus: regulator-usb-otg-vbus {
193                 compatible = "regulator-fixed";
194                 regulator-name = "usb_otg_vbus";
195                 regulator-min-microvolt = <5000000>;
196                 regulator-max-microvolt = <5000000>;
197                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
198                 enable-active-high;
199         };
200
201         reg_wlan_vmmc: regulator-wlan-vmmc {
202                 compatible = "regulator-fixed";
203                 pinctrl-names = "default";
204                 pinctrl-0 = <&pinctrl_wlan_vmmc>;
205                 regulator-name = "reg_wlan_vmmc";
206                 regulator-min-microvolt = <3300000>;
207                 regulator-max-microvolt = <3300000>;
208                 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
209                 startup-delay-us = <70000>;
210                 enable-active-high;
211         };
212
213         sound {
214                 compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
215                              "fsl,imx-audio-sgtl5000";
216                 model = "imx6q-nitrogen6_som2-sgtl5000";
217                 ssi-controller = <&ssi1>;
218                 audio-codec = <&codec>;
219                 audio-routing =
220                         "MIC_IN", "Mic Jack",
221                         "Mic Jack", "Mic Bias",
222                         "Headphone Jack", "HP_OUT";
223                 mux-int-port = <1>;
224                 mux-ext-port = <3>;
225         };
226 };
227
228 &audmux {
229         pinctrl-names = "default";
230         pinctrl-0 = <&pinctrl_audmux>;
231         status = "okay";
232 };
233
234 &can1 {
235         pinctrl-names = "default";
236         pinctrl-0 = <&pinctrl_can1>;
237         xceiver-supply = <&reg_can_xcvr>;
238         status = "okay";
239 };
240
241 &clks {
242         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
243                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
244         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
245                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
246 };
247
248 &ecspi1 {
249         cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
250         pinctrl-names = "default";
251         pinctrl-0 = <&pinctrl_ecspi1>;
252         status = "okay";
253
254         flash: m25p80@0 {
255                 compatible = "microchip,sst25vf016b";
256                 spi-max-frequency = <20000000>;
257                 reg = <0>;
258         };
259 };
260
261 &fec {
262         pinctrl-names = "default";
263         pinctrl-0 = <&pinctrl_enet>;
264         phy-mode = "rgmii";
265         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
266                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
267         fsl,err006687-workaround-present;
268         status = "okay";
269 };
270
271 &hdmi {
272         ddc-i2c-bus = <&i2c2>;
273         status = "okay";
274 };
275
276 &i2c1 {
277         clock-frequency = <100000>;
278         pinctrl-names = "default";
279         pinctrl-0 = <&pinctrl_i2c1>;
280         status = "okay";
281
282         codec: sgtl5000@a {
283                 compatible = "fsl,sgtl5000";
284                 pinctrl-names = "default";
285                 pinctrl-0 = <&pinctrl_sgtl5000>;
286                 reg = <0x0a>;
287                 clocks = <&clks IMX6QDL_CLK_CKO>;
288                 VDDA-supply = <&reg_2p5v>;
289                 VDDIO-supply = <&reg_3p3v>;
290         };
291
292         rtc@68 {
293                 compatible = "microcrystal,rv4162";
294                 pinctrl-names = "default";
295                 pinctrl-0 = <&pinctrl_rv4162>;
296                 reg = <0x68>;
297                 interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>;
298         };
299 };
300
301 &i2c2 {
302         clock-frequency = <100000>;
303         pinctrl-names = "default";
304         pinctrl-0 = <&pinctrl_i2c2>;
305         status = "okay";
306 };
307
308 &i2c3 {
309         clock-frequency = <100000>;
310         pinctrl-names = "default";
311         pinctrl-0 = <&pinctrl_i2c3>;
312         status = "okay";
313
314         touchscreen@4 {
315                 compatible = "eeti,egalax_ts";
316                 reg = <0x04>;
317                 interrupt-parent = <&gpio1>;
318                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
319                 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
320         };
321
322         touchscreen@38 {
323                 compatible = "edt,edt-ft5x06";
324                 reg = <0x38>;
325                 interrupt-parent = <&gpio1>;
326                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
327                 wakeup-source;
328         };
329 };
330
331 &iomuxc {
332         pinctrl_audmux: audmuxgrp {
333                 fsl,pins = <
334                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
335                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
336                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
337                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
338                 >;
339         };
340
341         pinctrl_backlight_lvds1: backlight-lvds1grp {
342                 fsl,pins = <
343                         MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x0b0b0
344                 >;
345         };
346
347         pinctrl_can1: can1grp {
348                 fsl,pins = <
349                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
350                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
351                 >;
352         };
353
354         pinctrl_can_xcvr: can-xcvrgrp {
355                 fsl,pins = <
356                         /* Flexcan XCVR enable */
357                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x0b0b0
358                 >;
359         };
360
361         pinctrl_ecspi1: ecspi1grp {
362                 fsl,pins = <
363                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
364                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
365                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
366                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x000b1
367                 >;
368         };
369
370         pinctrl_enet: enetgrp {
371                 fsl,pins = <
372                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
373                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
374                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
375                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
376                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
377                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
378                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
379                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
380                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
381                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
382                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x130b0
383                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
384                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x130b0
385                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
386                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x130b0
387                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x030b0
388                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
389                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
390                 >;
391         };
392
393         pinctrl_gpio_keys: gpio-keysgrp {
394                 fsl,pins = <
395                         /* Power Button */
396                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x1b0b0
397                         /* Menu Button */
398                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
399                         /* Home Button */
400                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x1b0b0
401                         /* Back Button */
402                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
403                         /* Volume Up Button */
404                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
405                         /* Volume Down Button */
406                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b0
407                 >;
408         };
409
410         pinctrl_i2c1: i2c1grp {
411                 fsl,pins = <
412                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
413                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
414                 >;
415         };
416
417         pinctrl_i2c2: i2c2grp {
418                 fsl,pins = <
419                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
420                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
421                 >;
422         };
423
424         pinctrl_i2c3: i2c3grp {
425                 fsl,pins = <
426                         MX6QDL_PAD_GPIO_5__I2C3_SCL     0x4001b8b1
427                         MX6QDL_PAD_GPIO_16__I2C3_SDA    0x4001b8b1
428                         MX6QDL_PAD_GPIO_9__GPIO1_IO09   0x1b0b0
429                 >;
430         };
431
432         pinctrl_i2c3mux: i2c3muxgrp {
433                 fsl,pins = <
434                         /* PCIe I2C enable */
435                         MX6QDL_PAD_EIM_OE__GPIO2_IO25   0x000b0
436                 >;
437         };
438
439         pinctrl_j15: j15grp {
440                 fsl,pins = <
441                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
442                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
443                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
444                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
445                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
446                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
447                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
448                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
449                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
450                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
451                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
452                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
453                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
454                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
455                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
456                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
457                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
458                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
459                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
460                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
461                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
462                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
463                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
464                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
465                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
466                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
467                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
468                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
469                 >;
470         };
471
472         pinctrl_pcie: pciegrp {
473                 fsl,pins = <
474                         /* PCIe reset */
475                         MX6QDL_PAD_EIM_DA0__GPIO3_IO00  0x030b0
476                         MX6QDL_PAD_EIM_DA4__GPIO3_IO04  0x030b0
477                 >;
478         };
479
480         pinctrl_pwm1: pwm1grp {
481                 fsl,pins = <
482                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT   0x030b1
483                 >;
484         };
485
486         pinctrl_pwm3: pwm3grp {
487                 fsl,pins = <
488                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT   0x030b1
489                 >;
490         };
491
492         pinctrl_pwm4: pwm4grp {
493                 fsl,pins = <
494                         MX6QDL_PAD_SD1_CMD__PWM4_OUT    0x030b1
495                 >;
496         };
497
498         pinctrl_rv4162: rv4162grp {
499                 fsl,pins = <
500                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0
501                 >;
502         };
503
504         pinctrl_sgtl5000: sgtl5000grp {
505                 fsl,pins = <
506                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x000b0
507                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x130b0
508                         MX6QDL_PAD_EIM_DA2__GPIO3_IO02          0x130b0
509                         MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x130b0
510                 >;
511         };
512
513         pinctrl_uart1: uart1grp {
514                 fsl,pins = <
515                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
516                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
517                 >;
518         };
519
520         pinctrl_uart2: uart2grp {
521                 fsl,pins = <
522                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
523                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
524                 >;
525         };
526
527         pinctrl_uart3: uart3grp {
528                 fsl,pins = <
529                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
530                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
531                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
532                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
533                 >;
534         };
535
536         pinctrl_usbh1: usbh1grp {
537                 fsl,pins = <
538                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x030b0
539                 >;
540         };
541
542         pinctrl_usbotg: usbotggrp {
543                 fsl,pins = <
544                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
545                         MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
546                         /* power enable, high active */
547                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x030b0
548                 >;
549         };
550
551         pinctrl_usdhc2: usdhc2grp {
552                 fsl,pins = <
553                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10071
554                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17071
555                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17071
556                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17071
557                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17071
558                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17071
559                 >;
560         };
561
562         pinctrl_usdhc3: usdhc3grp {
563                 fsl,pins = <
564                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10071
565                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17071
566                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17071
567                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17071
568                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17071
569                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17071
570                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0
571                 >;
572         };
573
574         pinctrl_usdhc4: usdhc4grp {
575                 fsl,pins = <
576                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
577                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
578                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
579                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
580                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
581                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
582                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
583                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
584                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
585                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
586                 >;
587         };
588
589         pinctrl_wlan_vmmc: wlan-vmmcgrp {
590                 fsl,pins = <
591                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x100b0
592                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x030b0
593                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x030b0
594                         MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT      0x000b0
595                 >;
596         };
597 };
598
599 &ipu1_di0_disp0 {
600         remote-endpoint = <&lcd_display_in>;
601 };
602
603 &ldb {
604         status = "okay";
605
606         lvds-channel@0 {
607                 status = "okay";
608
609                 port@4 {
610                         reg = <4>;
611
612                         lvds0_out: endpoint {
613                                 remote-endpoint = <&panel_in_lvds0>;
614                         };
615                 };
616         };
617
618         lvds-channel@1 {
619                 fsl,data-mapping = "spwg";
620                 fsl,data-width = <18>;
621                 status = "okay";
622
623                 port@4 {
624                         reg = <4>;
625
626                         lvds1_out: endpoint {
627                                 remote-endpoint = <&panel_in_lvds1>;
628                         };
629                 };
630         };
631 };
632
633 &pcie {
634         pinctrl-names = "default";
635         pinctrl-0 = <&pinctrl_pcie>;
636         reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>;
637         status = "okay";
638 };
639
640 &pwm1 {
641         pinctrl-names = "default";
642         pinctrl-0 = <&pinctrl_pwm1>;
643         status = "okay";
644 };
645
646 &pwm3 {
647         pinctrl-names = "default";
648         pinctrl-0 = <&pinctrl_pwm3>;
649         status = "okay";
650 };
651
652 &pwm4 {
653         pinctrl-names = "default";
654         pinctrl-0 = <&pinctrl_pwm4>;
655         status = "okay";
656 };
657
658 &ssi1 {
659         status = "okay";
660 };
661
662 &uart1 {
663         pinctrl-names = "default";
664         pinctrl-0 = <&pinctrl_uart1>;
665         status = "okay";
666 };
667
668 &uart2 {
669         pinctrl-names = "default";
670         pinctrl-0 = <&pinctrl_uart2>;
671         status = "okay";
672 };
673
674 &uart3 {
675         pinctrl-names = "default";
676         pinctrl-0 = <&pinctrl_uart3>;
677         uart-has-rtscts;
678         status = "okay";
679 };
680
681 &usbh1 {
682         vbus-supply = <&reg_usb_h1_vbus>;
683         status = "okay";
684 };
685
686 &usbotg {
687         vbus-supply = <&reg_usb_otg_vbus>;
688         pinctrl-names = "default";
689         pinctrl-0 = <&pinctrl_usbotg>;
690         disable-over-current;
691         status = "okay";
692 };
693
694 &usdhc2 {
695         pinctrl-names = "default";
696         pinctrl-0 = <&pinctrl_usdhc2>;
697         bus-width = <4>;
698         non-removable;
699         vmmc-supply = <&reg_wlan_vmmc>;
700         cap-power-off-card;
701         keep-power-in-suspend;
702         status = "okay";
703
704         #address-cells = <1>;
705         #size-cells = <0>;
706         wlcore: wlcore@2 {
707                 compatible = "ti,wl1271";
708                 reg = <2>;
709                 interrupt-parent = <&gpio6>;
710                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
711                 ref-clock-frequency = <38400000>;
712         };
713 };
714
715 &usdhc3 {
716         pinctrl-names = "default";
717         pinctrl-0 = <&pinctrl_usdhc3>;
718         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
719         bus-width = <4>;
720         vmmc-supply = <&reg_3p3v>;
721         status = "okay";
722 };
723
724 &usdhc4 {
725         pinctrl-names = "default";
726         pinctrl-0 = <&pinctrl_usdhc4>;
727         bus-width = <8>;
728         non-removable;
729         vmmc-supply = <&reg_1p8v>;
730         keep-power-in-suspend;
731         status = "okay";
732 };