2 * Copyright 2014 Gateworks Corporation
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
15 /* these are used by bootloader for disabling nodes */
26 bootargs = "console=ttymxc1,115200";
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpio_leds>;
36 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
38 linux,default-trigger = "heartbeat";
43 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
44 default-state = "off";
49 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
50 default-state = "off";
55 reg = <0x10000000 0x20000000>;
59 compatible = "simple-bus";
63 reg_1p0v: regulator@0 {
64 compatible = "regulator-fixed";
66 regulator-name = "1P0V";
67 regulator-min-microvolt = <1000000>;
68 regulator-max-microvolt = <1000000>;
72 reg_3p3v: regulator@2 {
73 compatible = "regulator-fixed";
75 regulator-name = "3P3V";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
81 reg_5p0v: regulator@3 {
82 compatible = "regulator-fixed";
84 regulator-name = "5P0V";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_gpmi_nand>;
99 ddc-i2c-bus = <&i2c3>;
104 clock-frequency = <100000>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c1>;
110 compatible = "atmel,24c02";
116 compatible = "atmel,24c02";
122 compatible = "atmel,24c02";
128 compatible = "atmel,24c02";
134 compatible = "nxp,pca9555";
141 compatible = "dallas,ds1672";
147 clock-frequency = <100000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c2>;
154 clock-frequency = <100000>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c3>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_pcie>;
163 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_uart2>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart3>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_uart5>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_wdog>;
203 fsl,ext-reset-output;
208 pinctrl_gpio_leds: gpioledsgrp {
210 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
211 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
212 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
216 pinctrl_gpmi_nand: gpminandgrp {
218 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
219 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
220 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
221 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
222 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
223 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
224 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
225 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
226 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
227 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
228 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
229 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
230 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
231 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
232 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
236 pinctrl_i2c1: i2c1grp {
238 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
239 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
243 pinctrl_i2c2: i2c2grp {
245 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
246 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
250 pinctrl_i2c3: i2c3grp {
252 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
253 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
257 pinctrl_pcie: pciegrp {
259 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
263 pinctrl_pwm2: pwm2grp {
265 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
269 pinctrl_pwm3: pwm3grp {
271 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
275 pinctrl_uart2: uart2grp {
277 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
278 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
282 pinctrl_uart3: uart3grp {
284 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
285 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
289 pinctrl_uart5: uart5grp {
291 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
292 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
296 pinctrl_wdog: wdoggrp {
298 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0