arch/arm/boot/dts/imx6qdl-gw54xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/sound/fsl-imx-audmux.h>
  10
  11 / {
  12         /* these are used by bootloader for disabling nodes */
  13         aliases {
  14                 led0 = &led0;
  15                 led1 = &led1;
  16                 led2 = &led2;
  17                 nand = &gpmi;
  18                 ssi0 = &ssi1;
  19                 usb0 = &usbh1;
  20                 usb1 = &usbotg;
  21         };
  22
  23         chosen {
  24                 bootargs = "console=ttymxc1,115200";
  25         };
  26
  27         backlight {
  28                 compatible = "pwm-backlight";
  29                 pwms = <&pwm4 0 5000000>;
  30                 brightness-levels = <0 4 8 16 32 64 128 255>;
  31                 default-brightness-level = <7>;
  32         };
  33
  34         gpio-keys {
  35                 compatible = "gpio-keys";
  36
  37                 user-pb {
  38                         label = "user_pb";
  39                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  40                         linux,code = <BTN_0>;
  41                 };
  42
  43                 user-pb1x {
  44                         label = "user_pb1x";
  45                         linux,code = <BTN_1>;
  46                         interrupt-parent = <&gsc>;
  47                         interrupts = <0>;
  48                 };
  49
  50                 key-erased {
  51                         label = "key-erased";
  52                         linux,code = <BTN_2>;
  53                         interrupt-parent = <&gsc>;
  54                         interrupts = <1>;
  55                 };
  56
  57                 eeprom-wp {
  58                         label = "eeprom_wp";
  59                         linux,code = <BTN_3>;
  60                         interrupt-parent = <&gsc>;
  61                         interrupts = <2>;
  62                 };
  63
  64                 tamper {
  65                         label = "tamper";
  66                         linux,code = <BTN_4>;
  67                         interrupt-parent = <&gsc>;
  68                         interrupts = <5>;
  69                 };
  70
  71                 switch-hold {
  72                         label = "switch_hold";
  73                         linux,code = <BTN_5>;
  74                         interrupt-parent = <&gsc>;
  75                         interrupts = <7>;
  76                 };
  77         };
  78
  79         leds {
  80                 compatible = "gpio-leds";
  81                 pinctrl-names = "default";
  82                 pinctrl-0 = <&pinctrl_gpio_leds>;
  83
  84                 led0: led-user1 {
  85                         label = "user1";
  86                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  87                         default-state = "on";
  88                         linux,default-trigger = "heartbeat";
  89                 };
  90
  91                 led1: led-user2 {
  92                         label = "user2";
  93                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  94                         default-state = "off";
  95                 };
  96
  97                 led2: led-user3 {
  98                         label = "user3";
  99                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 100                         default-state = "off";
 101                 };
 102         };
 103
 104         memory@10000000 {
 105                 device_type = "memory";
 106                 reg = <0x10000000 0x40000000>;
 107         };
 108
 109         pps {
 110                 compatible = "pps-gpio";
 111                 pinctrl-names = "default";
 112                 pinctrl-0 = <&pinctrl_pps>;
 113                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 114                 status = "okay";
 115         };
 116
 117         regulators {
 118                 compatible = "simple-bus";
 119                 #address-cells = <1>;
 120                 #size-cells = <0>;
 121
 122                 reg_1p0v: regulator@0 {
 123                         compatible = "regulator-fixed";
 124                         reg = <0>;
 125                         regulator-name = "1P0V";
 126                         regulator-min-microvolt = <1000000>;
 127                         regulator-max-microvolt = <1000000>;
 128                         regulator-always-on;
 129                 };
 130
 131                 reg_3p3v: regulator@1 {
 132                         compatible = "regulator-fixed";
 133                         reg = <1>;
 134                         regulator-name = "3P3V";
 135                         regulator-min-microvolt = <3300000>;
 136                         regulator-max-microvolt = <3300000>;
 137                         regulator-always-on;
 138                 };
 139
 140                 reg_can1_stby: regulator-can1-stby {
 141                         compatible = "regulator-fixed";
 142                         pinctrl-names = "default";
 143                         pinctrl-0 = <&pinctrl_reg_can1>;
 144                         regulator-name = "can1_stby";
 145                         gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
 146                         regulator-min-microvolt = <3300000>;
 147                         regulator-max-microvolt = <3300000>;
 148                 };
 149
 150                 reg_usb_h1_vbus: regulator@2 {
 151                         compatible = "regulator-fixed";
 152                         reg = <2>;
 153                         regulator-name = "usb_h1_vbus";
 154                         regulator-min-microvolt = <5000000>;
 155                         regulator-max-microvolt = <5000000>;
 156                         regulator-always-on;
 157                 };
 158
 159                 reg_usb_otg_vbus: regulator@3 {
 160                         compatible = "regulator-fixed";
 161                         reg = <3>;
 162                         regulator-name = "usb_otg_vbus";
 163                         regulator-min-microvolt = <5000000>;
 164                         regulator-max-microvolt = <5000000>;
 165                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 166                         enable-active-high;
 167                 };
 168         };
 169
 170         sound-analog {
 171                 compatible = "fsl,imx6q-ventana-sgtl5000",
 172                              "fsl,imx-audio-sgtl5000";
 173                 model = "sgtl5000-audio";
 174                 ssi-controller = <&ssi1>;
 175                 audio-codec = <&sgtl5000>;
 176                 audio-routing =
 177                         "MIC_IN", "Mic Jack",
 178                         "Mic Jack", "Mic Bias",
 179                         "Headphone Jack", "HP_OUT";
 180                 mux-int-port = <1>;
 181                 mux-ext-port = <4>;
 182         };
 183 };
 184
 185 &audmux {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
 188         status = "okay";
 189
 190         ssi2 {
 191                 fsl,audmux-port = <1>;
 192                 fsl,port-config = <
 193                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 194                         IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
 195                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 196                         IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
 197                         IMX_AUDMUX_V2_PTCR_SYN)
 198                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 199                 >;
 200         };
 201
 202         aud5 {
 203                 fsl,audmux-port = <4>;
 204                 fsl,port-config = <
 205                         IMX_AUDMUX_V2_PTCR_SYN
 206                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
 207         };
 208 };
 209
 210 &can1 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_flexcan1>;
 213         xceiver-supply = <&reg_can1_stby>;
 214         status = "okay";
 215 };
 216
 217 &clks {
 218         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 219                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 220         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 221                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 222 };
 223
 224 &ecspi2 {
 225         cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_ecspi2>;
 228         status = "okay";
 229 };
 230
 231 &fec {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_enet>;
 234         phy-mode = "rgmii-id";
 235         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 236         status = "okay";
 237 };
 238
 239 &gpmi {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_gpmi_nand>;
 242         status = "okay";
 243 };
 244
 245 &hdmi {
 246         ddc-i2c-bus = <&i2c3>;
 247         status = "okay";
 248 };
 249
 250 &i2c1 {
 251         clock-frequency = <100000>;
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pinctrl_i2c1>;
 254         status = "okay";
 255
 256         gsc: gsc@20 {
 257                 compatible = "gw,gsc";
 258                 reg = <0x20>;
 259                 interrupt-parent = <&gpio1>;
 260                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 261                 interrupt-controller;
 262                 #interrupt-cells = <1>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265
 266                 adc {
 267                         compatible = "gw,gsc-adc";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270
 271                         channel@0 {
 272                                 gw,mode = <0>;
 273                                 reg = <0x00>;
 274                                 label = "temp";
 275                         };
 276
 277                         channel@2 {
 278                                 gw,mode = <1>;
 279                                 reg = <0x02>;
 280                                 label = "vdd_vin";
 281                         };
 282
 283                         channel@5 {
 284                                 gw,mode = <1>;
 285                                 reg = <0x05>;
 286                                 label = "vdd_3p3";
 287                         };
 288
 289                         channel@8 {
 290                                 gw,mode = <1>;
 291                                 reg = <0x08>;
 292                                 label = "vdd_bat";
 293                         };
 294
 295                         channel@b {
 296                                 gw,mode = <1>;
 297                                 reg = <0x0b>;
 298                                 label = "vdd_5p0";
 299                         };
 300
 301                         channel@e {
 302                                 gw,mode = <1>;
 303                                 reg = <0xe>;
 304                                 label = "vdd_arm";
 305                         };
 306
 307                         channel@11 {
 308                                 gw,mode = <1>;
 309                                 reg = <0x11>;
 310                                 label = "vdd_soc";
 311                         };
 312
 313                         channel@14 {
 314                                 gw,mode = <1>;
 315                                 reg = <0x14>;
 316                                 label = "vdd_3p0";
 317                         };
 318
 319                         channel@17 {
 320                                 gw,mode = <1>;
 321                                 reg = <0x17>;
 322                                 label = "vdd_1p5";
 323                         };
 324
 325                         channel@1d {
 326                                 gw,mode = <1>;
 327                                 reg = <0x1d>;
 328                                 label = "vdd_1p8";
 329                         };
 330
 331                         channel@20 {
 332                                 gw,mode = <1>;
 333                                 reg = <0x20>;
 334                                 label = "vdd_1p0";
 335                         };
 336
 337                         channel@23 {
 338                                 gw,mode = <1>;
 339                                 reg = <0x23>;
 340                                 label = "vdd_2p5";
 341                         };
 342
 343                         channel@26 {
 344                                 gw,mode = <1>;
 345                                 reg = <0x26>;
 346                                 label = "vdd_gps";
 347                         };
 348                 };
 349
 350                 fan-controller@2c {
 351                         compatible = "gw,gsc-fan";
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         reg = <0x2c>;
 355                 };
 356         };
 357
 358         gsc_gpio: gpio@23 {
 359                 compatible = "nxp,pca9555";
 360                 reg = <0x23>;
 361                 gpio-controller;
 362                 #gpio-cells = <2>;
 363                 interrupt-parent = <&gsc>;
 364                 interrupts = <4>;
 365         };
 366
 367         eeprom1: eeprom@50 {
 368                 compatible = "atmel,24c02";
 369                 reg = <0x50>;
 370                 pagesize = <16>;
 371         };
 372
 373         eeprom2: eeprom@51 {
 374                 compatible = "atmel,24c02";
 375                 reg = <0x51>;
 376                 pagesize = <16>;
 377         };
 378
 379         eeprom3: eeprom@52 {
 380                 compatible = "atmel,24c02";
 381                 reg = <0x52>;
 382                 pagesize = <16>;
 383         };
 384
 385         eeprom4: eeprom@53 {
 386                 compatible = "atmel,24c02";
 387                 reg = <0x53>;
 388                 pagesize = <16>;
 389         };
 390
 391         rtc: ds1672@68 {
 392                 compatible = "dallas,ds1672";
 393                 reg = <0x68>;
 394         };
 395 };
 396
 397 &i2c2 {
 398         clock-frequency = <100000>;
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_i2c2>;
 401         status = "okay";
 402
 403         pmic: pfuze100@8 {
 404                 compatible = "fsl,pfuze100";
 405                 reg = <0x08>;
 406
 407                 regulators {
 408                         sw1a_reg: sw1ab {
 409                                 regulator-min-microvolt = <300000>;
 410                                 regulator-max-microvolt = <1875000>;
 411                                 regulator-boot-on;
 412                                 regulator-always-on;
 413                                 regulator-ramp-delay = <6250>;
 414                         };
 415
 416                         sw1c_reg: sw1c {
 417                                 regulator-min-microvolt = <300000>;
 418                                 regulator-max-microvolt = <1875000>;
 419                                 regulator-boot-on;
 420                                 regulator-always-on;
 421                                 regulator-ramp-delay = <6250>;
 422                         };
 423
 424                         sw2_reg: sw2 {
 425                                 regulator-min-microvolt = <800000>;
 426                                 regulator-max-microvolt = <3950000>;
 427                                 regulator-boot-on;
 428                                 regulator-always-on;
 429                         };
 430
 431                         sw3a_reg: sw3a {
 432                                 regulator-min-microvolt = <400000>;
 433                                 regulator-max-microvolt = <1975000>;
 434                                 regulator-boot-on;
 435                                 regulator-always-on;
 436                         };
 437
 438                         sw3b_reg: sw3b {
 439                                 regulator-min-microvolt = <400000>;
 440                                 regulator-max-microvolt = <1975000>;
 441                                 regulator-boot-on;
 442                                 regulator-always-on;
 443                         };
 444
 445                         sw4_reg: sw4 {
 446                                 regulator-min-microvolt = <800000>;
 447                                 regulator-max-microvolt = <3300000>;
 448                         };
 449
 450                         swbst_reg: swbst {
 451                                 regulator-min-microvolt = <5000000>;
 452                                 regulator-max-microvolt = <5150000>;
 453                                 regulator-boot-on;
 454                                 regulator-always-on;
 455                         };
 456
 457                         snvs_reg: vsnvs {
 458                                 regulator-min-microvolt = <1000000>;
 459                                 regulator-max-microvolt = <3000000>;
 460                                 regulator-boot-on;
 461                                 regulator-always-on;
 462                         };
 463
 464                         vref_reg: vrefddr {
 465                                 regulator-boot-on;
 466                                 regulator-always-on;
 467                         };
 468
 469                         vgen1_reg: vgen1 {
 470                                 regulator-min-microvolt = <800000>;
 471                                 regulator-max-microvolt = <1550000>;
 472                         };
 473
 474                         vgen2_reg: vgen2 {
 475                                 regulator-min-microvolt = <800000>;
 476                                 regulator-max-microvolt = <1550000>;
 477                         };
 478
 479                         vgen3_reg: vgen3 {
 480                                 regulator-min-microvolt = <1800000>;
 481                                 regulator-max-microvolt = <3300000>;
 482                         };
 483
 484                         vgen4_reg: vgen4 {
 485                                 regulator-min-microvolt = <1800000>;
 486                                 regulator-max-microvolt = <3300000>;
 487                                 regulator-always-on;
 488                         };
 489
 490                         vgen5_reg: vgen5 {
 491                                 regulator-min-microvolt = <1800000>;
 492                                 regulator-max-microvolt = <3300000>;
 493                                 regulator-always-on;
 494                         };
 495
 496                         vgen6_reg: vgen6 {
 497                                 regulator-min-microvolt = <1800000>;
 498                                 regulator-max-microvolt = <3300000>;
 499                                 regulator-always-on;
 500                         };
 501                 };
 502         };
 503 };
 504
 505 &i2c3 {
 506         clock-frequency = <100000>;
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&pinctrl_i2c3>;
 509         status = "okay";
 510
 511         sgtl5000: audio-codec@a {
 512                 compatible = "fsl,sgtl5000";
 513                 reg = <0x0a>;
 514                 clocks = <&clks IMX6QDL_CLK_CKO>;
 515                 VDDA-supply = <&sw4_reg>;
 516                 VDDIO-supply = <&reg_3p3v>;
 517         };
 518
 519         touchscreen: egalax_ts@4 {
 520                 compatible = "eeti,egalax_ts";
 521                 reg = <0x04>;
 522                 interrupt-parent = <&gpio7>;
 523                 interrupts = <12 2>;
 524                 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 525         };
 526
 527         accel@1e {
 528                 compatible = "nxp,fxos8700";
 529                 reg = <0x1e>;
 530         };
 531 };
 532
 533 &ldb {
 534         status = "okay";
 535
 536         lvds-channel@0 {
 537                 fsl,data-mapping = "spwg";
 538                 fsl,data-width = <18>;
 539                 status = "okay";
 540
 541                 display-timings {
 542                         native-mode = <&timing0>;
 543                         timing0: hsd100pxn1 {
 544                                 clock-frequency = <65000000>;
 545                                 hactive = <1024>;
 546                                 vactive = <768>;
 547                                 hback-porch = <220>;
 548                                 hfront-porch = <40>;
 549                                 vback-porch = <21>;
 550                                 vfront-porch = <7>;
 551                                 hsync-len = <60>;
 552                                 vsync-len = <10>;
 553                         };
 554                 };
 555         };
 556 };
 557
 558 &pcie {
 559         pinctrl-names = "default";
 560         pinctrl-0 = <&pinctrl_pcie>;
 561         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 562         status = "okay";
 563 };
 564
 565 &pwm1 {
 566         pinctrl-names = "default";
 567         pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
 568         status = "disabled";
 569 };
 570
 571 &pwm2 {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 574         status = "disabled";
 575 };
 576
 577 &pwm3 {
 578         pinctrl-names = "default";
 579         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 580         status = "disabled";
 581 };
 582
 583 &pwm4 {
 584         #pwm-cells = <2>;
 585         pinctrl-names = "default", "state_dio";
 586         pinctrl-0 = <&pinctrl_pwm4_backlight>;
 587         pinctrl-1 = <&pinctrl_pwm4_dio>;
 588         status = "okay";
 589 };
 590
 591 &ssi1 {
 592         status = "okay";
 593 };
 594
 595 &ssi2 {
 596         status = "okay";
 597 };
 598
 599 &uart1 {
 600         pinctrl-names = "default";
 601         pinctrl-0 = <&pinctrl_uart1>;
 602         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 603         status = "okay";
 604 };
 605
 606 &uart2 {
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&pinctrl_uart2>;
 609         status = "okay";
 610 };
 611
 612 &uart5 {
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&pinctrl_uart5>;
 615         status = "okay";
 616 };
 617
 618 &usbotg {
 619         vbus-supply = <&reg_usb_otg_vbus>;
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&pinctrl_usbotg>;
 622         disable-over-current;
 623         status = "okay";
 624 };
 625
 626 &usbh1 {
 627         vbus-supply = <&reg_usb_h1_vbus>;
 628         status = "okay";
 629 };
 630
 631 &usdhc3 {
 632         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 633         pinctrl-0 = <&pinctrl_usdhc3>;
 634         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 635         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 636         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 637         vmmc-supply = <&reg_3p3v>;
 638         no-1-8-v; /* firmware will remove if board revision supports */
 639         status = "okay";
 640 };
 641
 642 &wdog1 {
 643         status = "disabled";
 644 };
 645
 646 &wdog2 {
 647         pinctrl-names = "default";
 648         pinctrl-0 = <&pinctrl_wdog>;
 649         fsl,ext-reset-output;
 650         status = "okay";
 651 };
 652
 653 &iomuxc {
 654         pinctrl_audmux: audmuxgrp {
 655                 fsl,pins = <
 656                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 657                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 658                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 659                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 660                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 661                         MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
 662                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 663                         MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
 664                 >;
 665         };
 666
 667         pinctrl_enet: enetgrp {
 668                 fsl,pins = <
 669                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 670                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 671                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 672                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 673                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 674                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 675                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 676                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 677                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 678                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 679                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 680                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 681                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 682                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 683                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 684                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 685                 >;
 686         };
 687
 688         pinctrl_ecspi2: escpi2grp {
 689                 fsl,pins = <
 690                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 691                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 692                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 693                         MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1
 694                 >;
 695         };
 696
 697         pinctrl_flexcan1: flexcan1grp {
 698                 fsl,pins = <
 699                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 700                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 701                 >;
 702         };
 703
 704         pinctrl_gpio_leds: gpioledsgrp {
 705                 fsl,pins = <
 706                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 707                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 708                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 709                 >;
 710         };
 711
 712         pinctrl_gpmi_nand: gpminandgrp {
 713                 fsl,pins = <
 714                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 715                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 716                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 717                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 718                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 719                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 720                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 721                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 722                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 723                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 724                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 725                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 726                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 727                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 728                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 729                 >;
 730         };
 731
 732         pinctrl_i2c1: i2c1grp {
 733                 fsl,pins = <
 734                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 735                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 736                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 737                 >;
 738         };
 739
 740         pinctrl_i2c2: i2c2grp {
 741                 fsl,pins = <
 742                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 743                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 744                 >;
 745         };
 746
 747         pinctrl_i2c3: i2c3grp {
 748                 fsl,pins = <
 749                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 750                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 751                 >;
 752         };
 753
 754         pinctrl_pcie: pciegrp {
 755                 fsl,pins = <
 756                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
 757                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
 758                 >;
 759         };
 760
 761         pinctrl_pps: ppsgrp {
 762                 fsl,pins = <
 763                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 764                 >;
 765         };
 766
 767         pinctrl_pwm1: pwm1grp {
 768                 fsl,pins = <
 769                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 770                 >;
 771         };
 772
 773         pinctrl_pwm2: pwm2grp {
 774                 fsl,pins = <
 775                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 776                 >;
 777         };
 778
 779         pinctrl_pwm3: pwm3grp {
 780                 fsl,pins = <
 781                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 782                 >;
 783         };
 784
 785         pinctrl_pwm4_backlight: pwm4grpbacklight {
 786                 fsl,pins = <
 787                         /* LVDS_PWM J6.5 */
 788                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 789                 >;
 790         };
 791
 792         pinctrl_pwm4_dio: pwm4grpdio {
 793                 fsl,pins = <
 794                         /* DIO3 J16.4 */
 795                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
 796                 >;
 797         };
 798
 799         pinctrl_reg_can1: regcan1grp {
 800                 fsl,pins = <
 801                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 802                 >;
 803         };
 804
 805         pinctrl_uart1: uart1grp {
 806                 fsl,pins = <
 807                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 808                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 809                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 810                 >;
 811         };
 812
 813         pinctrl_uart2: uart2grp {
 814                 fsl,pins = <
 815                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 816                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 817                 >;
 818         };
 819
 820         pinctrl_uart5: uart5grp {
 821                 fsl,pins = <
 822                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 823                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 824                 >;
 825         };
 826
 827         pinctrl_usbotg: usbotggrp {
 828                 fsl,pins = <
 829                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 830                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 831                         MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x17059
 832                 >;
 833         };
 834
 835         pinctrl_usdhc3: usdhc3grp {
 836                 fsl,pins = <
 837                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 838                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 839                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 840                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 841                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 842                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 843                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 844                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 845                 >;
 846         };
 847
 848         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 849                 fsl,pins = <
 850                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 851                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 852                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 853                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 854                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 855                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 856                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 857                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 858                 >;
 859         };
 860
 861         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 862                 fsl,pins = <
 863                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 864                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 865                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 866                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 867                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 868                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 869                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 870                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 871                 >;
 872         };
 873
 874         pinctrl_wdog: wdoggrp {
 875                 fsl,pins = <
 876                         MX6QDL_PAD_SD1_DAT3__WDOG2_B            0x1b0b0
 877                 >;
 878         };
 879 };