1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2013 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
11 /* these are used by bootloader for disabling nodes */
23 bootargs = "console=ttymxc1,115200";
27 compatible = "pwm-backlight";
28 pwms = <&pwm4 0 5000000>;
29 brightness-levels = <0 4 8 16 32 64 128 255>;
30 default-brightness-level = <7>;
34 compatible = "gpio-keys";
38 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
45 interrupt-parent = <&gsc>;
52 interrupt-parent = <&gsc>;
59 interrupt-parent = <&gsc>;
66 interrupt-parent = <&gsc>;
71 label = "switch_hold";
73 interrupt-parent = <&gsc>;
79 compatible = "gpio-leds";
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_gpio_leds>;
85 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
87 linux,default-trigger = "heartbeat";
92 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
93 default-state = "off";
98 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
99 default-state = "off";
104 device_type = "memory";
105 reg = <0x10000000 0x20000000>;
109 compatible = "pps-gpio";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_pps>;
112 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
116 reg_1p0v: regulator-1p0v {
117 compatible = "regulator-fixed";
118 regulator-name = "1P0V";
119 regulator-min-microvolt = <1000000>;
120 regulator-max-microvolt = <1000000>;
124 reg_3p3v: regulator-3p3v {
125 compatible = "regulator-fixed";
126 regulator-name = "3P3V";
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
132 reg_5p0v: regulator-5p0v {
133 compatible = "regulator-fixed";
134 regulator-name = "5P0V";
135 regulator-min-microvolt = <5000000>;
136 regulator-max-microvolt = <5000000>;
140 reg_can1_stby: regulator-can1-stby {
141 compatible = "regulator-fixed";
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_reg_can1>;
144 regulator-name = "can1_stby";
145 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
150 reg_usb_otg_vbus: regulator-usb-otg-vbus {
151 compatible = "regulator-fixed";
152 regulator-name = "usb_otg_vbus";
153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <5000000>;
155 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
160 compatible = "fsl,imx6q-ventana-sgtl5000",
161 "fsl,imx-audio-sgtl5000";
162 model = "sgtl5000-audio";
163 ssi-controller = <&ssi1>;
164 audio-codec = <&codec>;
166 "MIC_IN", "Mic Jack",
167 "Mic Jack", "Mic Bias",
168 "Headphone Jack", "HP_OUT";
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_audmux>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_flexcan1>;
183 xceiver-supply = <®_can1_stby>;
188 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
189 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
190 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
191 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
195 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_ecspi3>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_enet>;
204 phy-mode = "rgmii-id";
205 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_gpmi_nand>;
216 ddc-i2c-bus = <&i2c3>;
221 clock-frequency = <100000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c1>;
227 compatible = "gw,gsc";
229 interrupt-parent = <&gpio1>;
230 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
231 interrupt-controller;
232 #interrupt-cells = <1>;
236 compatible = "gw,gsc-adc";
237 #address-cells = <1>;
321 compatible = "nxp,pca9555";
325 interrupt-parent = <&gsc>;
330 compatible = "atmel,24c02";
336 compatible = "atmel,24c02";
342 compatible = "atmel,24c02";
348 compatible = "atmel,24c02";
354 compatible = "dallas,ds1672";
360 clock-frequency = <100000>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_i2c2>;
366 compatible = "lltc,ltc3676";
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_pmic>;
370 interrupt-parent = <&gpio1>;
371 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
374 /* VDD_SOC (1+R1/R2 = 1.635) */
376 regulator-name = "vddsoc";
377 regulator-min-microvolt = <674400>;
378 regulator-max-microvolt = <1308000>;
379 lltc,fb-voltage-divider = <127000 200000>;
380 regulator-ramp-delay = <7000>;
385 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
387 regulator-name = "vdd1p8";
388 regulator-min-microvolt = <1033310>;
389 regulator-max-microvolt = <2004000>;
390 lltc,fb-voltage-divider = <301000 200000>;
391 regulator-ramp-delay = <7000>;
396 /* VDD_ARM (1+R1/R2 = 1.635) */
398 regulator-name = "vddarm";
399 regulator-min-microvolt = <674400>;
400 regulator-max-microvolt = <1308000>;
401 lltc,fb-voltage-divider = <127000 200000>;
402 regulator-ramp-delay = <7000>;
407 /* VDD_DDR (1+R1/R2 = 2.105) */
409 regulator-name = "vddddr";
410 regulator-min-microvolt = <868310>;
411 regulator-max-microvolt = <1684000>;
412 lltc,fb-voltage-divider = <221000 200000>;
413 regulator-ramp-delay = <7000>;
418 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
420 regulator-name = "vdd2p5";
421 regulator-min-microvolt = <2490375>;
422 regulator-max-microvolt = <2490375>;
423 lltc,fb-voltage-divider = <487000 200000>;
428 /* VDD_AUD_1P8: Audio codec */
430 regulator-name = "vdd1p8a";
431 regulator-min-microvolt = <1800000>;
432 regulator-max-microvolt = <1800000>;
436 /* VDD_HIGH (1+R1/R2 = 4.17) */
438 regulator-name = "vdd3p0";
439 regulator-min-microvolt = <3023250>;
440 regulator-max-microvolt = <3023250>;
441 lltc,fb-voltage-divider = <634000 200000>;
450 clock-frequency = <100000>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_i2c3>;
456 compatible = "fsl,sgtl5000";
458 clocks = <&clks IMX6QDL_CLK_CKO>;
459 VDDA-supply = <®_1p8v>;
460 VDDIO-supply = <®_3p3v>;
463 touchscreen: egalax_ts@4 {
464 compatible = "eeti,egalax_ts";
466 interrupt-parent = <&gpio7>;
468 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
472 compatible = "nxp,fxos8700";
481 fsl,data-mapping = "spwg";
482 fsl,data-width = <18>;
486 native-mode = <&timing0>;
487 timing0: hsd100pxn1 {
488 clock-frequency = <65000000>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_pcie>;
505 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
516 pinctrl-names = "default";
517 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_pwm4>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_uart1>;
535 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_uart2>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_uart5>;
552 vbus-supply = <®_usb_otg_vbus>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_usbotg>;
555 disable-over-current;
564 pinctrl-names = "default", "state_100mhz", "state_200mhz";
565 pinctrl-0 = <&pinctrl_usdhc3>;
566 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
567 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
568 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
569 vmmc-supply = <®_3p3v>;
570 no-1-8-v; /* firmware will remove if board revision supports */
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_wdog>;
577 fsl,ext-reset-output;
581 pinctrl_audmux: audmuxgrp {
583 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
584 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
585 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
586 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
587 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
591 pinctrl_ecspi3: escpi3grp {
593 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
594 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
595 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
596 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
600 pinctrl_enet: enetgrp {
602 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
603 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
604 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
605 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
606 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
607 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
608 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
609 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
610 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
611 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
612 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
613 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
614 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
615 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
616 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
617 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
618 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
622 pinctrl_flexcan1: flexcan1grp {
624 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
625 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
629 pinctrl_gpio_leds: gpioledsgrp {
631 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
632 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
633 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
637 pinctrl_gpmi_nand: gpminandgrp {
639 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
640 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
641 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
642 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
643 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
644 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
645 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
646 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
647 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
648 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
649 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
650 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
651 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
652 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
653 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
657 pinctrl_i2c1: i2c1grp {
659 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
660 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
661 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
665 pinctrl_i2c2: i2c2grp {
667 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
668 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
672 pinctrl_i2c3: i2c3grp {
674 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
675 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
679 pinctrl_pcie: pciegrp {
681 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
685 pinctrl_pmic: pmicgrp {
687 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
691 pinctrl_pps: ppsgrp {
693 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
697 pinctrl_pwm2: pwm2grp {
699 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
703 pinctrl_pwm3: pwm3grp {
705 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
709 pinctrl_pwm4: pwm4grp {
711 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
715 pinctrl_reg_can1: regcan1grp {
717 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
721 pinctrl_uart1: uart1grp {
723 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
724 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
725 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
729 pinctrl_uart2: uart2grp {
731 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
732 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
736 pinctrl_uart5: uart5grp {
738 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
739 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
743 pinctrl_usbotg: usbotggrp {
745 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
746 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
747 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059
751 pinctrl_usdhc3: usdhc3grp {
753 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
754 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
755 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
756 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
757 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
758 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
759 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
760 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
764 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
766 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
767 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
768 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
769 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
770 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
771 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
772 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
773 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
777 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
779 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
780 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
781 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
782 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
783 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
784 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
785 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
786 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
790 pinctrl_wdog: wdoggrp {
792 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0