GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / imx6qdl-aristainetos.dtsi
1 /*
2  * support fot the imx6 based aristainetos board
3  *
4  * Copyright (C) 2014 Heiko Schocher <hs@denx.de>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  */
11
12 #include <dt-bindings/gpio/gpio.h>
13
14 / {
15
16         reg_2p5v: regulator-2p5v {
17                 compatible = "regulator-fixed";
18                 regulator-name = "2P5V";
19                 regulator-min-microvolt = <2500000>;
20                 regulator-max-microvolt = <2500000>;
21                 regulator-always-on;
22         };
23
24         reg_3p3v: regulator-3p3v {
25                 compatible = "regulator-fixed";
26                 regulator-name = "3P3V";
27                 regulator-min-microvolt = <3300000>;
28                 regulator-max-microvolt = <3300000>;
29                 regulator-always-on;
30         };
31
32         reg_usbh1_vbus: regulator-usbh1-vbus {
33                 compatible = "regulator-fixed";
34                 enable-active-high;
35                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
36                 pinctrl-names = "default";
37                 pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>;
38                 regulator-name = "usb_h1_vbus";
39                 regulator-min-microvolt = <5000000>;
40                 regulator-max-microvolt = <5000000>;
41         };
42
43         reg_usbotg_vbus: regulator-usbotg-vbus {
44                 compatible = "regulator-fixed";
45                 enable-active-high;
46                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
47                 pinctrl-names = "default";
48                 pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>;
49                 regulator-name = "usb_otg_vbus";
50                 regulator-min-microvolt = <5000000>;
51                 regulator-max-microvolt = <5000000>;
52         };
53 };
54
55 &audmux {
56         pinctrl-names = "default";
57         pinctrl-0 = <&pinctrl_audmux>;
58         status = "okay";
59 };
60
61 &can1 {
62         pinctrl-names = "default";
63         pinctrl-0 = <&pinctrl_flexcan1>;
64         status = "okay";
65 };
66
67 &can2 {
68         pinctrl-names = "default";
69         pinctrl-0 = <&pinctrl_flexcan2>;
70         status = "okay";
71 };
72
73 &i2c1 {
74         clock-frequency = <100000>;
75         pinctrl-names = "default";
76         pinctrl-0 = <&pinctrl_i2c1>;
77         status = "okay";
78
79         tmp103: tmp103@71 {
80                 compatible = "ti,tmp103";
81                 reg = <0x71>;
82         };
83 };
84
85 &i2c3 {
86         clock-frequency = <100000>;
87         pinctrl-names = "default";
88         pinctrl-0 = <&pinctrl_i2c3>;
89         status = "okay";
90
91         rtc@68 {
92                 compatible = "dallas,m41t00";
93                 reg = <0x68>;
94         };
95 };
96
97 &ecspi4 {
98         cs-gpios = <&gpio3 20 0>;
99         pinctrl-names = "default";
100         pinctrl-0 = <&pinctrl_ecspi4>;
101         status = "okay";
102
103         flash: m25p80@0 {
104                 #address-cells = <1>;
105                 #size-cells = <1>;
106                 compatible = "micron,n25q128a11", "jedec,spi-nor";
107                 spi-max-frequency = <20000000>;
108                 reg = <0>;
109         };
110 };
111
112 &fec {
113         pinctrl-names = "default";
114         pinctrl-0 = <&pinctrl_enet>;
115         phy-mode = "rmii";
116         phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
117         status = "okay";
118 };
119
120 &gpmi {
121         pinctrl-names = "default";
122         pinctrl-0 = <&pinctrl_gpmi_nand>;
123         status = "okay";
124 };
125
126 &pcie {
127         status = "okay";
128 };
129
130 &uart2 {
131         pinctrl-names = "default";
132         pinctrl-0 = <&pinctrl_uart2>;
133         status = "okay";
134 };
135
136
137 &uart4 {
138         pinctrl-names = "default";
139         pinctrl-0 = <&pinctrl_uart4>;
140         uart-has-rtscts;
141         status = "okay";
142 };
143
144 &uart5 {
145         pinctrl-names = "default";
146         pinctrl-0 = <&pinctrl_uart5>;
147         uart-has-rtscts;
148         status = "okay";
149 };
150
151 &usbh1 {
152         vbus-supply = <&reg_usbh1_vbus>;
153         dr_mode = "host";
154         status = "okay";
155 };
156
157 &usbotg {
158         vbus-supply = <&reg_usbotg_vbus>;
159         pinctrl-names = "default";
160         pinctrl-0 = <&pinctrl_usbotg>;
161         disable-over-current;
162         dr_mode = "host";
163         status = "okay";
164 };
165
166 &usdhc1 {
167         pinctrl-names = "default";
168         pinctrl-0 = <&pinctrl_usdhc1>;
169         vmmc-supply = <&reg_3p3v>;
170         cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
171         status = "okay";
172 };
173
174 &usdhc2 {
175         pinctrl-names = "default";
176         pinctrl-0 = <&pinctrl_usdhc2>;
177         vmmc-supply = <&reg_3p3v>;
178         cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
179         status = "okay";
180 };
181
182 &iomuxc {
183         pinctrl-names = "default";
184         pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>;
185
186         imx6qdl-aristainetos {
187                 pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus {
188                         fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>;
189                 };
190
191                 pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus {
192                         fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0>;
193                 };
194
195                 pinctrl_audmux: audmuxgrp {
196                         fsl,pins = <
197                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x1b0b0
198                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x1b0b0
199                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x1b0b0
200                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
201                         >;
202                 };
203
204                 pinctrl_backlight: backlightgrp {
205                         fsl,pins = <
206                                 MX6QDL_PAD_GPIO_9__PWM1_OUT     0x1b0b0
207                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT   0x1b0b0
208                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b0b0
209                         >;
210                 };
211
212                 pinctrl_ecspi2: ecspi2grp {
213                         fsl,pins = <
214                                 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
215                                 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
216                                 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
217                                 MX6QDL_PAD_EIM_D24__GPIO3_IO24  0x100b1
218                         >;
219                 };
220
221                 pinctrl_ecspi4: ecspi4grp {
222                         fsl,pins = <
223                                 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
224                                 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
225                                 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
226                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20  0x100b1
227                                 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
228                         >;
229                 };
230
231                 pinctrl_enet: enetgrp {
232                         fsl,pins = <
233                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
234                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO  0x1b0b0
235                                 MX6QDL_PAD_ENET_MDC__ENET_MDC    0x1b0b0
236                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
237                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
238                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN   0x1b0b0
239                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER   0x1b0b0
240                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
241                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
242                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN  0x1b0b0
243                         >;
244                 };
245
246                 pinctrl_flexcan1: flexcan1grp {
247                         fsl,pins = <
248                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
249                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
250                         >;
251                 };
252
253                 pinctrl_flexcan2: flexcan2grp {
254                         fsl,pins = <
255                                 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX        0x1b0b0
256                                 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX        0x1b0b0
257                                 >;
258                 };
259
260                 pinctrl_gpio: gpiogrp {
261                         fsl,pins = <
262                                 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
263                                 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
264                                 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
265                                 MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0
266                                 MX6QDL_PAD_GPIO_3__GPIO1_IO03   0x1b0b0
267                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x1b0b0
268                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05   0x1b0b0
269                                 MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0
270                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07   0x1b0b0
271                                 MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0
272                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
273                         >;
274                 };
275
276                 pinctrl_gpmi_nand: gpminandgrp {
277                         fsl,pins = <
278                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
279                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
280                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
281                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
282                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
283                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
284                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
285                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
286                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
287                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
288                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
289                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
290                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
291                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
292                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
293                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
294                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
295                         >;
296                 };
297
298                 pinctrl_hog: hoggrp {
299                         fsl,pins = <
300                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29   0x10
301                         >;
302                 };
303
304                 pinctrl_i2c1: i2c1grp {
305                         fsl,pins = <
306                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
307                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
308                         >;
309                 };
310
311                 pinctrl_i2c2: i2c2grp {
312                         fsl,pins = <
313                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
314                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
315                         >;
316                 };
317
318                 pinctrl_i2c3: i2c3grp {
319                         fsl,pins = <
320                                 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
321                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
322                         >;
323                 };
324
325                 pinctrl_ipu_disp: ipudisp1grp {
326                         fsl,pins = <
327                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x10
328                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0x10
329                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x10
330                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x10
331                                 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20                 0x20000
332                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x10
333                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
334                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
335                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x10
336                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x10
337                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x10
338                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x10
339                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x10
340                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x10
341                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x10
342                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x10
343                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x10
344                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x10
345                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x10
346                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x10
347                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x10
348                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x10
349                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x10
350                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x10
351                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x10
352                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x10
353                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x10
354                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x10
355                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x10
356                                 >;
357                 };
358
359                 pinctrl_uart2: uart2grp {
360                         fsl,pins = <
361                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
362                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
363                         >;
364                 };
365
366                 pinctrl_uart4: uart4grp {
367                         fsl,pins = <
368                                 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
369                                 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
370                                 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
371                                 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
372                         >;
373                 };
374
375                 pinctrl_uart5: uart5grp {
376                         fsl,pins = <
377                                 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
378                                 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
379                         >;
380                 };
381
382                 pinctrl_usbotg: usbotggrp {
383                         fsl,pins = <
384                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
385                         >;
386                 };
387
388                 pinctrl_usdhc1: usdhc1grp {
389                         fsl,pins = <
390                                 MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
391                                 MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
392                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
393                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
394                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
395                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
396                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
397                         >;
398                 };
399
400                 pinctrl_usdhc2: usdhc2grp {
401                         fsl,pins = <
402                                 MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
403                                 MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
404                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
405                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
406                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
407                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
408                                 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
409                         >;
410                 };
411         };
412 };