1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2014-2022 Toradex
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pwm/pwm.h>
12 model = "Toradex Apalis iMX6Q/D Module";
13 compatible = "toradex,apalis_imx6q", "fsl,imx6q";
15 /* Will be filled by the bootloader */
17 device_type = "memory";
21 backlight: backlight {
22 compatible = "pwm-backlight";
23 brightness-levels = <0 45 63 88 119 158 203 255>;
24 default-brightness-level = <4>;
25 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_bl_on>;
28 power-supply = <®_module_3v3>;
29 pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>;
33 clk_ov5640_osc: clk-ov5640-osc {
34 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
40 compatible = "gpio-keys";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_gpio_keys>;
45 debounce-interval = <10>;
46 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_WAKEUP>;
54 compatible = "fsl,imx-parallel-display";
57 interface-pix-fmt = "rgb24";
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
65 lcd_display_in: endpoint {
66 remote-endpoint = <&ipu1_di1_disp1>;
73 lcd_display_out: endpoint {
74 remote-endpoint = <&lcd_panel_in>;
79 panel_dpi: panel-dpi {
80 compatible = "edt,et057090dhu";
81 backlight = <&backlight>;
86 lcd_panel_in: endpoint {
87 remote-endpoint = <&lcd_display_out>;
92 panel_lvds: panel-lvds {
93 compatible = "panel-lvds";
94 backlight = <&backlight>;
98 lvds_panel_in: endpoint {
99 remote-endpoint = <&lvds0_out>;
104 reg_module_3v3: regulator-module-3v3 {
105 compatible = "regulator-fixed";
107 regulator-max-microvolt = <3300000>;
108 regulator-min-microvolt = <3300000>;
109 regulator-name = "+V3.3";
112 reg_module_3v3_audio: regulator-module-3v3-audio {
113 compatible = "regulator-fixed";
115 regulator-max-microvolt = <3300000>;
116 regulator-min-microvolt = <3300000>;
117 regulator-name = "+V3.3_AUDIO";
120 reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd {
121 compatible = "regulator-fixed";
123 regulator-max-microvolt = <1800000>;
124 regulator-min-microvolt = <1800000>;
125 regulator-name = "DOVDD/DVDD_1.8V";
126 /* Note: The CSI module uses on-board 3.3V_SW supply */
127 vin-supply = <®_module_3v3>;
130 reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd {
131 compatible = "regulator-fixed";
133 regulator-max-microvolt = <2800000>;
134 regulator-min-microvolt = <2800000>;
135 regulator-name = "AVDD/AFVDD_2.8V";
136 /* Note: The CSI module uses on-board 3.3V_SW supply */
137 vin-supply = <®_module_3v3>;
140 reg_usb_otg_vbus: regulator-usb-otg-vbus {
141 compatible = "regulator-fixed";
143 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
146 regulator-max-microvolt = <5000000>;
147 regulator-min-microvolt = <5000000>;
148 regulator-name = "usb_otg_vbus";
152 /* on module USB hub */
153 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
154 compatible = "regulator-fixed";
156 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
159 regulator-max-microvolt = <5000000>;
160 regulator-min-microvolt = <5000000>;
161 regulator-name = "usb_host_vbus_hub";
162 startup-delay-us = <2000>;
166 reg_usb_host_vbus: regulator-usb-host-vbus {
167 compatible = "regulator-fixed";
169 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
172 regulator-max-microvolt = <5000000>;
173 regulator-min-microvolt = <5000000>;
174 regulator-name = "usb_host_vbus";
175 vin-supply = <®_usb_host_vbus_hub>;
180 compatible = "fsl,imx-audio-sgtl5000";
181 audio-codec = <&codec>;
183 "LINE_IN", "Line In Jack",
184 "MIC_IN", "Mic Jack",
185 "Mic Jack", "Mic Bias",
186 "Headphone Jack", "HP_OUT";
187 model = "imx6q-apalis-sgtl5000";
190 ssi-controller = <&ssi1>;
193 sound_spdif: sound-spdif {
194 compatible = "fsl,imx-audio-spdif";
195 spdif-controller = <&spdif>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_audmux>;
210 pinctrl-names = "default", "sleep";
211 pinctrl-0 = <&pinctrl_flexcan1_default>;
212 pinctrl-1 = <&pinctrl_flexcan1_sleep>;
217 pinctrl-names = "default", "sleep";
218 pinctrl-0 = <&pinctrl_flexcan2_default>;
219 pinctrl-1 = <&pinctrl_flexcan2_sleep>;
224 fsl,pmic-stby-poweroff;
229 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_ecspi1>;
237 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_ecspi2>;
244 gpio-line-names = "MXM3_84",
272 gpio-line-names = "MXM3_148",
307 gpio-line-names = "MXM3_271",
342 gpio-line-names = "",
366 gpio-line-names = "MXM3_159",
401 gpio-line-names = "MXM3_183",
421 gpio-line-names = "",
438 #address-cells = <1>;
444 ipu1_csi0_mux_from_parallel_sensor: endpoint {
445 remote-endpoint = <&adv7280_to_ipu1_csi0_mux>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_enet>;
454 phy-mode = "rgmii-id";
455 phy-handle = <ðphy>;
456 phy-reset-duration = <10>;
457 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
461 #address-cells = <1>;
464 ethphy: ethernet-phy@7 {
465 interrupt-parent = <&gpio1>;
466 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>;
478 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
480 clock-frequency = <100000>;
481 pinctrl-names = "default", "gpio";
482 pinctrl-0 = <&pinctrl_i2c1>;
483 pinctrl-1 = <&pinctrl_i2c1_gpio>;
484 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
485 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
488 atmel_mxt_ts: touchscreen@4a {
489 compatible = "atmel,maxtouch";
490 /* These GPIOs are muxed with the iomuxc node */
491 interrupt-parent = <&gpio6>;
492 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */
494 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */
500 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
501 * touch screen controller
504 clock-frequency = <100000>;
505 pinctrl-names = "default", "gpio";
506 pinctrl-0 = <&pinctrl_i2c2>;
507 pinctrl-1 = <&pinctrl_i2c2_gpio>;
508 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
509 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
513 compatible = "fsl,pfuze100";
514 fsl,pmic-stby-poweroff;
521 regulator-max-microvolt = <1875000>;
522 regulator-min-microvolt = <300000>;
523 regulator-ramp-delay = <6250>;
529 regulator-max-microvolt = <1875000>;
530 regulator-min-microvolt = <300000>;
531 regulator-ramp-delay = <6250>;
537 regulator-max-microvolt = <1975000>;
538 regulator-min-microvolt = <400000>;
544 regulator-max-microvolt = <5150000>;
545 regulator-min-microvolt = <5000000>;
551 regulator-max-microvolt = <3000000>;
552 regulator-min-microvolt = <1000000>;
563 regulator-max-microvolt = <1550000>;
564 regulator-min-microvolt = <800000>;
570 regulator-max-microvolt = <1550000>;
571 regulator-min-microvolt = <800000>;
577 regulator-max-microvolt = <3300000>;
578 regulator-min-microvolt = <1800000>;
584 regulator-max-microvolt = <1800000>;
585 regulator-min-microvolt = <1800000>;
591 regulator-max-microvolt = <3300000>;
592 regulator-min-microvolt = <1800000>;
598 regulator-max-microvolt = <3300000>;
599 regulator-min-microvolt = <1800000>;
605 compatible = "fsl,sgtl5000";
606 #sound-dai-cells = <0>;
607 clocks = <&clks IMX6QDL_CLK_CKO>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&pinctrl_sgtl5000>;
611 VDDA-supply = <®_module_3v3_audio>;
612 VDDIO-supply = <®_module_3v3>;
613 VDDD-supply = <&vgen4_reg>;
616 /* STMPE811 touch screen controller */
618 compatible = "st,stmpe811";
621 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
622 interrupt-controller;
623 interrupt-parent = <&gpio4>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&pinctrl_touch_int>;
628 /* 3.25 MHz ADC clock speed */
632 /* internal ADC reference */
634 /* ADC conversion time: 80 clocks */
635 st,sample-time = <4>;
637 stmpe_ts: stmpe_touchscreen {
638 compatible = "st,stmpe-ts";
639 /* 8 sample average control */
641 /* 7 length fractional part in z */
644 * 50 mA typical 80 mA max touchscreen drivers
645 * current limit value
648 /* 1 ms panel driver settling time */
650 /* 5 ms touch detect interrupt delay */
651 st,touch-det-delay = <5>;
655 stmpe_adc: stmpe_adc {
656 compatible = "st,stmpe-adc";
657 #io-channel-cells = <1>;
658 /* forbid to use ADC channels 3-0 (touch) */
659 st,norequest-mask = <0x0F>;
665 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
669 clock-frequency = <100000>;
670 pinctrl-names = "default", "gpio";
671 pinctrl-0 = <&pinctrl_i2c3>;
672 pinctrl-1 = <&pinctrl_i2c3_gpio>;
673 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
674 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
677 adv_7280: adv7280@21 {
678 compatible = "adi,adv7280";
680 pinctrl-names = "default";
681 pinctrl-0 = <&pinctrl_ipu1_csi0>;
686 adv7280_to_ipu1_csi0_mux: endpoint {
688 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
693 ov5640_csi_cam: ov5640_mipi@3c {
694 compatible = "ovti,ov5640";
695 AVDD-supply = <®_ov5640_2v8_a_vdd>;
696 DOVDD-supply = <®_ov5640_1v8_d_o_vdd>;
697 DVDD-supply = <®_ov5640_1v8_d_o_vdd>;
698 clock-names = "xclk";
699 clocks = <&clks IMX6QDL_CLK_CKO2>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_cam_mclk>;
702 /* These GPIOs are muxed with the iomuxc node */
703 powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
705 reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
709 ov5640_to_mipi_csi2: endpoint {
712 remote-endpoint = <&mipi_csi_from_ov5640>;
719 remote-endpoint = <&lcd_display_in>;
727 lvds0_out: endpoint {
728 remote-endpoint = <&lvds_panel_in>;
734 fsl,data-mapping = "spwg";
735 fsl,data-width = <18>;
740 lvds1_out: endpoint {
747 #address-cells = <1>;
754 mipi_csi_from_ov5640: endpoint {
757 remote-endpoint = <&ov5640_to_mipi_csi2>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&pinctrl_pwm1>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&pinctrl_pwm2>;
775 pinctrl-names = "default";
776 pinctrl-0 = <&pinctrl_pwm3>;
781 pinctrl-names = "default";
782 pinctrl-0 = <&pinctrl_pwm4>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&pinctrl_spdif>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
806 pinctrl-names = "default";
807 pinctrl-0 = <&pinctrl_uart2_dte>;
814 pinctrl-names = "default";
815 pinctrl-0 = <&pinctrl_uart4_dte>;
821 pinctrl-names = "default";
822 pinctrl-0 = <&pinctrl_uart5_dte>;
827 disable-over-current;
828 pinctrl-names = "default";
829 pinctrl-0 = <&pinctrl_usbotg>;
836 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
841 vqmmc-supply = <®_module_3v3>;
850 pinctrl-names = "default";
851 pinctrl-0 = <&pinctrl_usdhc2>;
852 vqmmc-supply = <®_module_3v3>;
861 pinctrl-names = "default";
862 pinctrl-0 = <&pinctrl_usdhc3>;
863 vqmmc-supply = <®_module_3v3>;
872 /* Mux the Apalis GPIOs */
873 pinctrl-names = "default";
874 pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
875 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
876 &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
877 &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
880 pinctrl_apalis_gpio1: apalisgpio1grp {
882 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
886 pinctrl_apalis_gpio2: apalisgpio2grp {
888 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
892 pinctrl_apalis_gpio3: apalisgpio3grp {
894 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
898 pinctrl_apalis_gpio4: apalisgpio4grp {
900 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
904 pinctrl_apalis_gpio5: apalisgpio5grp {
906 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
910 pinctrl_apalis_gpio6: apalisgpio6grp {
912 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
916 pinctrl_apalis_gpio7: apalisgpio7grp {
918 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
922 pinctrl_apalis_gpio8: apalisgpio8grp {
924 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
928 pinctrl_audmux: audmuxgrp {
930 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
931 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
932 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
933 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
937 pinctrl_cam_mclk: cammclkgrp {
940 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
944 pinctrl_ecspi1: ecspi1grp {
946 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
947 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
948 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
950 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
954 pinctrl_ecspi2: ecspi2grp {
956 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
957 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
958 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
960 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
964 pinctrl_enet: enetgrp {
966 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
967 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
968 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
969 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
970 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
971 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
972 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
973 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
974 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
975 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
976 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
977 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
978 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
979 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
980 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
981 /* Ethernet PHY reset */
982 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
983 /* Ethernet PHY interrupt */
984 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
988 pinctrl_flexcan1_default: flexcan1defgrp {
990 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
991 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
995 pinctrl_flexcan1_sleep: flexcan1slpgrp {
997 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
998 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
1002 pinctrl_flexcan2_default: flexcan2defgrp {
1004 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
1005 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
1008 pinctrl_flexcan2_sleep: flexcan2slpgrp {
1010 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
1011 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
1015 pinctrl_gpio_bl_on: gpioblongrp {
1017 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
1021 pinctrl_gpio_keys: gpio1io04grp {
1024 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
1028 pinctrl_hdmi_cec: hdmicecgrp {
1030 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
1034 pinctrl_hdmi_ddc: hdmiddcgrp {
1036 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
1037 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
1041 pinctrl_i2c1: i2c1grp {
1043 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
1044 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
1048 pinctrl_i2c1_gpio: i2c1gpiogrp {
1050 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
1051 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
1055 pinctrl_i2c2: i2c2grp {
1057 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
1058 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
1062 pinctrl_i2c2_gpio: i2c2gpiogrp {
1064 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
1065 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
1069 pinctrl_i2c3: i2c3grp {
1071 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
1072 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
1076 pinctrl_i2c3_gpio: i2c3gpiogrp {
1078 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
1079 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
1083 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
1085 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
1086 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
1087 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
1088 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
1089 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
1090 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
1091 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
1092 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
1093 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
1094 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
1095 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
1099 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
1101 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
1103 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
1105 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
1107 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
1108 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
1109 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
1110 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
1111 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
1112 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
1113 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
1114 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
1115 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
1116 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
1117 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
1118 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
1119 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
1120 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
1121 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
1122 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
1123 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
1124 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
1125 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
1126 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
1127 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
1128 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
1129 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
1130 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
1131 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
1135 pinctrl_ipu2_vdac: ipu2vdacgrp {
1137 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
1138 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
1139 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
1140 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
1141 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
1142 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
1143 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
1144 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
1145 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
1146 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
1147 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
1148 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
1149 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
1150 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
1151 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
1152 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
1153 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
1154 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
1155 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
1156 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
1160 pinctrl_mmc_cd: mmccdgrp {
1163 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
1167 pinctrl_pwm1: pwm1grp {
1169 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
1173 pinctrl_pwm2: pwm2grp {
1175 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
1179 pinctrl_pwm3: pwm3grp {
1181 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1185 pinctrl_pwm4: pwm4grp {
1187 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
1191 pinctrl_regulator_usbh_pwr: regusbhpwrgrp {
1194 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
1198 pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp {
1201 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
1205 pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp {
1207 /* USBO1 power en */
1208 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
1212 pinctrl_reset_moci: resetmocigrp {
1214 /* RESET_MOCI control */
1215 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
1219 pinctrl_sd_cd: sdcdgrp {
1222 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
1226 pinctrl_sgtl5000: sgtl5000grp {
1228 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
1232 pinctrl_spdif: spdifgrp {
1234 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1235 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1239 pinctrl_touch_int: touchintgrp {
1241 /* STMPE811 interrupt */
1242 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
1246 /* Additional DTR, DSR, DCD */
1247 pinctrl_uart1_ctrl: uart1ctrlgrp {
1249 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
1250 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
1251 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
1255 pinctrl_uart1_dce: uart1dcegrp {
1257 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1258 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1263 pinctrl_uart1_dte: uart1dtegrp {
1265 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
1266 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
1267 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
1268 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
1272 pinctrl_uart2_dce: uart2dcegrp {
1274 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
1275 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
1280 pinctrl_uart2_dte: uart2dtegrp {
1282 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
1283 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
1284 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
1285 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
1289 pinctrl_uart4_dce: uart4dcegrp {
1291 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1292 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1297 pinctrl_uart4_dte: uart4dtegrp {
1299 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
1300 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
1304 pinctrl_uart5_dce: uart5dcegrp {
1306 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
1307 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
1312 pinctrl_uart5_dte: uart5dtegrp {
1314 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
1315 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
1319 pinctrl_usbotg: usbotggrp {
1321 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1325 pinctrl_usdhc1_4bit: usdhc1-4bitgrp {
1327 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
1328 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
1329 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
1330 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
1331 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
1332 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
1336 pinctrl_usdhc1_8bit: usdhc1-8bitgrp {
1338 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
1339 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
1340 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
1341 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
1345 pinctrl_usdhc2: usdhc2grp {
1347 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
1348 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
1349 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
1350 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
1351 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
1352 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
1356 pinctrl_usdhc3: usdhc3grp {
1358 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1359 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1360 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1361 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1362 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1363 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1364 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1365 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1366 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1367 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1369 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059