arch/arm/boot/dts/imx6qdl-apalis.dtsi

   1 /*
   2  * Copyright 2014-2017 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Apalis iMX6Q/D Module";
  48         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  49
  50         /* Will be filled by the bootloader */
  51         memory@10000000 {
  52                 reg = <0x10000000 0>;
  53         };
  54
  55         backlight: backlight {
  56                 compatible = "pwm-backlight";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  59                 pwms = <&pwm4 0 5000000>;
  60                 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  61                 status = "disabled";
  62         };
  63
  64         reg_module_3v3: regulator-module-3v3 {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "+V3.3";
  67                 regulator-min-microvolt = <3300000>;
  68                 regulator-max-microvolt = <3300000>;
  69                 regulator-always-on;
  70         };
  71
  72         reg_module_3v3_audio: regulator-module-3v3-audio {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "+V3.3_AUDIO";
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 regulator-always-on;
  78         };
  79
  80         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  81                 compatible = "regulator-fixed";
  82                 pinctrl-names = "default";
  83                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
  84                 regulator-name = "usb_otg_vbus";
  85                 regulator-min-microvolt = <5000000>;
  86                 regulator-max-microvolt = <5000000>;
  87                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  88                 enable-active-high;
  89                 status = "disabled";
  90         };
  91
  92         /* on module USB hub */
  93         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
  94                 compatible = "regulator-fixed";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
  97                 regulator-name = "usb_host_vbus_hub";
  98                 regulator-min-microvolt = <5000000>;
  99                 regulator-max-microvolt = <5000000>;
 100                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 101                 startup-delay-us = <2000>;
 102                 enable-active-high;
 103                 status = "okay";
 104         };
 105
 106         reg_usb_host_vbus: regulator-usb-host-vbus {
 107                 compatible = "regulator-fixed";
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
 110                 regulator-name = "usb_host_vbus";
 111                 regulator-min-microvolt = <5000000>;
 112                 regulator-max-microvolt = <5000000>;
 113                 gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
 114                 enable-active-high;
 115                 vin-supply = <&reg_usb_host_vbus_hub>;
 116                 status = "disabled";
 117         };
 118
 119         sound {
 120                 compatible = "fsl,imx-audio-sgtl5000";
 121                 model = "imx6q-apalis-sgtl5000";
 122                 ssi-controller = <&ssi1>;
 123                 audio-codec = <&codec>;
 124                 audio-routing =
 125                         "LINE_IN", "Line In Jack",
 126                         "MIC_IN", "Mic Jack",
 127                         "Mic Jack", "Mic Bias",
 128                         "Headphone Jack", "HP_OUT";
 129                 mux-int-port = <1>;
 130                 mux-ext-port = <4>;
 131         };
 132
 133         sound_spdif: sound-spdif {
 134                 compatible = "fsl,imx-audio-spdif";
 135                 model = "imx-spdif";
 136                 spdif-controller = <&spdif>;
 137                 spdif-in;
 138                 spdif-out;
 139                 status = "disabled";
 140         };
 141 };
 142
 143 &audmux {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_audmux>;
 146         status = "okay";
 147 };
 148
 149 &can1 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_flexcan1>;
 152         status = "disabled";
 153 };
 154
 155 &can2 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_flexcan2>;
 158         status = "disabled";
 159 };
 160
 161 /* Apalis SPI1 */
 162 &ecspi1 {
 163         cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_ecspi1>;
 166         status = "disabled";
 167 };
 168
 169 /* Apalis SPI2 */
 170 &ecspi2 {
 171         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_ecspi2>;
 174         status = "disabled";
 175 };
 176
 177 &fec {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_enet>;
 180         phy-mode = "rgmii";
 181         phy-handle = <&ethphy>;
 182         phy-reset-duration = <10>;
 183         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 184         status = "okay";
 185
 186         mdio {
 187                 #address-cells = <1>;
 188                 #size-cells = <0>;
 189
 190                 ethphy: ethernet-phy@7 {
 191                         interrupt-parent = <&gpio1>;
 192                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 193                         reg = <7>;
 194                 };
 195         };
 196 };
 197
 198 &hdmi {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 201         status = "disabled";
 202 };
 203
 204 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 205 &i2c1 {
 206         clock-frequency = <100000>;
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_i2c1>;
 209         status = "disabled";
 210 };
 211
 212 /*
 213  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 214  * touch screen controller
 215  */
 216 &i2c2 {
 217         clock-frequency = <100000>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_i2c2>;
 220         status = "okay";
 221
 222         pmic: pfuze100@8 {
 223                 compatible = "fsl,pfuze100";
 224                 reg = <0x08>;
 225
 226                 regulators {
 227                         sw1a_reg: sw1ab {
 228                                 regulator-min-microvolt = <300000>;
 229                                 regulator-max-microvolt = <1875000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                                 regulator-ramp-delay = <6250>;
 233                         };
 234
 235                         sw1c_reg: sw1c {
 236                                 regulator-min-microvolt = <300000>;
 237                                 regulator-max-microvolt = <1875000>;
 238                                 regulator-boot-on;
 239                                 regulator-always-on;
 240                                 regulator-ramp-delay = <6250>;
 241                         };
 242
 243                         sw3a_reg: sw3a {
 244                                 regulator-min-microvolt = <400000>;
 245                                 regulator-max-microvolt = <1975000>;
 246                                 regulator-boot-on;
 247                                 regulator-always-on;
 248                         };
 249
 250                         swbst_reg: swbst {
 251                                 regulator-min-microvolt = <5000000>;
 252                                 regulator-max-microvolt = <5150000>;
 253                                 regulator-boot-on;
 254                                 regulator-always-on;
 255                         };
 256
 257                         snvs_reg: vsnvs {
 258                                 regulator-min-microvolt = <1000000>;
 259                                 regulator-max-microvolt = <3000000>;
 260                                 regulator-boot-on;
 261                                 regulator-always-on;
 262                         };
 263
 264                         vref_reg: vrefddr {
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                         };
 268
 269                         vgen1_reg: vgen1 {
 270                                 regulator-min-microvolt = <800000>;
 271                                 regulator-max-microvolt = <1550000>;
 272                                 regulator-boot-on;
 273                                 regulator-always-on;
 274                         };
 275
 276                         vgen2_reg: vgen2 {
 277                                 regulator-min-microvolt = <800000>;
 278                                 regulator-max-microvolt = <1550000>;
 279                                 regulator-boot-on;
 280                                 regulator-always-on;
 281                         };
 282
 283                         vgen3_reg: vgen3 {
 284                                 regulator-min-microvolt = <1800000>;
 285                                 regulator-max-microvolt = <3300000>;
 286                                 regulator-boot-on;
 287                                 regulator-always-on;
 288                         };
 289
 290                         vgen4_reg: vgen4 {
 291                                 regulator-min-microvolt = <1800000>;
 292                                 regulator-max-microvolt = <1800000>;
 293                                 regulator-boot-on;
 294                                 regulator-always-on;
 295                         };
 296
 297                         vgen5_reg: vgen5 {
 298                                 regulator-min-microvolt = <1800000>;
 299                                 regulator-max-microvolt = <3300000>;
 300                                 regulator-boot-on;
 301                                 regulator-always-on;
 302                         };
 303
 304                         vgen6_reg: vgen6 {
 305                                 regulator-min-microvolt = <1800000>;
 306                                 regulator-max-microvolt = <3300000>;
 307                                 regulator-boot-on;
 308                                 regulator-always-on;
 309                         };
 310                 };
 311         };
 312
 313         codec: sgtl5000@a {
 314                 compatible = "fsl,sgtl5000";
 315                 reg = <0x0a>;
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&pinctrl_sgtl5000>;
 318                 clocks = <&clks IMX6QDL_CLK_CKO>;
 319                 VDDA-supply = <&reg_module_3v3_audio>;
 320                 VDDIO-supply = <&reg_module_3v3>;
 321                 VDDD-supply = <&vgen4_reg>;
 322         };
 323
 324         /* STMPE811 touch screen controller */
 325         stmpe811@41 {
 326                 compatible = "st,stmpe811";
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&pinctrl_touch_int>;
 329                 reg = <0x41>;
 330                 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 331                 interrupt-parent = <&gpio4>;
 332                 interrupt-controller;
 333                 id = <0>;
 334                 blocks = <0x5>;
 335                 irq-trigger = <0x1>;
 336
 337                 stmpe_touchscreen {
 338                         compatible = "st,stmpe-ts";
 339                         /* 3.25 MHz ADC clock speed */
 340                         st,adc-freq = <1>;
 341                         /* 8 sample average control */
 342                         st,ave-ctrl = <3>;
 343                         /* 7 length fractional part in z */
 344                         st,fraction-z = <7>;
 345                         /*
 346                          * 50 mA typical 80 mA max touchscreen drivers
 347                          * current limit value
 348                          */
 349                         st,i-drive = <1>;
 350                         /* 12-bit ADC */
 351                         st,mod-12b = <1>;
 352                         /* internal ADC reference */
 353                         st,ref-sel = <0>;
 354                         /* ADC converstion time: 80 clocks */
 355                         st,sample-time = <4>;
 356                         /* 1 ms panel driver settling time */
 357                         st,settling = <3>;
 358                         /* 5 ms touch detect interrupt delay */
 359                         st,touch-det-delay = <5>;
 360                 };
 361         };
 362 };
 363
 364 /*
 365  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 366  * board)
 367  */
 368 &i2c3 {
 369         clock-frequency = <100000>;
 370         pinctrl-names = "default", "recovery";
 371         pinctrl-0 = <&pinctrl_i2c3>;
 372         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 373         scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
 374         sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 375         status = "disabled";
 376 };
 377
 378 &pwm1 {
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_pwm1>;
 381         status = "disabled";
 382 };
 383
 384 &pwm2 {
 385         pinctrl-names = "default";
 386         pinctrl-0 = <&pinctrl_pwm2>;
 387         status = "disabled";
 388 };
 389
 390 &pwm3 {
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&pinctrl_pwm3>;
 393         status = "disabled";
 394 };
 395
 396 &pwm4 {
 397         pinctrl-names = "default";
 398         pinctrl-0 = <&pinctrl_pwm4>;
 399         status = "disabled";
 400 };
 401
 402 &spdif {
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_spdif>;
 405         status = "disabled";
 406 };
 407
 408 &ssi1 {
 409         status = "okay";
 410 };
 411
 412 &uart1 {
 413         pinctrl-names = "default";
 414         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 415         fsl,dte-mode;
 416         uart-has-rtscts;
 417         status = "disabled";
 418 };
 419
 420 &uart2 {
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&pinctrl_uart2_dte>;
 423         fsl,dte-mode;
 424         uart-has-rtscts;
 425         status = "disabled";
 426 };
 427
 428 &uart4 {
 429         pinctrl-names = "default";
 430         pinctrl-0 = <&pinctrl_uart4_dte>;
 431         fsl,dte-mode;
 432         status = "disabled";
 433 };
 434
 435 &uart5 {
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&pinctrl_uart5_dte>;
 438         fsl,dte-mode;
 439         status = "disabled";
 440 };
 441
 442 &usbotg {
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_usbotg>;
 445         disable-over-current;
 446         status = "disabled";
 447 };
 448
 449 /* MMC1 */
 450 &usdhc1 {
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
 453         vqmmc-supply = <&reg_module_3v3>;
 454         bus-width = <8>;
 455         disable-wp;
 456         no-1-8-v;
 457         status = "disabled";
 458 };
 459
 460 /* SD1 */
 461 &usdhc2 {
 462         pinctrl-names = "default";
 463         pinctrl-0 = <&pinctrl_usdhc2>;
 464         vqmmc-supply = <&reg_module_3v3>;
 465         bus-width = <4>;
 466         disable-wp;
 467         no-1-8-v;
 468         status = "disabled";
 469 };
 470
 471 /* eMMC */
 472 &usdhc3 {
 473         pinctrl-names = "default";
 474         pinctrl-0 = <&pinctrl_usdhc3>;
 475         vqmmc-supply = <&reg_module_3v3>;
 476         bus-width = <8>;
 477         no-1-8-v;
 478         non-removable;
 479         status = "okay";
 480 };
 481
 482 &weim {
 483         status = "disabled";
 484 };
 485
 486 &iomuxc {
 487         /* pins used on module */
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&pinctrl_reset_moci>;
 490
 491         pinctrl_apalis_gpio1: gpio2io04grp {
 492                 fsl,pins = <
 493                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 494                 >;
 495         };
 496
 497         pinctrl_apalis_gpio2: gpio2io05grp {
 498                 fsl,pins = <
 499                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 500                 >;
 501         };
 502
 503         pinctrl_apalis_gpio3: gpio2io06grp {
 504                 fsl,pins = <
 505                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 506                 >;
 507         };
 508
 509         pinctrl_apalis_gpio4: gpio2io07grp {
 510                 fsl,pins = <
 511                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 512                 >;
 513         };
 514
 515         pinctrl_apalis_gpio5: gpio6io10grp {
 516                 fsl,pins = <
 517                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 518                 >;
 519         };
 520
 521         pinctrl_apalis_gpio6: gpio6io09grp {
 522                 fsl,pins = <
 523                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 524                 >;
 525         };
 526
 527         pinctrl_apalis_gpio7: gpio1io02grp {
 528                 fsl,pins = <
 529                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 530                 >;
 531         };
 532
 533         pinctrl_apalis_gpio8: gpio1io06grp {
 534                 fsl,pins = <
 535                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 536                 >;
 537         };
 538
 539         pinctrl_audmux: audmuxgrp {
 540                 fsl,pins = <
 541                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 542                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 543                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 544                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 545                 >;
 546         };
 547
 548         pinctrl_cam_mclk: cammclkgrp {
 549                 fsl,pins = <
 550                         /* CAM sys_mclk */
 551                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 552                 >;
 553         };
 554
 555         pinctrl_ecspi1: ecspi1grp {
 556                 fsl,pins = <
 557                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
 558                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
 559                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
 560                         /* SPI1 cs */
 561                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
 562                 >;
 563         };
 564
 565         pinctrl_ecspi2: ecspi2grp {
 566                 fsl,pins = <
 567                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 568                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 569                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 570                         /* SPI2 cs */
 571                         MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
 572                 >;
 573         };
 574
 575         pinctrl_enet: enetgrp {
 576                 fsl,pins = <
 577                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 578                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 579                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 580                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 581                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 582                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 583                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 584                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 585                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 586                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 587                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 588                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 589                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 590                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 591                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 592                         /* Ethernet PHY reset */
 593                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 594                         /* Ethernet PHY interrupt */
 595                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 596                 >;
 597         };
 598
 599         pinctrl_flexcan1: flexcan1grp {
 600                 fsl,pins = <
 601                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 602                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 603                 >;
 604         };
 605
 606         pinctrl_flexcan2: flexcan2grp {
 607                 fsl,pins = <
 608                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
 609                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
 610                 >;
 611         };
 612
 613         pinctrl_gpio_bl_on: gpioblon {
 614                 fsl,pins = <
 615                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 616                 >;
 617         };
 618
 619         pinctrl_gpio_keys: gpio1io04grp {
 620                 fsl,pins = <
 621                         /* Power button */
 622                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
 623                 >;
 624         };
 625
 626         pinctrl_hdmi_cec: hdmicecgrp {
 627                 fsl,pins = <
 628                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 629                 >;
 630         };
 631
 632         pinctrl_hdmi_ddc: hdmiddcgrp {
 633                 fsl,pins = <
 634                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 635                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 636                 >;
 637         };
 638
 639         pinctrl_i2c1: i2c1grp {
 640                 fsl,pins = <
 641                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 642                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 643                 >;
 644         };
 645
 646         pinctrl_i2c2: i2c2grp {
 647                 fsl,pins = <
 648                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 649                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 650                 >;
 651         };
 652
 653         pinctrl_i2c3: i2c3grp {
 654                 fsl,pins = <
 655                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 656                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 657                 >;
 658         };
 659
 660         pinctrl_i2c3_recovery: i2c3recoverygrp {
 661                 fsl,pins = <
 662                         MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
 663                         MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
 664                 >;
 665         };
 666
 667         pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
 668                 fsl,pins = <
 669                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
 670                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
 671                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
 672                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
 673                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
 674                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
 675                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
 676                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
 677                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
 678                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
 679                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
 680                 >;
 681         };
 682
 683         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 684                 fsl,pins = <
 685                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
 686                         /* DE */
 687                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
 688                         /* HSync */
 689                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
 690                         /* VSync */
 691                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
 692                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
 693                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
 694                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
 695                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
 696                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
 697                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
 698                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
 699                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
 700                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
 701                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
 702                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
 703                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
 704                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
 705                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
 706                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
 707                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
 708                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
 709                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
 710                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
 711                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
 712                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
 713                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
 714                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
 715                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
 716                 >;
 717         };
 718
 719         pinctrl_ipu2_vdac: ipu2vdacgrp {
 720                 fsl,pins = <
 721                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
 722                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
 723                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
 724                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
 725                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
 726                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
 727                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
 728                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
 729                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
 730                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
 731                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
 732                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
 733                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
 734                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
 735                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
 736                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
 737                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
 738                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
 739                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
 740                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
 741                 >;
 742         };
 743
 744         pinctrl_mmc_cd: gpiommccdgrp {
 745                 fsl,pins = <
 746                          /* MMC1 CD */
 747                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
 748                 >;
 749         };
 750
 751         pinctrl_pwm1: pwm1grp {
 752                 fsl,pins = <
 753                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
 754                 >;
 755         };
 756
 757         pinctrl_pwm2: pwm2grp {
 758                 fsl,pins = <
 759                         MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
 760                 >;
 761         };
 762
 763         pinctrl_pwm3: pwm3grp {
 764                 fsl,pins = <
 765                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 766                 >;
 767         };
 768
 769         pinctrl_pwm4: pwm4grp {
 770                 fsl,pins = <
 771                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
 772                 >;
 773         };
 774
 775         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 776                 fsl,pins = <
 777                         /* USBH_EN */
 778                         MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
 779                 >;
 780         };
 781
 782         pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
 783                 fsl,pins = <
 784                         /* USBH_HUB_EN */
 785                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
 786                 >;
 787         };
 788
 789         pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
 790                 fsl,pins = <
 791                         /* USBO1 power en */
 792                         MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
 793                 >;
 794         };
 795
 796         pinctrl_reset_moci: gpioresetmocigrp {
 797                 fsl,pins = <
 798                         /* RESET_MOCI control */
 799                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
 800                 >;
 801         };
 802
 803         pinctrl_sd_cd: gpiosdcdgrp {
 804                 fsl,pins = <
 805                         /* SD1 CD */
 806                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
 807                 >;
 808         };
 809
 810         pinctrl_sgtl5000: sgtl5000grp {
 811                 fsl,pins = <
 812                         MX6QDL_PAD_GPIO_5__CCM_CLKO1    0x130b0
 813                 >;
 814         };
 815
 816         pinctrl_spdif: spdifgrp {
 817                 fsl,pins = <
 818                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 819                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 820                 >;
 821         };
 822
 823         pinctrl_touch_int: gpiotouchintgrp {
 824                 fsl,pins = <
 825                         /* STMPE811 interrupt */
 826                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 827                 >;
 828         };
 829
 830         pinctrl_uart1_dce: uart1dcegrp {
 831                 fsl,pins = <
 832                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 833                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 834                 >;
 835         };
 836
 837         /* DTE mode */
 838         pinctrl_uart1_dte: uart1dtegrp {
 839                 fsl,pins = <
 840                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 841                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 842                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 843                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 844                 >;
 845         };
 846
 847         /* Additional DTR, DSR, DCD */
 848         pinctrl_uart1_ctrl: uart1ctrlgrp {
 849                 fsl,pins = <
 850                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 851                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 852                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 853                 >;
 854         };
 855
 856         pinctrl_uart2_dce: uart2dcegrp {
 857                 fsl,pins = <
 858                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 859                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 860                 >;
 861         };
 862
 863         /* DTE mode */
 864         pinctrl_uart2_dte: uart2dtegrp {
 865                 fsl,pins = <
 866                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 867                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 868                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 869                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 870                 >;
 871         };
 872
 873         pinctrl_uart4_dce: uart4dcegrp {
 874                 fsl,pins = <
 875                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 876                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 877                 >;
 878         };
 879
 880         /* DTE mode */
 881         pinctrl_uart4_dte: uart4dtegrp {
 882                 fsl,pins = <
 883                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
 884                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
 885                 >;
 886         };
 887
 888         pinctrl_uart5_dce: uart5dcegrp {
 889                 fsl,pins = <
 890                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
 891                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
 892                 >;
 893         };
 894
 895         /* DTE mode */
 896         pinctrl_uart5_dte: uart5dtegrp {
 897                 fsl,pins = <
 898                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
 899                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
 900                 >;
 901         };
 902
 903         pinctrl_usbotg: usbotggrp {
 904                 fsl,pins = <
 905                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 906                 >;
 907         };
 908
 909         pinctrl_usdhc1_4bit: usdhc1grp_4bit {
 910                 fsl,pins = <
 911                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 912                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 913                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 914                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 915                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 916                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 917                 >;
 918         };
 919
 920         pinctrl_usdhc1_8bit: usdhc1grp_8bit {
 921                 fsl,pins = <
 922                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
 923                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
 924                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
 925                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
 926                 >;
 927         };
 928
 929         pinctrl_usdhc2: usdhc2grp {
 930                 fsl,pins = <
 931                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
 932                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
 933                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
 934                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
 935                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
 936                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
 937                 >;
 938         };
 939
 940         pinctrl_usdhc3: usdhc3grp {
 941                 fsl,pins = <
 942                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 943                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 944                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 945                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 946                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 947                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 948                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 949                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 950                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 951                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 952                         /* eMMC reset */
 953                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
 954                 >;
 955         };
 956 };