arch/arm/boot/dts/imx6q.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6q-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 ipu1 = &ipu2;
  12                 spi4 = &ecspi5;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 852000  1250000
  29                                 792000  1175000
  30                                 396000  975000
  31                         >;
  32                         fsl,soc-operating-points = <
  33                                 /* ARM kHz  SOC-PU uV */
  34                                 1200000 1275000
  35                                 996000  1250000
  36                                 852000  1250000
  37                                 792000  1175000
  38                                 396000  1175000
  39                         >;
  40                         clock-latency = <61036>; /* two CLK32 periods */
  41                         #cooling-cells = <2>;
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                         operating-points = <
  60                                 /* kHz    uV */
  61                                 1200000 1275000
  62                                 996000  1250000
  63                                 852000  1250000
  64                                 792000  1175000
  65                                 396000  975000
  66                         >;
  67                         fsl,soc-operating-points = <
  68                                 /* ARM kHz  SOC-PU uV */
  69                                 1200000 1275000
  70                                 996000  1250000
  71                                 852000  1250000
  72                                 792000  1175000
  73                                 396000  1175000
  74                         >;
  75                         clock-latency = <61036>; /* two CLK32 periods */
  76                         clocks = <&clks IMX6QDL_CLK_ARM>,
  77                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  78                                  <&clks IMX6QDL_CLK_STEP>,
  79                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  80                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  81                         clock-names = "arm", "pll2_pfd2_396m", "step",
  82                                       "pll1_sw", "pll1_sys";
  83                         arm-supply = <&reg_arm>;
  84                         pu-supply = <&reg_pu>;
  85                         soc-supply = <&reg_soc>;
  86                 };
  87
  88                 cpu2: cpu@2 {
  89                         compatible = "arm,cortex-a9";
  90                         device_type = "cpu";
  91                         reg = <2>;
  92                         next-level-cache = <&L2>;
  93                         operating-points = <
  94                                 /* kHz    uV */
  95                                 1200000 1275000
  96                                 996000  1250000
  97                                 852000  1250000
  98                                 792000  1175000
  99                                 396000  975000
 100                         >;
 101                         fsl,soc-operating-points = <
 102                                 /* ARM kHz  SOC-PU uV */
 103                                 1200000 1275000
 104                                 996000  1250000
 105                                 852000  1250000
 106                                 792000  1175000
 107                                 396000  1175000
 108                         >;
 109                         clock-latency = <61036>; /* two CLK32 periods */
 110                         clocks = <&clks IMX6QDL_CLK_ARM>,
 111                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 112                                  <&clks IMX6QDL_CLK_STEP>,
 113                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 114                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 115                         clock-names = "arm", "pll2_pfd2_396m", "step",
 116                                       "pll1_sw", "pll1_sys";
 117                         arm-supply = <&reg_arm>;
 118                         pu-supply = <&reg_pu>;
 119                         soc-supply = <&reg_soc>;
 120                 };
 121
 122                 cpu3: cpu@3 {
 123                         compatible = "arm,cortex-a9";
 124                         device_type = "cpu";
 125                         reg = <3>;
 126                         next-level-cache = <&L2>;
 127                         operating-points = <
 128                                 /* kHz    uV */
 129                                 1200000 1275000
 130                                 996000  1250000
 131                                 852000  1250000
 132                                 792000  1175000
 133                                 396000  975000
 134                         >;
 135                         fsl,soc-operating-points = <
 136                                 /* ARM kHz  SOC-PU uV */
 137                                 1200000 1275000
 138                                 996000  1250000
 139                                 852000  1250000
 140                                 792000  1175000
 141                                 396000  1175000
 142                         >;
 143                         clock-latency = <61036>; /* two CLK32 periods */
 144                         clocks = <&clks IMX6QDL_CLK_ARM>,
 145                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 146                                  <&clks IMX6QDL_CLK_STEP>,
 147                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 148                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 149                         clock-names = "arm", "pll2_pfd2_396m", "step",
 150                                       "pll1_sw", "pll1_sys";
 151                         arm-supply = <&reg_arm>;
 152                         pu-supply = <&reg_pu>;
 153                         soc-supply = <&reg_soc>;
 154                 };
 155         };
 156
 157         soc {
 158                 ocram: sram@900000 {
 159                         compatible = "mmio-sram";
 160                         reg = <0x00900000 0x40000>;
 161                         ranges = <0 0x00900000 0x40000>;
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 165                 };
 166
 167                 aips-bus@2000000 { /* AIPS1 */
 168                         spba-bus@2000000 {
 169                                 ecspi5: ecspi@2018000 {
 170                                         #address-cells = <1>;
 171                                         #size-cells = <0>;
 172                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 173                                         reg = <0x02018000 0x4000>;
 174                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 175                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 176                                                  <&clks IMX6Q_CLK_ECSPI5>;
 177                                         clock-names = "ipg", "per";
 178                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 179                                         dma-names = "rx", "tx";
 180                                         status = "disabled";
 181                                 };
 182                         };
 183
 184                         iomuxc: iomuxc@20e0000 {
 185                                 compatible = "fsl,imx6q-iomuxc";
 186                         };
 187                 };
 188
 189                 sata: sata@2200000 {
 190                         compatible = "fsl,imx6q-ahci";
 191                         reg = <0x02200000 0x4000>;
 192                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 193                         clocks = <&clks IMX6QDL_CLK_SATA>,
 194                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 195                                  <&clks IMX6QDL_CLK_AHB>;
 196                         clock-names = "sata", "sata_ref", "ahb";
 197                         status = "disabled";
 198                 };
 199
 200                 gpu_vg: gpu@2204000 {
 201                         compatible = "vivante,gc";
 202                         reg = <0x02204000 0x4000>;
 203                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 204                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 205                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 206                         clock-names = "bus", "core";
 207                         power-domains = <&pd_pu>;
 208                 };
 209
 210                 ipu2: ipu@2800000 {
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         compatible = "fsl,imx6q-ipu";
 214                         reg = <0x02800000 0x400000>;
 215                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 218                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 219                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 220                         clock-names = "bus", "di0", "di1";
 221                         resets = <&src 4>;
 222
 223                         ipu2_csi0: port@0 {
 224                                 reg = <0>;
 225
 226                                 ipu2_csi0_from_mipi_vc2: endpoint {
 227                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 228                                 };
 229                         };
 230
 231                         ipu2_csi1: port@1 {
 232                                 reg = <1>;
 233
 234                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 235                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 236                                 };
 237                         };
 238
 239                         ipu2_di0: port@2 {
 240                                 #address-cells = <1>;
 241                                 #size-cells = <0>;
 242                                 reg = <2>;
 243
 244                                 ipu2_di0_disp0: endpoint@0 {
 245                                         reg = <0>;
 246                                 };
 247
 248                                 ipu2_di0_hdmi: endpoint@1 {
 249                                         reg = <1>;
 250                                         remote-endpoint = <&hdmi_mux_2>;
 251                                 };
 252
 253                                 ipu2_di0_mipi: endpoint@2 {
 254                                         reg = <2>;
 255                                         remote-endpoint = <&mipi_mux_2>;
 256                                 };
 257
 258                                 ipu2_di0_lvds0: endpoint@3 {
 259                                         reg = <3>;
 260                                         remote-endpoint = <&lvds0_mux_2>;
 261                                 };
 262
 263                                 ipu2_di0_lvds1: endpoint@4 {
 264                                         reg = <4>;
 265                                         remote-endpoint = <&lvds1_mux_2>;
 266                                 };
 267                         };
 268
 269                         ipu2_di1: port@3 {
 270                                 #address-cells = <1>;
 271                                 #size-cells = <0>;
 272                                 reg = <3>;
 273
 274                                 ipu2_di1_hdmi: endpoint@1 {
 275                                         reg = <1>;
 276                                         remote-endpoint = <&hdmi_mux_3>;
 277                                 };
 278
 279                                 ipu2_di1_mipi: endpoint@2 {
 280                                         reg = <2>;
 281                                         remote-endpoint = <&mipi_mux_3>;
 282                                 };
 283
 284                                 ipu2_di1_lvds0: endpoint@3 {
 285                                         reg = <3>;
 286                                         remote-endpoint = <&lvds0_mux_3>;
 287                                 };
 288
 289                                 ipu2_di1_lvds1: endpoint@4 {
 290                                         reg = <4>;
 291                                         remote-endpoint = <&lvds1_mux_3>;
 292                                 };
 293                         };
 294                 };
 295         };
 296
 297         capture-subsystem {
 298                 compatible = "fsl,imx-capture-subsystem";
 299                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 300         };
 301
 302         display-subsystem {
 303                 compatible = "fsl,imx-display-subsystem";
 304                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 305         };
 306 };
 307
 308 &gpio1 {
 309         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 310                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 311                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 312                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 313                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 314                       <&iomuxc 22 116 10>;
 315 };
 316
 317 &gpio2 {
 318         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 319                       <&iomuxc 31  44  1>;
 320 };
 321
 322 &gpio3 {
 323         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 324 };
 325
 326 &gpio4 {
 327         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 328 };
 329
 330 &gpio5 {
 331         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 332                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 333 };
 334
 335 &gpio6 {
 336         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 337                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 338                       <&iomuxc 31  86 1>;
 339 };
 340
 341 &gpio7 {
 342         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 343 };
 344
 345 &gpr {
 346         ipu1_csi0_mux {
 347                 compatible = "video-mux";
 348                 mux-controls = <&mux 0>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351
 352                 port@0 {
 353                         reg = <0>;
 354
 355                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 356                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 357                         };
 358                 };
 359
 360                 port@1 {
 361                         reg = <1>;
 362
 363                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 364                         };
 365                 };
 366
 367                 port@2 {
 368                         reg = <2>;
 369
 370                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 371                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 372                         };
 373                 };
 374         };
 375
 376         ipu2_csi1_mux {
 377                 compatible = "video-mux";
 378                 mux-controls = <&mux 1>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381
 382                 port@0 {
 383                         reg = <0>;
 384
 385                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 386                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 387                         };
 388                 };
 389
 390                 port@1 {
 391                         reg = <1>;
 392
 393                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 394                         };
 395                 };
 396
 397                 port@2 {
 398                         reg = <2>;
 399
 400                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 401                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 402                         };
 403                 };
 404         };
 405 };
 406
 407 &hdmi {
 408         compatible = "fsl,imx6q-hdmi";
 409
 410         port@2 {
 411                 reg = <2>;
 412
 413                 hdmi_mux_2: endpoint {
 414                         remote-endpoint = <&ipu2_di0_hdmi>;
 415                 };
 416         };
 417
 418         port@3 {
 419                 reg = <3>;
 420
 421                 hdmi_mux_3: endpoint {
 422                         remote-endpoint = <&ipu2_di1_hdmi>;
 423                 };
 424         };
 425 };
 426
 427 &ipu1_csi1 {
 428         ipu1_csi1_from_mipi_vc1: endpoint {
 429                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 430         };
 431 };
 432
 433 &ldb {
 434         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 435                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 436                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 437                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 438         clock-names = "di0_pll", "di1_pll",
 439                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 440                       "di0", "di1";
 441
 442         lvds-channel@0 {
 443                 port@2 {
 444                         reg = <2>;
 445
 446                         lvds0_mux_2: endpoint {
 447                                 remote-endpoint = <&ipu2_di0_lvds0>;
 448                         };
 449                 };
 450
 451                 port@3 {
 452                         reg = <3>;
 453
 454                         lvds0_mux_3: endpoint {
 455                                 remote-endpoint = <&ipu2_di1_lvds0>;
 456                         };
 457                 };
 458         };
 459
 460         lvds-channel@1 {
 461                 port@2 {
 462                         reg = <2>;
 463
 464                         lvds1_mux_2: endpoint {
 465                                 remote-endpoint = <&ipu2_di0_lvds1>;
 466                         };
 467                 };
 468
 469                 port@3 {
 470                         reg = <3>;
 471
 472                         lvds1_mux_3: endpoint {
 473                                 remote-endpoint = <&ipu2_di1_lvds1>;
 474                         };
 475                 };
 476         };
 477 };
 478
 479 &mipi_csi {
 480         port@1 {
 481                 reg = <1>;
 482
 483                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 484                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 485                 };
 486         };
 487
 488         port@2 {
 489                 reg = <2>;
 490
 491                 mipi_vc1_to_ipu1_csi1: endpoint {
 492                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 493                 };
 494         };
 495
 496         port@3 {
 497                 reg = <3>;
 498
 499                 mipi_vc2_to_ipu2_csi0: endpoint {
 500                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 501                 };
 502         };
 503
 504         port@4 {
 505                 reg = <4>;
 506
 507                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 508                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 509                 };
 510         };
 511 };
 512
 513 &mipi_dsi {
 514         ports {
 515                 port@2 {
 516                         reg = <2>;
 517
 518                         mipi_mux_2: endpoint {
 519                                 remote-endpoint = <&ipu2_di0_mipi>;
 520                         };
 521                 };
 522
 523                 port@3 {
 524                         reg = <3>;
 525
 526                         mipi_mux_3: endpoint {
 527                                 remote-endpoint = <&ipu2_di1_mipi>;
 528                         };
 529                 };
 530         };
 531 };
 532
 533 &mux {
 534         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 535                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 536                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 537                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 538                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 539                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 540                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 541 };
 542
 543 &vpu {
 544         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 545 };