arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6q-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 ipu1 = &ipu2;
  18                 spi4 = &ecspi5;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         reg = <0>;
  29                         next-level-cache = <&L2>;
  30                         operating-points = <
  31                                 /* kHz    uV */
  32                                 1200000 1275000
  33                                 996000  1250000
  34                                 852000  1250000
  35                                 792000  1175000
  36                                 396000  975000
  37                         >;
  38                         fsl,soc-operating-points = <
  39                                 /* ARM kHz  SOC-PU uV */
  40                                 1200000 1275000
  41                                 996000  1250000
  42                                 852000  1250000
  43                                 792000  1175000
  44                                 396000  1175000
  45                         >;
  46                         clock-latency = <61036>; /* two CLK32 periods */
  47                         clocks = <&clks IMX6QDL_CLK_ARM>,
  48                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  49                                  <&clks IMX6QDL_CLK_STEP>,
  50                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  51                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  52                         clock-names = "arm", "pll2_pfd2_396m", "step",
  53                                       "pll1_sw", "pll1_sys";
  54                         arm-supply = <&reg_arm>;
  55                         pu-supply = <&reg_pu>;
  56                         soc-supply = <&reg_soc>;
  57                 };
  58
  59                 cpu@1 {
  60                         compatible = "arm,cortex-a9";
  61                         device_type = "cpu";
  62                         reg = <1>;
  63                         next-level-cache = <&L2>;
  64                 };
  65
  66                 cpu@2 {
  67                         compatible = "arm,cortex-a9";
  68                         device_type = "cpu";
  69                         reg = <2>;
  70                         next-level-cache = <&L2>;
  71                 };
  72
  73                 cpu@3 {
  74                         compatible = "arm,cortex-a9";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                 };
  79         };
  80
  81         soc {
  82                 ocram: sram@00900000 {
  83                         compatible = "mmio-sram";
  84                         reg = <0x00900000 0x40000>;
  85                         ranges = <0 0x00900000 0x40000>;
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  89                 };
  90
  91                 aips-bus@02000000 { /* AIPS1 */
  92                         spba-bus@02000000 {
  93                                 ecspi5: ecspi@02018000 {
  94                                         #address-cells = <1>;
  95                                         #size-cells = <0>;
  96                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  97                                         reg = <0x02018000 0x4000>;
  98                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  99                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 100                                                  <&clks IMX6Q_CLK_ECSPI5>;
 101                                         clock-names = "ipg", "per";
 102                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 103                                         dma-names = "rx", "tx";
 104                                         status = "disabled";
 105                                 };
 106                         };
 107
 108                         iomuxc: iomuxc@020e0000 {
 109                                 compatible = "fsl,imx6q-iomuxc";
 110                         };
 111                 };
 112
 113                 sata: sata@02200000 {
 114                         compatible = "fsl,imx6q-ahci";
 115                         reg = <0x02200000 0x4000>;
 116                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&clks IMX6QDL_CLK_SATA>,
 118                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 119                                  <&clks IMX6QDL_CLK_AHB>;
 120                         clock-names = "sata", "sata_ref", "ahb";
 121                         status = "disabled";
 122                 };
 123
 124                 gpu_vg: gpu@02204000 {
 125                         compatible = "vivante,gc";
 126                         reg = <0x02204000 0x4000>;
 127                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 128                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 129                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 130                         clock-names = "bus", "core";
 131                         power-domains = <&pd_pu>;
 132                 };
 133
 134                 ipu2: ipu@02800000 {
 135                         #address-cells = <1>;
 136                         #size-cells = <0>;
 137                         compatible = "fsl,imx6q-ipu";
 138                         reg = <0x02800000 0x400000>;
 139                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 141                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 142                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 143                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 144                         clock-names = "bus", "di0", "di1";
 145                         resets = <&src 4>;
 146
 147                         ipu2_csi0: port@0 {
 148                                 reg = <0>;
 149
 150                                 ipu2_csi0_from_mipi_vc2: endpoint {
 151                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 152                                 };
 153                         };
 154
 155                         ipu2_csi1: port@1 {
 156                                 reg = <1>;
 157
 158                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 159                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 160                                 };
 161                         };
 162
 163                         ipu2_di0: port@2 {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                                 reg = <2>;
 167
 168                                 ipu2_di0_disp0: disp0-endpoint {
 169                                 };
 170
 171                                 ipu2_di0_hdmi: hdmi-endpoint {
 172                                         remote-endpoint = <&hdmi_mux_2>;
 173                                 };
 174
 175                                 ipu2_di0_mipi: mipi-endpoint {
 176                                         remote-endpoint = <&mipi_mux_2>;
 177                                 };
 178
 179                                 ipu2_di0_lvds0: lvds0-endpoint {
 180                                         remote-endpoint = <&lvds0_mux_2>;
 181                                 };
 182
 183                                 ipu2_di0_lvds1: lvds1-endpoint {
 184                                         remote-endpoint = <&lvds1_mux_2>;
 185                                 };
 186                         };
 187
 188                         ipu2_di1: port@3 {
 189                                 #address-cells = <1>;
 190                                 #size-cells = <0>;
 191                                 reg = <3>;
 192
 193                                 ipu2_di1_hdmi: hdmi-endpoint {
 194                                         remote-endpoint = <&hdmi_mux_3>;
 195                                 };
 196
 197                                 ipu2_di1_mipi: mipi-endpoint {
 198                                         remote-endpoint = <&mipi_mux_3>;
 199                                 };
 200
 201                                 ipu2_di1_lvds0: lvds0-endpoint {
 202                                         remote-endpoint = <&lvds0_mux_3>;
 203                                 };
 204
 205                                 ipu2_di1_lvds1: lvds1-endpoint {
 206                                         remote-endpoint = <&lvds1_mux_3>;
 207                                 };
 208                         };
 209                 };
 210         };
 211
 212         capture-subsystem {
 213                 compatible = "fsl,imx-capture-subsystem";
 214                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 215         };
 216
 217         display-subsystem {
 218                 compatible = "fsl,imx-display-subsystem";
 219                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 220         };
 221
 222         gpu-subsystem {
 223                 compatible = "fsl,imx-gpu-subsystem";
 224                 cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
 225         };
 226 };
 227
 228 &gpio1 {
 229         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 230                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 231                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 232                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 233                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 234                       <&iomuxc 22 116 10>;
 235 };
 236
 237 &gpio2 {
 238         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 239                       <&iomuxc 31  44  1>;
 240 };
 241
 242 &gpio3 {
 243         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 244 };
 245
 246 &gpio4 {
 247         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 248 };
 249
 250 &gpio5 {
 251         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 252                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 253 };
 254
 255 &gpio6 {
 256         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 257                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 258                       <&iomuxc 31  86 1>;
 259 };
 260
 261 &gpio7 {
 262         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 263 };
 264
 265 &gpr {
 266         ipu1_csi0_mux {
 267                 compatible = "video-mux";
 268                 mux-controls = <&mux 0>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271
 272                 port@0 {
 273                         reg = <0>;
 274
 275                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 276                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 277                         };
 278                 };
 279
 280                 port@1 {
 281                         reg = <1>;
 282
 283                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 284                         };
 285                 };
 286
 287                 port@2 {
 288                         reg = <2>;
 289
 290                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 291                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 292                         };
 293                 };
 294         };
 295
 296         ipu2_csi1_mux {
 297                 compatible = "video-mux";
 298                 mux-controls = <&mux 1>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301
 302                 port@0 {
 303                         reg = <0>;
 304
 305                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 306                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 307                         };
 308                 };
 309
 310                 port@1 {
 311                         reg = <1>;
 312
 313                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 314                         };
 315                 };
 316
 317                 port@2 {
 318                         reg = <2>;
 319
 320                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 321                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 322                         };
 323                 };
 324         };
 325 };
 326
 327 &hdmi {
 328         compatible = "fsl,imx6q-hdmi";
 329
 330         port@2 {
 331                 reg = <2>;
 332
 333                 hdmi_mux_2: endpoint {
 334                         remote-endpoint = <&ipu2_di0_hdmi>;
 335                 };
 336         };
 337
 338         port@3 {
 339                 reg = <3>;
 340
 341                 hdmi_mux_3: endpoint {
 342                         remote-endpoint = <&ipu2_di1_hdmi>;
 343                 };
 344         };
 345 };
 346
 347 &ipu1_csi1 {
 348         ipu1_csi1_from_mipi_vc1: endpoint {
 349                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 350         };
 351 };
 352
 353 &ldb {
 354         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 355                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 356                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 357                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 358         clock-names = "di0_pll", "di1_pll",
 359                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 360                       "di0", "di1";
 361
 362         lvds-channel@0 {
 363                 port@2 {
 364                         reg = <2>;
 365
 366                         lvds0_mux_2: endpoint {
 367                                 remote-endpoint = <&ipu2_di0_lvds0>;
 368                         };
 369                 };
 370
 371                 port@3 {
 372                         reg = <3>;
 373
 374                         lvds0_mux_3: endpoint {
 375                                 remote-endpoint = <&ipu2_di1_lvds0>;
 376                         };
 377                 };
 378         };
 379
 380         lvds-channel@1 {
 381                 port@2 {
 382                         reg = <2>;
 383
 384                         lvds1_mux_2: endpoint {
 385                                 remote-endpoint = <&ipu2_di0_lvds1>;
 386                         };
 387                 };
 388
 389                 port@3 {
 390                         reg = <3>;
 391
 392                         lvds1_mux_3: endpoint {
 393                                 remote-endpoint = <&ipu2_di1_lvds1>;
 394                         };
 395                 };
 396         };
 397 };
 398
 399 &mipi_csi {
 400         port@1 {
 401                 reg = <1>;
 402
 403                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 404                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 405                 };
 406         };
 407
 408         port@2 {
 409                 reg = <2>;
 410
 411                 mipi_vc1_to_ipu1_csi1: endpoint {
 412                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 413                 };
 414         };
 415
 416         port@3 {
 417                 reg = <3>;
 418
 419                 mipi_vc2_to_ipu2_csi0: endpoint {
 420                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 421                 };
 422         };
 423
 424         port@4 {
 425                 reg = <4>;
 426
 427                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 428                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 429                 };
 430         };
 431 };
 432
 433 &mipi_dsi {
 434         ports {
 435                 port@2 {
 436                         reg = <2>;
 437
 438                         mipi_mux_2: endpoint {
 439                                 remote-endpoint = <&ipu2_di0_mipi>;
 440                         };
 441                 };
 442
 443                 port@3 {
 444                         reg = <3>;
 445
 446                         mipi_mux_3: endpoint {
 447                                 remote-endpoint = <&ipu2_di1_mipi>;
 448                         };
 449                 };
 450         };
 451 };
 452
 453 &mux {
 454         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 455                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 456                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 457                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 458                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 459                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 460                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 461 };
 462
 463 &vpu {
 464         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 465 };