arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6q-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 ipu1 = &ipu2;
  18                 spi4 = &ecspi5;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         reg = <0>;
  29                         next-level-cache = <&L2>;
  30                         operating-points = <
  31                                 /* kHz    uV */
  32                                 1200000 1275000
  33                                 996000  1250000
  34                                 852000  1250000
  35                                 792000  1175000
  36                                 396000  975000
  37                         >;
  38                         fsl,soc-operating-points = <
  39                                 /* ARM kHz  SOC-PU uV */
  40                                 1200000 1275000
  41                                 996000  1250000
  42                                 852000  1250000
  43                                 792000  1175000
  44                                 396000  1175000
  45                         >;
  46                         clock-latency = <61036>; /* two CLK32 periods */
  47                         clocks = <&clks IMX6QDL_CLK_ARM>,
  48                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  49                                  <&clks IMX6QDL_CLK_STEP>,
  50                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  51                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  52                         clock-names = "arm", "pll2_pfd2_396m", "step",
  53                                       "pll1_sw", "pll1_sys";
  54                         arm-supply = <&reg_arm>;
  55                         pu-supply = <&reg_pu>;
  56                         soc-supply = <&reg_soc>;
  57                 };
  58
  59                 cpu@1 {
  60                         compatible = "arm,cortex-a9";
  61                         device_type = "cpu";
  62                         reg = <1>;
  63                         next-level-cache = <&L2>;
  64                 };
  65
  66                 cpu@2 {
  67                         compatible = "arm,cortex-a9";
  68                         device_type = "cpu";
  69                         reg = <2>;
  70                         next-level-cache = <&L2>;
  71                 };
  72
  73                 cpu@3 {
  74                         compatible = "arm,cortex-a9";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                 };
  79         };
  80
  81         soc {
  82                 ocram: sram@00900000 {
  83                         compatible = "mmio-sram";
  84                         reg = <0x00900000 0x40000>;
  85                         ranges = <0 0x00900000 0x40000>;
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  89                 };
  90
  91                 aips-bus@02000000 { /* AIPS1 */
  92                         spba-bus@02000000 {
  93                                 ecspi5: ecspi@02018000 {
  94                                         #address-cells = <1>;
  95                                         #size-cells = <0>;
  96                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  97                                         reg = <0x02018000 0x4000>;
  98                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  99                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 100                                                  <&clks IMX6Q_CLK_ECSPI5>;
 101                                         clock-names = "ipg", "per";
 102                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 103                                         dma-names = "rx", "tx";
 104                                         status = "disabled";
 105                                 };
 106                         };
 107
 108                         iomuxc: iomuxc@020e0000 {
 109                                 compatible = "fsl,imx6q-iomuxc";
 110                         };
 111                 };
 112
 113                 sata: sata@02200000 {
 114                         compatible = "fsl,imx6q-ahci";
 115                         reg = <0x02200000 0x4000>;
 116                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&clks IMX6QDL_CLK_SATA>,
 118                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 119                                  <&clks IMX6QDL_CLK_AHB>;
 120                         clock-names = "sata", "sata_ref", "ahb";
 121                         status = "disabled";
 122                 };
 123
 124                 gpu_vg: gpu@02204000 {
 125                         compatible = "vivante,gc";
 126                         reg = <0x02204000 0x4000>;
 127                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 128                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 129                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 130                         clock-names = "bus", "core";
 131                         power-domains = <&gpc 1>;
 132                 };
 133
 134                 ipu2: ipu@02800000 {
 135                         #address-cells = <1>;
 136                         #size-cells = <0>;
 137                         compatible = "fsl,imx6q-ipu";
 138                         reg = <0x02800000 0x400000>;
 139                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 141                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 142                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 143                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 144                         clock-names = "bus", "di0", "di1";
 145                         resets = <&src 4>;
 146
 147                         ipu2_csi0: port@0 {
 148                                 reg = <0>;
 149                         };
 150
 151                         ipu2_csi1: port@1 {
 152                                 reg = <1>;
 153                         };
 154
 155                         ipu2_di0: port@2 {
 156                                 #address-cells = <1>;
 157                                 #size-cells = <0>;
 158                                 reg = <2>;
 159
 160                                 ipu2_di0_disp0: disp0-endpoint {
 161                                 };
 162
 163                                 ipu2_di0_hdmi: hdmi-endpoint {
 164                                         remote-endpoint = <&hdmi_mux_2>;
 165                                 };
 166
 167                                 ipu2_di0_mipi: mipi-endpoint {
 168                                         remote-endpoint = <&mipi_mux_2>;
 169                                 };
 170
 171                                 ipu2_di0_lvds0: lvds0-endpoint {
 172                                         remote-endpoint = <&lvds0_mux_2>;
 173                                 };
 174
 175                                 ipu2_di0_lvds1: lvds1-endpoint {
 176                                         remote-endpoint = <&lvds1_mux_2>;
 177                                 };
 178                         };
 179
 180                         ipu2_di1: port@3 {
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183                                 reg = <3>;
 184
 185                                 ipu2_di1_hdmi: hdmi-endpoint {
 186                                         remote-endpoint = <&hdmi_mux_3>;
 187                                 };
 188
 189                                 ipu2_di1_mipi: mipi-endpoint {
 190                                         remote-endpoint = <&mipi_mux_3>;
 191                                 };
 192
 193                                 ipu2_di1_lvds0: lvds0-endpoint {
 194                                         remote-endpoint = <&lvds0_mux_3>;
 195                                 };
 196
 197                                 ipu2_di1_lvds1: lvds1-endpoint {
 198                                         remote-endpoint = <&lvds1_mux_3>;
 199                                 };
 200                         };
 201                 };
 202         };
 203
 204         display-subsystem {
 205                 compatible = "fsl,imx-display-subsystem";
 206                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 207         };
 208
 209         gpu-subsystem {
 210                 compatible = "fsl,imx-gpu-subsystem";
 211                 cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
 212         };
 213 };
 214
 215 &gpio1 {
 216         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 217                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 218                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 219                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 220                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 221                       <&iomuxc 22 116 10>;
 222 };
 223
 224 &gpio2 {
 225         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 226                       <&iomuxc 31  44  1>;
 227 };
 228
 229 &gpio3 {
 230         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 231 };
 232
 233 &gpio4 {
 234         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 235 };
 236
 237 &gpio5 {
 238         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 239                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 240 };
 241
 242 &gpio6 {
 243         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 244                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 245                       <&iomuxc 31  86 1>;
 246 };
 247
 248 &gpio7 {
 249         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 250 };
 251
 252 &hdmi {
 253         compatible = "fsl,imx6q-hdmi";
 254
 255         port@2 {
 256                 reg = <2>;
 257
 258                 hdmi_mux_2: endpoint {
 259                         remote-endpoint = <&ipu2_di0_hdmi>;
 260                 };
 261         };
 262
 263         port@3 {
 264                 reg = <3>;
 265
 266                 hdmi_mux_3: endpoint {
 267                         remote-endpoint = <&ipu2_di1_hdmi>;
 268                 };
 269         };
 270 };
 271
 272 &ldb {
 273         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 274                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 275                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 276                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 277         clock-names = "di0_pll", "di1_pll",
 278                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 279                       "di0", "di1";
 280
 281         lvds-channel@0 {
 282                 port@2 {
 283                         reg = <2>;
 284
 285                         lvds0_mux_2: endpoint {
 286                                 remote-endpoint = <&ipu2_di0_lvds0>;
 287                         };
 288                 };
 289
 290                 port@3 {
 291                         reg = <3>;
 292
 293                         lvds0_mux_3: endpoint {
 294                                 remote-endpoint = <&ipu2_di1_lvds0>;
 295                         };
 296                 };
 297         };
 298
 299         lvds-channel@1 {
 300                 port@2 {
 301                         reg = <2>;
 302
 303                         lvds1_mux_2: endpoint {
 304                                 remote-endpoint = <&ipu2_di0_lvds1>;
 305                         };
 306                 };
 307
 308                 port@3 {
 309                         reg = <3>;
 310
 311                         lvds1_mux_3: endpoint {
 312                                 remote-endpoint = <&ipu2_di1_lvds1>;
 313                         };
 314                 };
 315         };
 316 };
 317
 318 &mipi_dsi {
 319         ports {
 320                 port@2 {
 321                         reg = <2>;
 322
 323                         mipi_mux_2: endpoint {
 324                                 remote-endpoint = <&ipu2_di0_mipi>;
 325                         };
 326                 };
 327
 328                 port@3 {
 329                         reg = <3>;
 330
 331                         mipi_mux_3: endpoint {
 332                                 remote-endpoint = <&ipu2_di1_mipi>;
 333                         };
 334                 };
 335         };
 336 };
 337
 338 &vpu {
 339         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 340 };