arch/arm/boot/dts/imx6q-pistachio.dts

   1 /*
   2  * Copyright (C) 2017 NutsBoard.Org
   3  *
   4  * Author: Wig Cheng <onlywig@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46
  47 #include <dt-bindings/gpio/gpio.h>
  48 #include <dt-bindings/input/input.h>
  49 #include "imx6q.dtsi"
  50
  51 / {
  52         model = "NutsBoard i.MX6 Quad Pistachio board";
  53         compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q";
  54
  55         chosen {
  56                 stdout-path = &uart4;
  57         };
  58
  59         memory@10000000 {
  60                 reg = <0x10000000 0x80000000>;
  61         };
  62
  63         reg_3p3v: regulator-3p3v {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "3P3V";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68         };
  69
  70         reg_1p8v: regulator-1p8v {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "1P8V";
  73                 regulator-min-microvolt = <1800000>;
  74                 regulator-max-microvolt = <1800000>;
  75         };
  76
  77         wlan_en_reg: regulator-wlan_en {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "wlan-en-regulator";
  80                 regulator-min-microvolt = <1800000>;
  81                 regulator-max-microvolt = <1800000>;
  82                 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  83                 startup-delay-us = <70000>;
  84                 enable-active-high;
  85         };
  86
  87         reg_usb_otg_vbus: regulator-usb_vbus {
  88                 compatible = "regulator-fixed";
  89                 regulator-name = "usb_otg_vbus";
  90                 regulator-min-microvolt = <5000000>;
  91                 regulator-max-microvolt = <5000000>;
  92                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  93                 enable-active-high;
  94                 vin-supply = <&swbst_reg>;
  95         };
  96
  97         gpio-keys {
  98                 compatible = "gpio-keys";
  99                 pinctrl-names = "default";
 100                 pinctrl-0 = <&pinctrl_gpio_keys>;
 101
 102                 power {
 103                         label = "Power Button";
 104                         gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 105                         gpio-key,wakeup;
 106                         linux,code = <KEY_POWER>;
 107                 };
 108         };
 109
 110         sound {
 111                 compatible = "fsl,imx-sgtl5000",
 112                            "fsl,imx-audio-sgtl5000";
 113                 model = "audio-sgtl5000";
 114                 ssi-controller = <&ssi1>;
 115                 audio-codec = <&codec>;
 116                 audio-routing =
 117                         "MIC_IN", "Mic Jack",
 118                         "Mic Jack", "Mic Bias",
 119                         "Headphone Jack", "HP_OUT";
 120                 mux-int-port = <1>;
 121                 mux-ext-port = <3>;
 122         };
 123
 124         backlight_lvds: backlight-lvds {
 125                 compatible = "pwm-backlight";
 126                 pwms = <&pwm1 0 50000>;
 127                 brightness-levels = <
 128                         0  /*1  2  3  4  5  6*/  7  8  9
 129                         10 11 12 13 14 15 16 17 18 19
 130                         20 21 22 23 24 25 26 27 28 29
 131                         30 31 32 33 34 35 36 37 38 39
 132                         40 41 42 43 44 45 46 47 48 49
 133                         50 51 52 53 54 55 56 57 58 59
 134                         60 61 62 63 64 65 66 67 68 69
 135                         70 71 72 73 74 75 76 77 78 79
 136                         80 81 82 83 84 85 86 87 88 89
 137                         90 91 92 93 94 95 96 97 98 99
 138                         100
 139                 >;
 140                 default-brightness-level = <94>;
 141                 status = "okay";
 142         };
 143
 144         panel {
 145                 compatible = "hannstar,hsd100pxn1";
 146                 backlight = <&backlight_lvds>;
 147
 148                 port {
 149                         panel_in: endpoint {
 150                                 remote-endpoint = <&lvds0_out>;
 151                         };
 152                 };
 153         };
 154 };
 155
 156 &audmux {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_audmux>;
 159         status = "okay";
 160 };
 161
 162 &can2 {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_flexcan2>;
 165         status = "okay";
 166 };
 167
 168 &clks {
 169         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 170                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 171         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 172                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 173 };
 174
 175 &fec {
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&pinctrl_enet>;
 178         phy-mode = "rgmii";
 179         status = "okay";
 180 };
 181
 182 &hdmi {
 183         ddc-i2c-bus = <&i2c2>;
 184         status = "okay";
 185 };
 186
 187 &i2c1 {
 188         clock-frequency = <100000>;
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_i2c1>;
 191         status = "okay";
 192
 193         codec: sgtl5000@a {
 194                 compatible = "fsl,sgtl5000";
 195                 pinctrl-names = "default";
 196                 pinctrl-0 = <&pinctrl_i2c1_sgtl5000>;
 197                 reg = <0x0a>;
 198                 clocks = <&clks IMX6QDL_CLK_CKO>;
 199                 VDDA-supply = <&reg_1p8v>;
 200                 VDDIO-supply = <&reg_1p8v>;
 201         };
 202 };
 203
 204 &i2c2 {
 205         clock-frequency = <100000>;
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_i2c2>;
 208         status = "okay";
 209
 210         pmic: pfuze100@8 {
 211                 compatible = "fsl,pfuze100";
 212                 reg = <0x08>;
 213
 214                 regulators {
 215                         sw1a_reg: sw1ab {
 216                                 regulator-min-microvolt = <300000>;
 217                                 regulator-max-microvolt = <1875000>;
 218                                 regulator-boot-on;
 219                                 regulator-always-on;
 220                                 regulator-ramp-delay = <6250>;
 221                         };
 222
 223                         sw1c_reg: sw1c {
 224                                 regulator-min-microvolt = <300000>;
 225                                 regulator-max-microvolt = <1875000>;
 226                                 regulator-boot-on;
 227                                 regulator-always-on;
 228                                 regulator-ramp-delay = <6250>;
 229                         };
 230
 231                         sw2_reg: sw2 {
 232                                 regulator-min-microvolt = <800000>;
 233                                 regulator-max-microvolt = <3300000>;
 234                                 regulator-boot-on;
 235                                 regulator-always-on;
 236                                 regulator-ramp-delay = <6250>;
 237                         };
 238
 239                         sw3a_reg: sw3a {
 240                                 regulator-min-microvolt = <400000>;
 241                                 regulator-max-microvolt = <1975000>;
 242                                 regulator-boot-on;
 243                                 regulator-always-on;
 244                         };
 245
 246                         sw3b_reg: sw3b {
 247                                 regulator-min-microvolt = <400000>;
 248                                 regulator-max-microvolt = <1975000>;
 249                                 regulator-boot-on;
 250                                 regulator-always-on;
 251                         };
 252
 253                         sw4_reg: sw4 {
 254                                 regulator-min-microvolt = <800000>;
 255                                 regulator-max-microvolt = <3300000>;
 256                         };
 257
 258                         swbst_reg: swbst {
 259                                 regulator-min-microvolt = <5000000>;
 260                                 regulator-max-microvolt = <5150000>;
 261                         };
 262
 263                         snvs_reg: vsnvs {
 264                                 regulator-min-microvolt = <1000000>;
 265                                 regulator-max-microvolt = <3000000>;
 266                                 regulator-boot-on;
 267                                 regulator-always-on;
 268                         };
 269
 270                         vref_reg: vrefddr {
 271                                 regulator-boot-on;
 272                                 regulator-always-on;
 273                         };
 274
 275                         vgen1_reg: vgen1 {
 276                                 regulator-min-microvolt = <800000>;
 277                                 regulator-max-microvolt = <1550000>;
 278                         };
 279
 280                         vgen2_reg: vgen2 {
 281                                 regulator-min-microvolt = <800000>;
 282                                 regulator-max-microvolt = <1550000>;
 283                         };
 284
 285                         vgen3_reg: vgen3 {
 286                                 regulator-min-microvolt = <1800000>;
 287                                 regulator-max-microvolt = <3300000>;
 288                         };
 289
 290                         vgen4_reg: vgen4 {
 291                                 regulator-min-microvolt = <1800000>;
 292                                 regulator-max-microvolt = <3300000>;
 293                                 regulator-always-on;
 294                         };
 295
 296                         vgen5_reg: vgen5 {
 297                                 regulator-min-microvolt = <1800000>;
 298                                 regulator-max-microvolt = <3300000>;
 299                                 regulator-always-on;
 300                         };
 301                         vgen6_reg: vgen6 {
 302                                 regulator-min-microvolt = <1800000>;
 303                                 regulator-max-microvolt = <3300000>;
 304                                 regulator-always-on;
 305                         };
 306                 };
 307         };
 308
 309         ar1021@4d {
 310                 compatible = "microchip,ar1021-i2c";
 311                 reg = <0x4d>;
 312                 interrupt-parent = <&gpio6>;
 313                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 314         };
 315 };
 316
 317 &i2c3 {
 318         clock-frequency = <100000>;
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_i2c3>;
 321         status = "okay";
 322 };
 323
 324 &iomuxc {
 325         pinctrl-names = "default";
 326
 327         pinctrl_hog: hoggrp {
 328                 fsl,pins = <
 329                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0  /*pcie power*/
 330                         MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x1b0b0   /*LCD power*/
 331                         MX6QDL_PAD_EIM_D16__GPIO3_IO16  0x1b0b0   /*backlight power*/
 332                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1 /*SD3 CD pin*/
 333                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/
 334                         MX6QDL_PAD_EIM_A16__GPIO2_IO22  0x1b0b0 /*touch reset*/
 335                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b01 /*touch irq*/
 336                         MX6QDL_PAD_GPIO_7__GPIO1_IO07    0x1b0b0/*backlight pwr*/
 337                         MX6QDL_PAD_GPIO_16__GPIO7_IO11  0x1b0b0 /*gpio 5V_1*/
 338                         MX6QDL_PAD_EIM_A19__GPIO2_IO19  0x1b0b0 /*gpio 5V_2*/
 339                         MX6QDL_PAD_EIM_A24__GPIO5_IO04  0x1b0b0 /*gpio 5V_3*/
 340                         MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0 /*gpio 5V_4*/
 341                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0 /*AUX_5V_EN*/
 342                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x1b0b0 /*AUX_5VB_EN*/
 343                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x1b0b0 /*AUX_3V3_EN*/
 344                         MX6QDL_PAD_EIM_D21__GPIO3_IO21  0x1b0b0 /*I2C expander pwr*/
 345                 >;
 346         };
 347
 348         pinctrl_audmux: audmuxgrp {
 349                 fsl,pins = <
 350                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 351                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 352                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 353                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 354                 >;
 355         };
 356
 357         pinctrl_ecspi1: ecspi1grp {
 358                 fsl,pins = <
 359                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 360                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 361                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 362                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 363                 >;
 364         };
 365
 366         pinctrl_enet: enetgrp {
 367                 fsl,pins = <
 368                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
 369                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 370                         /* AR8035 reset */
 371                         MX6QDL_PAD_EIM_A20__GPIO2_IO18          0x130b0
 372                         /* AR8035 interrupt */
 373                         MX6QDL_PAD_EIM_CS0__GPIO2_IO23          0x1b0b1
 374                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 375                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 376                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 377                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 378                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 379                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 380                         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 381                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x0a0b1
 382                         /* AR8035 pin strapping: IO voltage: pull up */
 383                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 384                         /* AR8035 pin strapping: PHYADDR#0: pull down */
 385                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030
 386                         /* AR8035 pin strapping: PHYADDR#1: pull down */
 387                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
 388                         /* AR8035 pin strapping: MODE#1: pull up */
 389                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 390                         /* AR8035 pin strapping: MODE#3: pull up */
 391                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 392                         /* AR8035 pin strapping: MODE#0: pull down */
 393                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
 394                 >;
 395         };
 396
 397         pinctrl_flexcan2: flexcan2grp {
 398                 fsl,pins = <
 399                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 400                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 401                 >;
 402         };
 403
 404         pinctrl_gpio_keys: gpio_keysgrp {
 405                 fsl,pins = <
 406                         MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
 407                 >;
 408         };
 409
 410         pinctrl_hdmi_cec: hdmicecgrp {
 411                 fsl,pins = <
 412                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
 413                 >;
 414         };
 415
 416         pinctrl_i2c1: i2c1grp {
 417                 fsl,pins = <
 418                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 419                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 420                 >;
 421         };
 422
 423         pinctrl_i2c2: i2c2grp {
 424                 fsl,pins = <
 425                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 426                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 427                 >;
 428         };
 429
 430         pinctrl_i2c3: i2c3grp {
 431                 fsl,pins = <
 432                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 433                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 434                 >;
 435         };
 436
 437         pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp {
 438                 fsl,pins = <
 439                         MX6QDL_PAD_GPIO_0__CCM_CLKO1                    0x000b0 /* sys_mclk */
 440                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x130b0 /*headphone det*/
 441                         MX6QDL_PAD_GPIO_8__GPIO1_IO08                   0x130b0 /*microphone det*/
 442                 >;
 443         };
 444
 445         pinctrl_pwm1: pwm1grp {
 446                 fsl,pins = <
 447                         MX6QDL_PAD_GPIO_9__PWM1_OUT         0x1b0b1
 448                 >;
 449         };
 450
 451         pinctrl_uart1: uart1grp {
 452                 fsl,pins = <
 453                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA    0x1b0b1
 454                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA    0x1b0b1
 455                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 456                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 457                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 458                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 459                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 460                 >;
 461         };
 462
 463         pinctrl_uart2: uart2grp {
 464                 fsl,pins = <
 465                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 466                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 467                         MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
 468                         MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
 469                 >;
 470         };
 471
 472         pinctrl_uart3: uart3grp {
 473                 fsl,pins = <
 474                         MX6QDL_PAD_SD4_CLK__UART3_RX_DATA       0x1b0b1
 475                         MX6QDL_PAD_SD4_CMD__UART3_TX_DATA       0x1b0b1
 476                         MX6QDL_PAD_EIM_D30__UART3_CTS_B         0x1b0b1
 477                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 478                 >;
 479         };
 480
 481         pinctrl_uart4: uart4grp {
 482                 fsl,pins = <
 483                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 484                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 485                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 486                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 487                 >;
 488         };
 489
 490         pinctrl_uart5: uart5grp {
 491                 fsl,pins = <
 492                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x1b0b1
 493                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x1b0b1
 494                         MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B      0x1b0b1
 495                         MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B      0x1b0b1
 496                         MX6QDL_PAD_EIM_A21__GPIO2_IO17           0x15059 /*BT_EN*/
 497                 >;
 498         };
 499
 500         pinctrl_usbotg: usbotggrp {
 501                 fsl,pins = <
 502                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 503                 >;
 504         };
 505
 506         pinctrl_usdhc1: usdhc1grp {
 507                 fsl,pins = <
 508                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x17059
 509                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x10059
 510                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x17059
 511                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x17059
 512                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x17059
 513                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x17059
 514                         MX6QDL_PAD_NANDF_D0__SD1_DATA4          0x17059
 515                         MX6QDL_PAD_NANDF_D1__SD1_DATA5          0x17059
 516                         MX6QDL_PAD_NANDF_D2__SD1_DATA6          0x17059
 517                         MX6QDL_PAD_NANDF_D3__SD1_DATA7          0x17059
 518                 >;
 519         };
 520
 521         pinctrl_usdhc2: usdhc2grp {
 522                 fsl,pins = <
 523                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 524                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 525                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 526                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 527                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 528                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 529                         MX6QDL_PAD_EIM_RW__GPIO2_IO26                   0x15059 /*WL_EN_LDO*/
 530                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24          0x15059 /*WL_EN*/
 531                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x15059 /*WL_IRQ*/
 532                 >;
 533         };
 534
 535         pinctrl_usdhc3: usdhc3grp {
 536                 fsl,pins = <
 537                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17071
 538                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10071
 539                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17071
 540                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17071
 541                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17071
 542                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17071
 543                 >;
 544         };
 545
 546         pinctrl_wdog: wdoggrp {
 547                 fsl,pins = <
 548                         MX6QDL_PAD_GPIO_1__WDOG2_B      0x1b0b00
 549                 >;
 550         };
 551 };
 552
 553 &ldb {
 554         status = "okay";
 555
 556         lvds-channel@1 {
 557                 fsl,data-mapping = "spwg";
 558                 fsl,data-width = <18>;
 559                 status = "okay";
 560
 561                 port@4 {
 562                         reg = <4>;
 563
 564                         lvds0_out: endpoint {
 565                                 remote-endpoint = <&panel_in>;
 566                         };
 567                 };
 568         };
 569 };
 570
 571 &pwm1 {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&pinctrl_pwm1>;
 574         status = "okay";
 575 };
 576
 577 &snvs_poweroff {
 578         status = "okay";
 579 };
 580
 581 &ssi1 {
 582         status = "okay";
 583 };
 584
 585 &uart1 {
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&pinctrl_uart1>;
 588         uart-has-rtscts;
 589         fsl,dte-mode;
 590         status = "okay";
 591 };
 592
 593 &uart2 {
 594         pinctrl-names = "default";
 595         pinctrl-0 = <&pinctrl_uart2>;
 596         uart-has-rtscts;
 597         status = "okay";
 598 };
 599
 600 &uart3 {
 601         pinctrl-names = "default";
 602         pinctrl-0 = <&pinctrl_uart3>;
 603         uart-has-rtscts;
 604         status = "okay";
 605 };
 606
 607 &uart4 {
 608         pinctrl-names = "default";
 609         pinctrl-0 = <&pinctrl_uart4>;
 610         uart-has-rtscts;
 611         status = "okay";
 612 };
 613
 614 &uart5 {
 615         pinctrl-names = "default";
 616         pinctrl-0 = <&pinctrl_uart5>;
 617         uart-has-rtscts;
 618         status = "okay";
 619 };
 620
 621 &usbotg {
 622         vbus-supply = <&reg_usb_otg_vbus>;
 623         pinctrl-names = "default";
 624         pinctrl-0 = <&pinctrl_usbotg>;
 625         disable-over-current;
 626         srp-disable;
 627         hnp-disable;
 628         adp-disable;
 629         status = "okay";
 630 };
 631
 632 &usbh1 {
 633         status = "okay";
 634 };
 635
 636 &usbphy1 {
 637         fsl,tx-d-cal = <0x5>;
 638 };
 639
 640 &usbphy2 {
 641         fsl,tx-d-cal = <0x5>;
 642 };
 643
 644 &usdhc1 {
 645         pinctrl-names = "default";
 646         pinctrl-0 = <&pinctrl_usdhc1>;
 647         bus-width = <8>;
 648         keep-power-in-suspend;
 649         vmmc-supply = <&reg_3p3v>;
 650         status = "okay";
 651 };
 652
 653 &usdhc2 {
 654         pinctrl-names = "default";
 655         pinctrl-0 = <&pinctrl_usdhc2>;
 656         bus-width = <4>;
 657         vmmc-supply = <&wlan_en_reg>;
 658         no-1-8-v;
 659         keep-power-in-suspend;
 660         non-removable;
 661         cap-power-off-card;
 662         status = "okay";
 663
 664         #address-cells = <1>;
 665         #size-cells = <0>;
 666         wlcore: wlcore@2 {
 667                 compatible = "ti,wl1835";
 668                 reg = <2>;
 669                 interrupt-parent = <&gpio5>;
 670                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
 671                 ref-clock-frequency = <38400000>;
 672                 tcxo-clock-frequency = <26000000>;
 673         };
 674 };
 675
 676 &usdhc3 {
 677         pinctrl-names = "default";
 678         pinctrl-0 = <&pinctrl_usdhc3>;
 679         bus-width = <4>;
 680         cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 681         no-1-8-v;
 682         keep-power-in-suspend;
 683         wakeup-source;
 684         status = "okay";
 685 };
 686
 687 &sata {
 688         status = "okay";
 689 };
 690
 691 &wdog1 {
 692         status = "okay";
 693 };