arch/arm/boot/dts/imx6q-display5.dtsi

   1 /*
   2  * Copyright 2017
   3  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is licensed under the terms of the GNU General Public
  11  *     License version 2.  This program is licensed "as is" without
  12  *     any warranty of any kind, whether express or implied.
  13  *
  14  * Or, alternatively,
  15  *
  16  *  b) Permission is hereby granted, free of charge, to any person
  17  *     obtaining a copy of this software and associated documentation
  18  *     files (the "Software"), to deal in the Software without
  19  *     restriction, including without limitation the rights to use,
  20  *     copy, modify, merge, publish, distribute, sublicense, and/or
  21  *     sell copies of the Software, and to permit persons to whom the
  22  *     Software is furnished to do so, subject to the following
  23  *     conditions:
  24  *
  25  *     The above copyright notice and this permission notice shall be
  26  *     included in all copies or substantial portions of the Software.
  27  *
  28  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  29  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  30  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  31  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  32  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  33  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  34  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  35  *     OTHER DEALINGS IN THE SOFTWARE.
  36  */
  37
  38 /dts-v1/;
  39
  40 #include "imx6q.dtsi"
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/pwm/pwm.h>
  44 #include <dt-bindings/sound/fsl-imx-audmux.h>
  45
  46 / {
  47         model = "Liebherr (LWN) display5 i.MX6 Quad Board";
  48         compatible = "lwn,display5", "fsl,imx6q";
  49
  50         memory@10000000 {
  51                 reg = <0x10000000 0x40000000>;
  52         };
  53
  54         backlight_lvds: backlight {
  55                 compatible = "pwm-backlight";
  56                 pinctrl-names = "default";
  57                 pinctrl-0 = <&pinctrl_backlight>;
  58                 pwms = <&pwm2 0 5000000 0>;
  59                 brightness-levels = <  0   1   2   3   4   5   6   7   8   9
  60                                       10  11  12  13  14  15  16  17  18  19
  61                                       20  21  22  23  24  25  26  27  28  29
  62                                       30  31  32  33  34  35  36  37  38  39
  63                                       40  41  42  43  44  45  46  47  48  49
  64                                       50  51  52  53  54  55  56  57  58  59
  65                                       60  61  62  63  64  65  66  67  68  69
  66                                       70  71  72  73  74  75  76  77  78  79
  67                                       80  81  82  83  84  85  86  87  88  89
  68                                       90  91  92  93  94  95  96  97  98  99
  69                                      100 101 102 103 104 105 106 107 108 109
  70                                      110 111 112 113 114 115 116 117 118 119
  71                                      120 121 122 123 124 125 126 127 128 129
  72                                      130 131 132 133 134 135 136 137 138 139
  73                                      140 141 142 143 144 145 146 147 148 149
  74                                      150 151 152 153 154 155 156 157 158 159
  75                                      160 161 162 163 164 165 166 167 168 169
  76                                      170 171 172 173 174 175 176 177 178 179
  77                                      180 181 182 183 184 185 186 187 188 189
  78                                      190 191 192 193 194 195 196 197 198 199
  79                                      200 201 202 203 204 205 206 207 208 209
  80                                      210 211 212 213 214 215 216 217 218 219
  81                                      220 221 222 223 224 225 226 227 228 229
  82                                      230 231 232 233 234 235 236 237 238 239
  83                                      240 241 242 243 244 245 246 247 248 249
  84                                      250 251 252 253 254 255>;
  85                 default-brightness-level = <250>;
  86                 enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  87         };
  88
  89         reg_lvds: regulator-lvds {
  90                 compatible = "regulator-fixed";
  91                 regulator-name = "lvds_ppen";
  92                 regulator-min-microvolt = <3300000>;
  93                 regulator-max-microvolt = <3300000>;
  94                 regulator-boot-on;
  95                 regulator-always-on;
  96                 pinctrl-names = "default";
  97                 pinctrl-0 = <&pinctrl_reg_lvds>;
  98                 gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;
  99                 enable-active-high;
 100         };
 101
 102         reg_usbh1_vbus: usb-h1-vbus {
 103                 compatible = "regulator-fixed";
 104                 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
 105                 pinctrl-names = "default";
 106                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
 107                 regulator-name = "usb_h1_vbus";
 108                 regulator-min-microvolt = <5000000>;
 109                 regulator-max-microvolt = <5000000>;
 110                 regulator-enable-ramp-delay = <300000>;
 111         };
 112
 113         sound {
 114                 compatible = "simple-audio-card";
 115                 label = "tfa9879-mono";
 116
 117                 simple-audio-card,dai-link {
 118                         /* DAC */
 119                         format = "i2s";
 120                         bitclock-master = <&dailink_master>;
 121                         frame-master = <&dailink_master>;
 122
 123                         dailink_master: cpu {
 124                             sound-dai = <&ssi2>;
 125                         };
 126                         codec {
 127                             sound-dai = <&codec>;
 128                         };
 129                 };
 130         };
 131
 132         panel: panel-lvds0 {
 133                 backlight = <&backlight_lvds>;
 134                 power-supply = <&reg_lvds>;
 135
 136                 port {
 137                         panel_in_lvds0: endpoint {
 138                                 remote-endpoint = <&lvds0_out>;
 139                         };
 140                 };
 141         };
 142 };
 143
 144 &audmux {
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_audmux>;
 147         status = "okay";
 148
 149         ssi2 {
 150                 fsl,audmux-port = <1>;
 151                 fsl,port-config = <
 152                         (IMX_AUDMUX_V2_PTCR_SYN |
 153                          IMX_AUDMUX_V2_PTCR_TFSEL(5) |
 154                          IMX_AUDMUX_V2_PTCR_TCSEL(5) |
 155                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 156                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 157                         IMX_AUDMUX_V2_PDCR_RXDSEL(5)
 158                 >;
 159         };
 160
 161         aud6 {
 162                 fsl,audmux-port = <5>;
 163                 fsl,port-config = <
 164                         (IMX_AUDMUX_V2_PTCR_RFSEL(8) |
 165                          IMX_AUDMUX_V2_PTCR_RCSEL(8) |
 166                          IMX_AUDMUX_V2_PTCR_TFSEL(1) |
 167                          IMX_AUDMUX_V2_PTCR_TCSEL(1) |
 168                          IMX_AUDMUX_V2_PTCR_RFSDIR |
 169                          IMX_AUDMUX_V2_PTCR_RCLKDIR |
 170                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 171                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 172                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 173                 >;
 174         };
 175 };
 176
 177 &ecspi2 {
 178         cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>;
 181         status = "okay";
 182
 183         s25fl256s: flash@0 {
 184                 #address-cells = <1>;
 185                 #size-cells = <1>;
 186                 compatible = "jedec,spi-nor";
 187                 spi-max-frequency = <40000000>;
 188                 reg = <0>;
 189
 190                 partition@0 {
 191                         label = "SPL (spi)";
 192                         reg = <0x0 0x20000>;
 193                         read-only;
 194                 };
 195                 partition@1 {
 196                         label = "u-boot (spi)";
 197                         reg = <0x20000 0x100000>;
 198                         read-only;
 199                 };
 200                 partition@2 {
 201                         label = "uboot-env (spi)";
 202                         reg = <0x120000 0x10000>;
 203                 };
 204                 partition@3 {
 205                         label = "uboot-envr (spi)";
 206                         reg = <0x130000 0x10000>;
 207                 };
 208                 partition@4 {
 209                         label = "linux-recovery (spi)";
 210                         reg = <0x140000 0x800000>;
 211                 };
 212                 partition@5 {
 213                         label = "swupdate-fitImg (spi)";
 214                         reg = <0x940000 0x400000>;
 215                 };
 216                 partition@6 {
 217                         label = "swupdate-initramfs (spi)";
 218                         reg = <0xD40000 0x800000>;
 219                 };
 220         };
 221 };
 222
 223 &ecspi3 {
 224         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
 227         status = "okay";
 228 };
 229
 230 &fec {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_enet>;
 233         phy-handle = <&ethernet_phy0>;
 234         phy-mode = "rgmii-id";
 235         status = "okay";
 236
 237         mdio {
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 ethernet_phy0: ethernet-phy@0 {
 241                         compatible = "marvell,88E1510";
 242                         device_type = "ethernet-phy";
 243                         /* Set LED0 control: */
 244                         /* On - Link, Blink - Activity, Off - No Link */
 245                         marvell,reg-init = <3 0x10 0 0x1011>;
 246                         max-speed = <100>;
 247                         reg = <0>;
 248                 };
 249         };
 250 };
 251
 252 &i2c1 {
 253         clock-frequency = <400000>;
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_i2c1>;
 256         status = "okay";
 257
 258         codec: tfa9879@6c {
 259                 #sound-dai-cells = <0>;
 260                 compatible = "nxp,tfa9879";
 261                 reg = <0x6C>;
 262         };
 263 };
 264
 265 &i2c2 {
 266         clock-frequency = <400000>;
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_i2c2>;
 269         status = "okay";
 270 };
 271
 272 &i2c3 {
 273         clock-frequency = <400000>;
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_i2c3>;
 276         status = "okay";
 277
 278         at24@50 {
 279                 compatible = "atmel,24c256";
 280                 pagesize = <64>;
 281                 reg = <0x50>;
 282         };
 283
 284         pfuze100: pmic@8 {
 285                 compatible = "fsl,pfuze100";
 286                 reg = <0x08>;
 287
 288                 regulators {
 289                         sw1a_reg: sw1ab {
 290                                 regulator-min-microvolt = <300000>;
 291                                 regulator-max-microvolt = <1875000>;
 292                                 regulator-boot-on;
 293                                 regulator-always-on;
 294                                 regulator-ramp-delay = <6250>;
 295                         };
 296
 297                         sw1c_reg: sw1c {
 298                                 regulator-min-microvolt = <300000>;
 299                                 regulator-max-microvolt = <1875000>;
 300                                 regulator-boot-on;
 301                                 regulator-always-on;
 302                                 regulator-ramp-delay = <6250>;
 303                         };
 304
 305                         sw2_reg: sw2 {
 306                                 regulator-min-microvolt = <800000>;
 307                                 regulator-max-microvolt = <3950000>;
 308                                 regulator-boot-on;
 309                                 regulator-always-on;
 310                         };
 311
 312                         sw3a_reg: sw3a {
 313                                 regulator-min-microvolt = <400000>;
 314                                 regulator-max-microvolt = <1975000>;
 315                                 regulator-boot-on;
 316                                 regulator-always-on;
 317                         };
 318
 319                         sw3b_reg: sw3b {
 320                                 regulator-min-microvolt = <400000>;
 321                                 regulator-max-microvolt = <1975000>;
 322                                 regulator-boot-on;
 323                                 regulator-always-on;
 324                         };
 325
 326                         sw4_reg: sw4 {
 327                                 regulator-min-microvolt = <800000>;
 328                                 regulator-max-microvolt = <3300000>;
 329                         };
 330
 331                         swbst_reg: swbst {
 332                                 regulator-min-microvolt = <5000000>;
 333                                 regulator-max-microvolt = <5150000>;
 334                         };
 335
 336                         snvs_reg: vsnvs {
 337                                 regulator-min-microvolt = <1000000>;
 338                                 regulator-max-microvolt = <3000000>;
 339                                 regulator-boot-on;
 340                                 regulator-always-on;
 341                         };
 342
 343                         vref_reg: vrefddr {
 344                                 regulator-boot-on;
 345                                 regulator-always-on;
 346                         };
 347
 348                         vgen1_reg: vgen1 {
 349                                 regulator-min-microvolt = <800000>;
 350                                 regulator-max-microvolt = <1550000>;
 351                         };
 352
 353                         vgen2_reg: vgen2 {
 354                                 regulator-min-microvolt = <800000>;
 355                                 regulator-max-microvolt = <1550000>;
 356                         };
 357
 358                         vgen3_reg: vgen3 {
 359                                 regulator-min-microvolt = <1800000>;
 360                                 regulator-max-microvolt = <3300000>;
 361                         };
 362
 363                         vgen4_reg: vgen4 {
 364                                 regulator-min-microvolt = <1800000>;
 365                                 regulator-max-microvolt = <3300000>;
 366                                 regulator-always-on;
 367                         };
 368
 369                         vgen5_reg: vgen5 {
 370                                 regulator-min-microvolt = <1800000>;
 371                                 regulator-max-microvolt = <3300000>;
 372                                 regulator-always-on;
 373                         };
 374
 375                         vgen6_reg: vgen6 {
 376                                 regulator-min-microvolt = <1800000>;
 377                                 regulator-max-microvolt = <3300000>;
 378                                 regulator-always-on;
 379                         };
 380                 };
 381         };
 382 };
 383
 384 &ldb {
 385         status = "okay";
 386
 387         lvds0: lvds-channel@0 {
 388                 status = "okay";
 389
 390                 port@4 {
 391                         reg = <4>;
 392
 393                         lvds0_out: endpoint {
 394                                 remote-endpoint = <&panel_in_lvds0>;
 395                         };
 396                 };
 397         };
 398 };
 399
 400 &pwm2 {
 401         #pwm-cells = <3>;
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_pwm2>;
 404         status = "okay";
 405 };
 406
 407 &ssi2 {
 408         status = "okay";
 409 };
 410
 411 &uart4 {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_uart4>;
 414         uart-has-rtscts;
 415         status = "okay";
 416 };
 417
 418 &uart5 {
 419         pinctrl-names = "default";
 420         pinctrl-0 = <&pinctrl_uart5>;
 421         status = "okay";
 422 };
 423
 424 &usbh1 {
 425         vbus-supply = <&reg_usbh1_vbus>;
 426         pinctrl-0 = <&pinctrl_usbh1>;
 427         status = "okay";
 428 };
 429
 430 &usdhc4 {
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&pinctrl_usdhc4>;
 433         bus-width = <8>;
 434         non-removable;
 435         status = "okay";
 436 };
 437
 438 &iomuxc {
 439         pinctrl_audmux: audmuxgrp {
 440                 fsl,pins = <
 441                         /* I2S OUTPUT AUD6*/
 442                         MX6QDL_PAD_DI0_PIN4__AUD6_RXD  0x130b0
 443                         MX6QDL_PAD_DI0_PIN2__AUD6_TXD  0x130b0
 444                         MX6QDL_PAD_DI0_PIN3__AUD6_TXFS  0x130b0
 445                         MX6QDL_PAD_DI0_PIN15__AUD6_TXC  0x130b0
 446                 >;
 447         };
 448
 449         pinctrl_backlight: dispgrp {
 450                 fsl,pins = <
 451                         /* BLEN_OUT */
 452                         MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07    0x1b0b0
 453                 >;
 454         };
 455
 456         pinctrl_ecspi2: ecspi2grp {
 457                 fsl,pins = <
 458                         MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO      0x100b1
 459                         MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI       0x100b1
 460                         MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK       0x100b1
 461                 >;
 462         };
 463
 464         pinctrl_ecspi2_cs: ecspi2csgrp {
 465                 fsl,pins = <
 466                         MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
 467                 >;
 468         };
 469
 470         pinctrl_ecspi2_flwp: ecspi2flwpgrp {
 471                 fsl,pins = <
 472                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
 473                 >;
 474         };
 475
 476         pinctrl_ecspi3: ecspi3grp {
 477                 fsl,pins = <
 478                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 479                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 480                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 481                 >;
 482         };
 483
 484         pinctrl_ecspi3_cs: ecspi3csgrp {
 485                 fsl,pins = <
 486                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
 487                 >;
 488         };
 489
 490         pinctrl_ecspi3_flwp: ecspi3flwpgrp {
 491                 fsl,pins = <
 492                         MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
 493                 >;
 494         };
 495
 496         pinctrl_enet: enetgrp {
 497                 fsl,pins = <
 498                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 499                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 500                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 501                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 502                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 503                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 504                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 505                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 506                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 507                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 508                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 509                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 510                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 511                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 512                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 513                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
 514                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 515                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
 516                 >;
 517         };
 518
 519         pinctrl_i2c1: i2c1grp {
 520                 fsl,pins = <
 521                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
 522                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
 523                 >;
 524         };
 525
 526         pinctrl_i2c2: i2c2grp {
 527                 fsl,pins = <
 528                         MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 529                         MX6QDL_PAD_EIM_D16__I2C2_SDA    0x4001b8b1
 530                 >;
 531         };
 532
 533         pinctrl_i2c3: i2c3grp {
 534                 fsl,pins = <
 535                         MX6QDL_PAD_EIM_D17__I2C3_SCL    0x4001b8b1
 536                         MX6QDL_PAD_EIM_D18__I2C3_SDA    0x4001b8b1
 537                 >;
 538         };
 539
 540         pinctrl_pwm2: pwm2grp {
 541                 fsl,pins = <
 542                         MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
 543                 >;
 544         };
 545
 546         pinctrl_reg_lvds: reqlvdsgrp {
 547                 fsl,pins = <
 548                         /* LVDS_PPEN_OUT */
 549                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 550                 >;
 551         };
 552
 553         pinctrl_uart4: uart4grp {
 554                 fsl,pins = <
 555                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 556                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 557                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 558                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 559                 >;
 560         };
 561
 562         pinctrl_uart5: uart5grp {
 563                 fsl,pins = <
 564                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x1b0b1
 565                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x1b0b1
 566                 >;
 567         };
 568
 569         pinctrl_usbh1: usbh1grp {
 570                 fsl,pins = <
 571                         MX6QDL_PAD_EIM_D30__USB_H1_OC  0x030b0
 572                 >;
 573         };
 574
 575         pinctrl_usbh1_vbus: usbh1_vbus_grp {
 576                 fsl,pins = <
 577                         MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
 578                 >;
 579         };
 580
 581         pinctrl_usdhc4: usdhc4grp {
 582                 fsl,pins = <
 583                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 584                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 585                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 586                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 587                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 588                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 589                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 590                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 591                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 592                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 593                         MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059
 594                 >;
 595         };
 596 };