GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / imx6q-dhcom-som.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+)
2 /*
3  * Copyright (C) 2015 DH electronics GmbH
4  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5  */
6
7 #include "imx6q.dtsi"
8 #include <dt-bindings/pwm/pwm.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/imx6qdl-clock.h>
11 #include <dt-bindings/input/input.h>
12
13 / {
14         aliases {
15                 mmc0 = &usdhc2;
16                 mmc1 = &usdhc3;
17                 mmc2 = &usdhc4;
18                 mmc3 = &usdhc1;
19         };
20
21         memory@10000000 {
22                 reg = <0x10000000 0x40000000>;
23         };
24
25         reg_usb_otg_vbus: regulator-usb-otg-vbus {
26                 compatible = "regulator-fixed";
27                 regulator-name = "usb_otg_vbus";
28                 regulator-min-microvolt = <5000000>;
29                 regulator-max-microvolt = <5000000>;
30         };
31
32         reg_usb_h1_vbus: regulator-usb-h1-vbus {
33                 compatible = "regulator-fixed";
34                 regulator-name = "usb_h1_vbus";
35                 regulator-min-microvolt = <5000000>;
36                 regulator-max-microvolt = <5000000>;
37                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
38                 enable-active-high;
39         };
40
41         reg_3p3v: regulator-3P3V {
42                 compatible = "regulator-fixed";
43                 regulator-name = "3P3V";
44                 regulator-min-microvolt = <3300000>;
45                 regulator-max-microvolt = <3300000>;
46                 regulator-always-on;
47         };
48 };
49
50 &can1 {
51         pinctrl-names = "default";
52         pinctrl-0 = <&pinctrl_flexcan1>;
53         status = "okay";
54 };
55
56 &can2 {
57         pinctrl-names = "default";
58         pinctrl-0 = <&pinctrl_flexcan2>;
59         status = "okay";
60 };
61
62 &ecspi1 {
63         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio4 11 GPIO_ACTIVE_HIGH>;
64         pinctrl-names = "default";
65         pinctrl-0 = <&pinctrl_ecspi1>;
66         status = "okay";
67
68         flash@0 {       /* S25FL116K */
69                 #address-cells = <1>;
70                 #size-cells = <1>;
71                 compatible = "jedec,spi-nor";
72                 spi-max-frequency = <50000000>;
73                 reg = <0>;
74                 m25p,fast-read;
75         };
76 };
77
78 &ecspi2 {
79         cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
80         pinctrl-names = "default";
81         pinctrl-0 = <&pinctrl_ecspi2>;
82         status = "okay";
83 };
84
85 &fec {
86         pinctrl-names = "default";
87         pinctrl-0 = <&pinctrl_enet_100M>;
88         phy-mode = "rmii";
89         phy-handle = <&ethphy0>;
90         status = "okay";
91
92         mdio {
93                 #address-cells = <1>;
94                 #size-cells = <0>;
95
96                 ethphy0: ethernet-phy@0 {       /* SMSC LAN8710Ai */
97                         reg = <0>;
98                         max-speed = <100>;
99                         reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
100                         reset-assert-us = <1000>;
101                         reset-deassert-us = <1000>;
102                         smsc,disable-energy-detect; /* Make plugin detection reliable */
103                 };
104         };
105 };
106
107 &i2c1 {
108         clock-frequency = <100000>;
109         pinctrl-names = "default", "gpio";
110         pinctrl-0 = <&pinctrl_i2c1>;
111         pinctrl-1 = <&pinctrl_i2c1_gpio>;
112         scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
113         sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
114         status = "okay";
115 };
116
117 &i2c2 {
118         clock-frequency = <100000>;
119         pinctrl-names = "default", "gpio";
120         pinctrl-0 = <&pinctrl_i2c2>;
121         pinctrl-1 = <&pinctrl_i2c2_gpio>;
122         scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
123         sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
124         status = "okay";
125 };
126
127 &i2c3 {
128         clock-frequency = <100000>;
129         pinctrl-names = "default", "gpio";
130         pinctrl-0 = <&pinctrl_i2c3>;
131         pinctrl-1 = <&pinctrl_i2c3_gpio>;
132         scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
133         sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
134         status = "okay";
135
136         ltc3676: pmic@3c {
137                 compatible = "lltc,ltc3676";
138                 pinctrl-names = "default";
139                 pinctrl-0 = <&pinctrl_pmic_hw300>;
140                 reg = <0x3c>;
141                 interrupt-parent = <&gpio5>;
142                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
143
144                 regulators {
145                         sw1_reg: sw1 {
146                                 regulator-min-microvolt = <787500>;
147                                 regulator-max-microvolt = <1527272>;
148                                 lltc,fb-voltage-divider = <100000 110000>;
149                                 regulator-suspend-mem-microvolt = <1040000>;
150                                 regulator-ramp-delay = <7000>;
151                                 regulator-boot-on;
152                                 regulator-always-on;
153                         };
154
155                         sw2_reg: sw2 {
156                                 regulator-min-microvolt = <1885714>;
157                                 regulator-max-microvolt = <3657142>;
158                                 lltc,fb-voltage-divider = <100000 28000>;
159                                 regulator-ramp-delay = <7000>;
160                                 regulator-boot-on;
161                                 regulator-always-on;
162                         };
163
164                         sw3_reg: sw3 {
165                                 regulator-min-microvolt = <787500>;
166                                 regulator-max-microvolt = <1527272>;
167                                 lltc,fb-voltage-divider = <100000 110000>;
168                                 regulator-suspend-mem-microvolt = <980000>;
169                                 regulator-ramp-delay = <7000>;
170                                 regulator-boot-on;
171                                 regulator-always-on;
172                         };
173
174                         sw4_reg: sw4 {
175                                 regulator-min-microvolt = <855571>;
176                                 regulator-max-microvolt = <1659291>;
177                                 lltc,fb-voltage-divider = <100000 93100>;
178                                 regulator-ramp-delay = <7000>;
179                                 regulator-boot-on;
180                                 regulator-always-on;
181                         };
182
183                         ldo1_reg: ldo1 {
184                                 regulator-min-microvolt = <3240306>;
185                                 regulator-max-microvolt = <3240306>;
186                                 lltc,fb-voltage-divider = <102000 29400>;
187                                 regulator-boot-on;
188                                 regulator-always-on;
189                         };
190
191                         ldo2_reg: ldo2 {
192                                 regulator-min-microvolt = <2484708>;
193                                 regulator-max-microvolt = <2484708>;
194                                 lltc,fb-voltage-divider = <100000 41200>;
195                                 regulator-boot-on;
196                                 regulator-always-on;
197                         };
198                 };
199         };
200
201         touchscreen@49 {        /* TSC2004 */
202                 compatible = "ti,tsc2004";
203                 reg = <0x49>;
204                 vio-supply = <&reg_3p3v>;
205                 pinctrl-names = "default";
206                 pinctrl-0 = <&pinctrl_tsc2004_hw300>;
207                 interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
208                 status = "disabled";
209         };
210
211         eeprom@50 {
212                 compatible = "atmel,24c02";
213                 reg = <0x50>;
214                 pagesize = <16>;
215         };
216
217         rtc@56 {
218                 compatible = "microcrystal,rv3029";
219                 pinctrl-names = "default";
220                 pinctrl-0 = <&pinctrl_rtc_hw300>;
221                 reg = <0x56>;
222                 interrupt-parent = <&gpio7>;
223                 interrupts = <12 2>;
224         };
225 };
226
227 &iomuxc {
228         pinctrl-names = "default";
229         pinctrl-0 = <&pinctrl_hog_base>;
230
231         pinctrl_hog_base: hog-base-grp {
232                 fsl,pins = <
233                         MX6QDL_PAD_EIM_A19__GPIO2_IO19          0x120b0
234                         MX6QDL_PAD_EIM_A23__GPIO6_IO06          0x120b0
235                         MX6QDL_PAD_EIM_A22__GPIO2_IO16          0x120b0
236                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x120b0
237                         MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x120b0
238                 >;
239         };
240
241         pinctrl_ecspi1: ecspi1-grp {
242                 fsl,pins = <
243                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
244                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
245                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
246                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b0
247                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
248                 >;
249         };
250
251         pinctrl_ecspi2: ecspi2-grp {
252                 fsl,pins = <
253                         MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO      0x100b1
254                         MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI       0x100b1
255                         MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK       0x100b1
256                         MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29       0x1b0b0
257                 >;
258         };
259
260         pinctrl_enet_100M: enet-100M-grp {
261                 fsl,pins = <
262                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
263                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
264                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
265                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
266                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
267                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
268                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
269                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
270                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
271                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
272                         MX6QDL_PAD_EIM_WAIT__GPIO5_IO00         0x000b0
273                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x000b1
274                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x120b0
275                 >;
276         };
277
278         pinctrl_flexcan1: flexcan1-grp {
279                 fsl,pins = <
280                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
281                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
282                 >;
283         };
284
285         pinctrl_flexcan2: flexcan2-grp {
286                 fsl,pins = <
287                         MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX        0x1b0b0
288                         MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX        0x1b0b0
289                 >;
290         };
291
292         pinctrl_i2c1: i2c1-grp {
293                 fsl,pins = <
294                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
295                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
296                 >;
297         };
298
299         pinctrl_i2c1_gpio: i2c1-gpio-grp {
300                 fsl,pins = <
301                         MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x4001b8b1
302                         MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x4001b8b1
303                 >;
304         };
305
306         pinctrl_i2c2: i2c2-grp {
307                 fsl,pins = <
308                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
309                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
310                 >;
311         };
312
313         pinctrl_i2c2_gpio: i2c2-gpio-grp {
314                 fsl,pins = <
315                         MX6QDL_PAD_KEY_COL3__GPIO4_IO12         0x4001b8b1
316                         MX6QDL_PAD_KEY_ROW3__GPIO4_IO13         0x4001b8b1
317                 >;
318         };
319
320         pinctrl_i2c3: i2c3-grp {
321                 fsl,pins = <
322                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
323                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
324                 >;
325         };
326
327         pinctrl_i2c3_gpio: i2c3-gpio-grp {
328                 fsl,pins = <
329                         MX6QDL_PAD_GPIO_3__GPIO1_IO03           0x4001b8b1
330                         MX6QDL_PAD_GPIO_6__GPIO1_IO06           0x4001b8b1
331                 >;
332         };
333
334         pinctrl_pmic_hw300: pmic-hw300-grp {
335                 fsl,pins = <
336                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1B0B0
337                 >;
338         };
339
340         pinctrl_rtc_hw300: rtc-hw300-grp {
341                 fsl,pins = <
342                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x120B0
343                 >;
344         };
345
346         pinctrl_tsc2004_hw300: tsc2004-hw300-grp {
347                 fsl,pins = <
348                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x120B0
349                 >;
350         };
351
352         pinctrl_uart1: uart1-grp {
353                 fsl,pins = <
354                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
355                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
356                         MX6QDL_PAD_EIM_D20__UART1_RTS_B         0x1b0b1
357                         MX6QDL_PAD_EIM_D19__UART1_CTS_B         0x4001b0b1
358                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x4001b0b1
359                         MX6QDL_PAD_EIM_D24__GPIO3_IO24          0x4001b0b1
360                         MX6QDL_PAD_EIM_D25__GPIO3_IO25          0x4001b0b1
361                         MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x4001b0b1
362                 >;
363         };
364
365         pinctrl_uart4: uart4-grp {
366                 fsl,pins = <
367                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
368                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
369                 >;
370         };
371
372         pinctrl_uart5: uart5-grp {
373                 fsl,pins = <
374                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x1b0b1
375                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x1b0b1
376                         MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B      0x1b0b1
377                         MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B      0x4001b0b1
378                 >;
379         };
380
381         pinctrl_usbh1: usbh1-grp {
382                 fsl,pins = <
383                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x120B0
384                 >;
385         };
386
387         pinctrl_usbotg: usbotg-grp {
388                 fsl,pins = <
389                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
390                 >;
391         };
392
393         pinctrl_usdhc2: usdhc2-grp {
394                 fsl,pins = <
395                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
396                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
397                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
398                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
399                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
400                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
401                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x120B0
402                 >;
403         };
404
405         pinctrl_usdhc3: usdhc3-grp {
406                 fsl,pins = <
407                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
408                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
409                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
410                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
411                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
412                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
413                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x120B0
414                 >;
415         };
416
417         pinctrl_usdhc4: usdhc4-grp {
418                 fsl,pins = <
419                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
420                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
421                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
422                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
423                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
424                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
425                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
426                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
427                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
428                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
429                 >;
430         };
431 };
432
433 &reg_arm {
434         vin-supply = <&sw3_reg>;
435 };
436
437 &reg_soc {
438         vin-supply = <&sw1_reg>;
439 };
440
441 &reg_pu {
442         vin-supply = <&sw1_reg>;
443 };
444
445 &reg_vdd1p1 {
446         vin-supply = <&sw2_reg>;
447 };
448
449 &reg_vdd2p5 {
450         vin-supply = <&sw2_reg>;
451 };
452
453 &uart1 {
454         pinctrl-names = "default";
455         pinctrl-0 = <&pinctrl_uart1>;
456         uart-has-rtscts;
457         dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
458         dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
459         dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
460         rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
461         status = "okay";
462 };
463
464 &uart4 {
465         pinctrl-names = "default";
466         pinctrl-0 = <&pinctrl_uart4>;
467         status = "okay";
468 };
469
470 &uart5 {
471         pinctrl-names = "default";
472         pinctrl-0 = <&pinctrl_uart5>;
473         uart-has-rtscts;
474         status = "okay";
475 };
476
477 &usbh1 {
478         pinctrl-names = "default";
479         pinctrl-0 = <&pinctrl_usbh1>;
480         vbus-supply = <&reg_usb_h1_vbus>;
481         dr_mode = "host";
482         status = "okay";
483 };
484
485 &usbotg {
486         vbus-supply = <&reg_usb_otg_vbus>;
487         pinctrl-names = "default";
488         pinctrl-0 = <&pinctrl_usbotg>;
489         disable-over-current;
490         dr_mode = "otg";
491         status = "okay";
492 };
493
494 &usdhc2 {
495         pinctrl-names = "default";
496         pinctrl-0 = <&pinctrl_usdhc2>;
497         cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
498         keep-power-in-suspend;
499         status = "okay";
500 };
501
502 &usdhc3 {
503         pinctrl-names = "default";
504         pinctrl-0 = <&pinctrl_usdhc3>;
505         cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
506         fsl,wp-controller;
507         keep-power-in-suspend;
508         status = "disabled";
509 };
510
511 &usdhc4 {
512         pinctrl-names = "default";
513         pinctrl-0 = <&pinctrl_usdhc4>;
514         non-removable;
515         bus-width = <8>;
516         no-1-8-v;
517         keep-power-in-suspend;
518         status = "okay";
519 };