1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
7 #include "imx6qdl.dtsi"
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
35 clock-latency = <61036>; /* two CLK32 periods */
37 clocks = <&clks IMX6QDL_CLK_ARM>,
38 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39 <&clks IMX6QDL_CLK_STEP>,
40 <&clks IMX6QDL_CLK_PLL1_SW>,
41 <&clks IMX6QDL_CLK_PLL1_SYS>;
42 clock-names = "arm", "pll2_pfd2_396m", "step",
43 "pll1_sw", "pll1_sys";
44 arm-supply = <®_arm>;
45 pu-supply = <®_pu>;
46 soc-supply = <®_soc>;
50 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
60 fsl,soc-operating-points = <
61 /* ARM kHz SOC-PU uV */
66 clock-latency = <61036>; /* two CLK32 periods */
67 clocks = <&clks IMX6QDL_CLK_ARM>,
68 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
69 <&clks IMX6QDL_CLK_STEP>,
70 <&clks IMX6QDL_CLK_PLL1_SW>,
71 <&clks IMX6QDL_CLK_PLL1_SYS>;
72 clock-names = "arm", "pll2_pfd2_396m", "step",
73 "pll1_sw", "pll1_sys";
74 arm-supply = <®_arm>;
75 pu-supply = <®_pu>;
76 soc-supply = <®_soc>;
82 compatible = "mmio-sram";
83 reg = <0x00900000 0x20000>;
84 ranges = <0 0x00900000 0x20000>;
87 clocks = <&clks IMX6QDL_CLK_OCRAM>;
90 aips1: aips-bus@2000000 {
91 iomuxc: iomuxc@20e0000 {
92 compatible = "fsl,imx6dl-iomuxc";
96 reg = <0x020f0000 0x4000>;
97 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
101 reg = <0x020f4000 0x4000>;
102 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
106 aips2: aips-bus@2100000 {
108 #address-cells = <1>;
110 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
111 reg = <0x021f8000 0x4000>;
112 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&clks IMX6DL_CLK_I2C4>;
120 compatible = "fsl,imx-capture-subsystem";
121 ports = <&ipu1_csi0>, <&ipu1_csi1>;
125 compatible = "fsl,imx-display-subsystem";
126 ports = <&ipu1_di0>, <&ipu1_di1>;
131 gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
132 <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
133 <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
134 <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
135 <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
136 <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
137 <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
141 gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
142 <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
143 <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
144 <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
149 gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
154 gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
155 <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
156 <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
157 <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
158 <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
162 gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
163 <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
164 <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
165 <&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
169 gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
170 <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
171 <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
172 <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
173 <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
174 <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
178 gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
179 <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
180 <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
185 compatible = "video-mux";
186 mux-controls = <&mux 0>;
187 #address-cells = <1>;
193 ipu1_csi0_mux_from_mipi_vc0: endpoint {
194 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
201 ipu1_csi0_mux_from_mipi_vc1: endpoint {
202 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
209 ipu1_csi0_mux_from_mipi_vc2: endpoint {
210 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
217 ipu1_csi0_mux_from_mipi_vc3: endpoint {
218 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
225 ipu1_csi0_mux_from_parallel_sensor: endpoint {
232 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
233 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
239 compatible = "video-mux";
240 mux-controls = <&mux 1>;
241 #address-cells = <1>;
247 ipu1_csi1_mux_from_mipi_vc0: endpoint {
248 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
255 ipu1_csi1_mux_from_mipi_vc1: endpoint {
256 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
263 ipu1_csi1_mux_from_mipi_vc2: endpoint {
264 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
271 ipu1_csi1_mux_from_mipi_vc3: endpoint {
272 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
279 ipu1_csi1_mux_from_parallel_sensor: endpoint {
286 ipu1_csi1_mux_to_ipu1_csi1: endpoint {
287 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
294 compatible = "fsl,imx6dl-gpt";
298 compatible = "fsl,imx6dl-hdmi";
302 ipu1_csi1_from_ipu1_csi1_mux: endpoint {
303 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
308 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
309 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
310 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
311 clock-names = "di0_pll", "di1_pll",
312 "di0_sel", "di1_sel",
319 #address-cells = <1>;
322 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
324 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
327 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
329 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
335 #address-cells = <1>;
338 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
340 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
343 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
345 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
351 #address-cells = <1>;
354 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
356 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
359 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
361 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
367 #address-cells = <1>;
370 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
372 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
375 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
377 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
383 mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
384 <0x34 0x00000038>, /* IPU_CSI1_MUX */
385 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
386 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
387 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
388 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
389 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
393 compatible = "fsl,imx6dl-vpu", "cnm,coda960";