arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6dl-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 i2c3 = &i2c4;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         next-level-cache = <&L2>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 996000  1250000
  32                                 792000  1175000
  33                                 396000  1150000
  34                         >;
  35                         fsl,soc-operating-points = <
  36                                 /* ARM kHz  SOC-PU uV */
  37                                 996000  1175000
  38                                 792000  1175000
  39                                 396000  1175000
  40                         >;
  41                         clock-latency = <61036>; /* two CLK32 periods */
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                 };
  60         };
  61
  62         soc {
  63                 ocram: sram@00900000 {
  64                         compatible = "mmio-sram";
  65                         reg = <0x00900000 0x20000>;
  66                         ranges = <0 0x00900000 0x20000>;
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  70                 };
  71
  72                 aips1: aips-bus@02000000 {
  73                         iomuxc: iomuxc@020e0000 {
  74                                 compatible = "fsl,imx6dl-iomuxc";
  75                         };
  76
  77                         pxp: pxp@020f0000 {
  78                                 reg = <0x020f0000 0x4000>;
  79                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
  80                         };
  81
  82                         epdc: epdc@020f4000 {
  83                                 reg = <0x020f4000 0x4000>;
  84                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
  85                         };
  86
  87                         lcdif: lcdif@020f8000 {
  88                                 reg = <0x020f8000 0x4000>;
  89                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
  90                         };
  91                 };
  92
  93                 aips2: aips-bus@02100000 {
  94                         i2c4: i2c@021f8000 {
  95                                 #address-cells = <1>;
  96                                 #size-cells = <0>;
  97                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  98                                 reg = <0x021f8000 0x4000>;
  99                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 100                                 clocks = <&clks IMX6DL_CLK_I2C4>;
 101                                 status = "disabled";
 102                         };
 103                 };
 104         };
 105
 106         capture-subsystem {
 107                 compatible = "fsl,imx-capture-subsystem";
 108                 ports = <&ipu1_csi0>, <&ipu1_csi1>;
 109         };
 110
 111         display-subsystem {
 112                 compatible = "fsl,imx-display-subsystem";
 113                 ports = <&ipu1_di0>, <&ipu1_di1>;
 114         };
 115
 116         gpu-subsystem {
 117                 compatible = "fsl,imx-gpu-subsystem";
 118                 cores = <&gpu_2d>, <&gpu_3d>;
 119         };
 120 };
 121
 122 &gpio1 {
 123         gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
 124                       <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
 125                       <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
 126                       <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
 127                       <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
 128                       <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
 129                       <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
 130 };
 131
 132 &gpio2 {
 133         gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
 134                       <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
 135                       <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
 136                       <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
 137                       <&iomuxc 28 113 4>;
 138 };
 139
 140 &gpio3 {
 141         gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
 142                       <&iomuxc 16 81 16>;
 143 };
 144
 145 &gpio4 {
 146         gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
 147                       <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
 148                       <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
 149                       <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
 150                       <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
 151 };
 152
 153 &gpio5 {
 154         gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
 155                       <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
 156                       <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
 157                       <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
 158 };
 159
 160 &gpio6 {
 161         gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
 162                       <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
 163                       <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
 164                       <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
 165                       <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
 166                       <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
 167 };
 168
 169 &gpio7 {
 170         gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
 171                       <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
 172                       <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
 173 };
 174
 175 &gpr {
 176         ipu1_csi0_mux: ipu1_csi0_mux@34 {
 177                 compatible = "video-mux";
 178                 mux-controls = <&mux 0>;
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181
 182                 port@0 {
 183                         reg = <0>;
 184
 185                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 186                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 187                         };
 188                 };
 189
 190                 port@1 {
 191                         reg = <1>;
 192
 193                         ipu1_csi0_mux_from_mipi_vc1: endpoint {
 194                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
 195                         };
 196                 };
 197
 198                 port@2 {
 199                         reg = <2>;
 200
 201                         ipu1_csi0_mux_from_mipi_vc2: endpoint {
 202                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
 203                         };
 204                 };
 205
 206                 port@3 {
 207                         reg = <3>;
 208
 209                         ipu1_csi0_mux_from_mipi_vc3: endpoint {
 210                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
 211                         };
 212                 };
 213
 214                 port@4 {
 215                         reg = <4>;
 216
 217                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 218                         };
 219                 };
 220
 221                 port@5 {
 222                         reg = <5>;
 223
 224                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 225                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 226                         };
 227                 };
 228         };
 229
 230         ipu1_csi1_mux: ipu1_csi1_mux@34 {
 231                 compatible = "video-mux";
 232                 mux-controls = <&mux 1>;
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235
 236                 port@0 {
 237                         reg = <0>;
 238
 239                         ipu1_csi1_mux_from_mipi_vc0: endpoint {
 240                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
 241                         };
 242                 };
 243
 244                 port@1 {
 245                         reg = <1>;
 246
 247                         ipu1_csi1_mux_from_mipi_vc1: endpoint {
 248                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
 249                         };
 250                 };
 251
 252                 port@2 {
 253                         reg = <2>;
 254
 255                         ipu1_csi1_mux_from_mipi_vc2: endpoint {
 256                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
 257                         };
 258                 };
 259
 260                 port@3 {
 261                         reg = <3>;
 262
 263                         ipu1_csi1_mux_from_mipi_vc3: endpoint {
 264                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
 265                         };
 266                 };
 267
 268                 port@4 {
 269                         reg = <4>;
 270
 271                         ipu1_csi1_mux_from_parallel_sensor: endpoint {
 272                         };
 273                 };
 274
 275                 port@5 {
 276                         reg = <5>;
 277
 278                         ipu1_csi1_mux_to_ipu1_csi1: endpoint {
 279                                 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
 280                         };
 281                 };
 282         };
 283 };
 284
 285 &gpt {
 286         compatible = "fsl,imx6dl-gpt";
 287 };
 288
 289 &hdmi {
 290         compatible = "fsl,imx6dl-hdmi";
 291 };
 292
 293 &ipu1_csi1 {
 294         ipu1_csi1_from_ipu1_csi1_mux: endpoint {
 295                 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
 296         };
 297 };
 298
 299 &ldb {
 300         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 301                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 302                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 303         clock-names = "di0_pll", "di1_pll",
 304                       "di0_sel", "di1_sel",
 305                       "di0", "di1";
 306 };
 307
 308 &mipi_csi {
 309         port@1 {
 310                 reg = <1>;
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313
 314                 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
 315                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 316                 };
 317
 318                 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
 319                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
 320                 };
 321         };
 322
 323         port@2 {
 324                 reg = <2>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327
 328                 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
 329                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
 330                 };
 331
 332                 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
 333                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
 334                 };
 335         };
 336
 337         port@3 {
 338                 reg = <3>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341
 342                 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
 343                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
 344                 };
 345
 346                 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
 347                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
 348                 };
 349         };
 350
 351         port@4 {
 352                 reg = <4>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355
 356                 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
 357                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
 358                 };
 359
 360                 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
 361                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
 362                 };
 363         };
 364 };
 365
 366 &mux {
 367         mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
 368                         <0x34 0x00000038>, /* IPU_CSI1_MUX */
 369                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 370                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 371                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 372                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 373                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 374 };
 375
 376 &vpu {
 377         compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 378 };