2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "imx53-pinfunc.h"
14 #include <dt-bindings/clock/imx5-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
23 * The decompressor and also some bootloaders rely on a
24 * pre-existing /chosen node to be available to insert the
25 * command line and merge other ATAGS info.
60 compatible = "arm,cortex-a8";
62 clocks = <&clks IMX5_CLK_ARM>;
63 clock-latency = <61036>;
64 voltage-tolerance = <5>;
77 compatible = "fsl,imx-display-subsystem";
78 ports = <&ipu_di0>, <&ipu_di1>;
81 tzic: tz-interrupt-controller@fffc000 {
82 compatible = "fsl,imx53-tzic", "fsl,tzic";
84 #interrupt-cells = <1>;
85 reg = <0x0fffc000 0x4000>;
90 compatible = "fsl,imx-ckil", "fixed-clock";
92 clock-frequency = <32768>;
96 compatible = "fsl,imx-ckih1", "fixed-clock";
98 clock-frequency = <22579200>;
102 compatible = "fsl,imx-ckih2", "fixed-clock";
104 clock-frequency = <0>;
108 compatible = "fsl,imx-osc", "fixed-clock";
110 clock-frequency = <24000000>;
115 compatible = "arm,cortex-a8-pmu";
116 interrupt-parent = <&tzic>;
121 compatible = "usb-nop-xceiv";
122 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
123 clock-names = "main_clk";
129 compatible = "usb-nop-xceiv";
130 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
131 clock-names = "main_clk";
137 #address-cells = <1>;
139 compatible = "simple-bus";
140 interrupt-parent = <&tzic>;
143 sata: sata@10000000 {
144 compatible = "fsl,imx53-ahci";
145 reg = <0x10000000 0x1000>;
147 clocks = <&clks IMX5_CLK_SATA_GATE>,
148 <&clks IMX5_CLK_SATA_REF>,
149 <&clks IMX5_CLK_AHB>;
150 clock-names = "sata", "sata_ref", "ahb";
155 #address-cells = <1>;
157 compatible = "fsl,imx53-ipu";
158 reg = <0x18000000 0x08000000>;
159 interrupts = <11 10>;
160 clocks = <&clks IMX5_CLK_IPU_GATE>,
161 <&clks IMX5_CLK_IPU_DI0_GATE>,
162 <&clks IMX5_CLK_IPU_DI1_GATE>;
163 clock-names = "bus", "di0", "di1";
175 #address-cells = <1>;
179 ipu_di0_disp0: endpoint@0 {
183 ipu_di0_lvds0: endpoint@1 {
185 remote-endpoint = <&lvds0_in>;
190 #address-cells = <1>;
194 ipu_di1_disp1: endpoint@0 {
198 ipu_di1_lvds1: endpoint@1 {
200 remote-endpoint = <&lvds1_in>;
203 ipu_di1_tve: endpoint@2 {
205 remote-endpoint = <&tve_in>;
210 aips@50000000 { /* AIPS1 */
211 compatible = "fsl,aips-bus", "simple-bus";
212 #address-cells = <1>;
214 reg = <0x50000000 0x10000000>;
218 compatible = "fsl,spba-bus", "simple-bus";
219 #address-cells = <1>;
221 reg = <0x50000000 0x40000>;
224 esdhc1: esdhc@50004000 {
225 compatible = "fsl,imx53-esdhc";
226 reg = <0x50004000 0x4000>;
228 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
229 <&clks IMX5_CLK_DUMMY>,
230 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
231 clock-names = "ipg", "ahb", "per";
236 esdhc2: esdhc@50008000 {
237 compatible = "fsl,imx53-esdhc";
238 reg = <0x50008000 0x4000>;
240 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
241 <&clks IMX5_CLK_DUMMY>,
242 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
243 clock-names = "ipg", "ahb", "per";
248 uart3: serial@5000c000 {
249 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
250 reg = <0x5000c000 0x4000>;
252 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
253 <&clks IMX5_CLK_UART3_PER_GATE>;
254 clock-names = "ipg", "per";
255 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
256 dma-names = "rx", "tx";
260 ecspi1: ecspi@50010000 {
261 #address-cells = <1>;
263 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
264 reg = <0x50010000 0x4000>;
266 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
267 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
268 clock-names = "ipg", "per";
273 #sound-dai-cells = <0>;
274 compatible = "fsl,imx53-ssi",
277 reg = <0x50014000 0x4000>;
279 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
280 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
281 clock-names = "ipg", "baud";
282 dmas = <&sdma 24 1 0>,
284 dma-names = "rx", "tx";
285 fsl,fifo-depth = <15>;
289 esdhc3: esdhc@50020000 {
290 compatible = "fsl,imx53-esdhc";
291 reg = <0x50020000 0x4000>;
293 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
294 <&clks IMX5_CLK_DUMMY>,
295 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
296 clock-names = "ipg", "ahb", "per";
301 esdhc4: esdhc@50024000 {
302 compatible = "fsl,imx53-esdhc";
303 reg = <0x50024000 0x4000>;
305 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
306 <&clks IMX5_CLK_DUMMY>,
307 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
308 clock-names = "ipg", "ahb", "per";
314 aipstz1: bridge@53f00000 {
315 compatible = "fsl,imx53-aipstz";
316 reg = <0x53f00000 0x60>;
319 usbotg: usb@53f80000 {
320 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
321 reg = <0x53f80000 0x0200>;
323 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
324 fsl,usbmisc = <&usbmisc 0>;
325 fsl,usbphy = <&usbphy0>;
329 usbh1: usb@53f80200 {
330 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
331 reg = <0x53f80200 0x0200>;
333 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
334 fsl,usbmisc = <&usbmisc 1>;
335 fsl,usbphy = <&usbphy1>;
340 usbh2: usb@53f80400 {
341 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
342 reg = <0x53f80400 0x0200>;
344 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
345 fsl,usbmisc = <&usbmisc 2>;
350 usbh3: usb@53f80600 {
351 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
352 reg = <0x53f80600 0x0200>;
354 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
355 fsl,usbmisc = <&usbmisc 3>;
360 usbmisc: usbmisc@53f80800 {
362 compatible = "fsl,imx53-usbmisc";
363 reg = <0x53f80800 0x200>;
364 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
367 gpio1: gpio@53f84000 {
368 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
369 reg = <0x53f84000 0x4000>;
370 interrupts = <50 51>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
377 gpio2: gpio@53f88000 {
378 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
379 reg = <0x53f88000 0x4000>;
380 interrupts = <52 53>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
387 gpio3: gpio@53f8c000 {
388 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
389 reg = <0x53f8c000 0x4000>;
390 interrupts = <54 55>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
397 gpio4: gpio@53f90000 {
398 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
399 reg = <0x53f90000 0x4000>;
400 interrupts = <56 57>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
408 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
409 reg = <0x53f94000 0x4000>;
411 clocks = <&clks IMX5_CLK_DUMMY>;
415 wdog1: wdog@53f98000 {
416 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
417 reg = <0x53f98000 0x4000>;
419 clocks = <&clks IMX5_CLK_DUMMY>;
422 wdog2: wdog@53f9c000 {
423 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
424 reg = <0x53f9c000 0x4000>;
426 clocks = <&clks IMX5_CLK_DUMMY>;
430 gpt: timer@53fa0000 {
431 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
432 reg = <0x53fa0000 0x4000>;
434 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
435 <&clks IMX5_CLK_GPT_HF_GATE>;
436 clock-names = "ipg", "per";
440 compatible = "fsl,imx53-rtc";
441 reg = <0x53fa4000 0x4000>;
443 clocks = <&clks IMX5_CLK_SRTC_GATE>;
446 iomuxc: iomuxc@53fa8000 {
447 compatible = "fsl,imx53-iomuxc";
448 reg = <0x53fa8000 0x4000>;
451 gpr: iomuxc-gpr@53fa8000 {
452 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
453 reg = <0x53fa8000 0xc>;
457 #address-cells = <1>;
459 compatible = "fsl,imx53-ldb";
460 reg = <0x53fa8008 0x4>;
462 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
463 <&clks IMX5_CLK_LDB_DI1_SEL>,
464 <&clks IMX5_CLK_IPU_DI0_SEL>,
465 <&clks IMX5_CLK_IPU_DI1_SEL>,
466 <&clks IMX5_CLK_LDB_DI0_GATE>,
467 <&clks IMX5_CLK_LDB_DI1_GATE>;
468 clock-names = "di0_pll", "di1_pll",
469 "di0_sel", "di1_sel",
474 #address-cells = <1>;
483 remote-endpoint = <&ipu_di0_lvds0>;
493 #address-cells = <1>;
502 remote-endpoint = <&ipu_di1_lvds1>;
514 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
515 reg = <0x53fb4000 0x4000>;
516 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
517 <&clks IMX5_CLK_PWM1_HF_GATE>;
518 clock-names = "ipg", "per";
524 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
525 reg = <0x53fb8000 0x4000>;
526 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
527 <&clks IMX5_CLK_PWM2_HF_GATE>;
528 clock-names = "ipg", "per";
532 uart1: serial@53fbc000 {
533 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
534 reg = <0x53fbc000 0x4000>;
536 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
537 <&clks IMX5_CLK_UART1_PER_GATE>;
538 clock-names = "ipg", "per";
539 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
540 dma-names = "rx", "tx";
544 uart2: serial@53fc0000 {
545 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
546 reg = <0x53fc0000 0x4000>;
548 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
549 <&clks IMX5_CLK_UART2_PER_GATE>;
550 clock-names = "ipg", "per";
551 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
552 dma-names = "rx", "tx";
557 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
558 reg = <0x53fc8000 0x4000>;
560 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
561 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
562 clock-names = "ipg", "per";
567 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
568 reg = <0x53fcc000 0x4000>;
570 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
571 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
572 clock-names = "ipg", "per";
577 compatible = "fsl,imx53-src", "fsl,imx51-src";
578 reg = <0x53fd0000 0x4000>;
583 compatible = "fsl,imx53-ccm";
584 reg = <0x53fd4000 0x4000>;
585 interrupts = <0 71 0x04 0 72 0x04>;
589 gpio5: gpio@53fdc000 {
590 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
591 reg = <0x53fdc000 0x4000>;
592 interrupts = <103 104>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
599 gpio6: gpio@53fe0000 {
600 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
601 reg = <0x53fe0000 0x4000>;
602 interrupts = <105 106>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
609 gpio7: gpio@53fe4000 {
610 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
611 reg = <0x53fe4000 0x4000>;
612 interrupts = <107 108>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
620 #address-cells = <1>;
622 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
623 reg = <0x53fec000 0x4000>;
625 clocks = <&clks IMX5_CLK_I2C3_GATE>;
629 uart4: serial@53ff0000 {
630 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
631 reg = <0x53ff0000 0x4000>;
633 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
634 <&clks IMX5_CLK_UART4_PER_GATE>;
635 clock-names = "ipg", "per";
636 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
637 dma-names = "rx", "tx";
642 aips@60000000 { /* AIPS2 */
643 compatible = "fsl,aips-bus", "simple-bus";
644 #address-cells = <1>;
646 reg = <0x60000000 0x10000000>;
649 aipstz2: bridge@63f00000 {
650 compatible = "fsl,imx53-aipstz";
651 reg = <0x63f00000 0x60>;
655 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
656 reg = <0x63f98000 0x4000>;
658 clocks = <&clks IMX5_CLK_IIM_GATE>;
661 uart5: serial@63f90000 {
662 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
663 reg = <0x63f90000 0x4000>;
665 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
666 <&clks IMX5_CLK_UART5_PER_GATE>;
667 clock-names = "ipg", "per";
668 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
669 dma-names = "rx", "tx";
673 tigerp: tigerp@63fa0000 {
674 compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
675 reg = <0x63fa0000 0x28>;
678 owire: owire@63fa4000 {
679 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
680 reg = <0x63fa4000 0x4000>;
681 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
685 ecspi2: ecspi@63fac000 {
686 #address-cells = <1>;
688 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
689 reg = <0x63fac000 0x4000>;
691 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
692 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
693 clock-names = "ipg", "per";
697 sdma: sdma@63fb0000 {
698 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
699 reg = <0x63fb0000 0x4000>;
701 clocks = <&clks IMX5_CLK_SDMA_GATE>,
702 <&clks IMX5_CLK_AHB>;
703 clock-names = "ipg", "ahb";
705 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
708 cspi: cspi@63fc0000 {
709 #address-cells = <1>;
711 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
712 reg = <0x63fc0000 0x4000>;
714 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
715 <&clks IMX5_CLK_CSPI_IPG_GATE>;
716 clock-names = "ipg", "per";
721 #address-cells = <1>;
723 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
724 reg = <0x63fc4000 0x4000>;
726 clocks = <&clks IMX5_CLK_I2C2_GATE>;
731 #address-cells = <1>;
733 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
734 reg = <0x63fc8000 0x4000>;
736 clocks = <&clks IMX5_CLK_I2C1_GATE>;
741 #sound-dai-cells = <0>;
742 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
744 reg = <0x63fcc000 0x4000>;
746 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
747 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
748 clock-names = "ipg", "baud";
749 dmas = <&sdma 28 0 0>,
751 dma-names = "rx", "tx";
752 fsl,fifo-depth = <15>;
756 audmux: audmux@63fd0000 {
757 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
758 reg = <0x63fd0000 0x4000>;
763 compatible = "fsl,imx53-nand";
764 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
766 clocks = <&clks IMX5_CLK_NFC_GATE>;
771 #sound-dai-cells = <0>;
772 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
774 reg = <0x63fe8000 0x4000>;
776 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
777 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
778 clock-names = "ipg", "baud";
779 dmas = <&sdma 46 0 0>,
781 dma-names = "rx", "tx";
782 fsl,fifo-depth = <15>;
786 fec: ethernet@63fec000 {
787 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
788 reg = <0x63fec000 0x4000>;
790 clocks = <&clks IMX5_CLK_FEC_GATE>,
791 <&clks IMX5_CLK_FEC_GATE>,
792 <&clks IMX5_CLK_FEC_GATE>;
793 clock-names = "ipg", "ahb", "ptp";
798 compatible = "fsl,imx53-tve";
799 reg = <0x63ff0000 0x1000>;
801 clocks = <&clks IMX5_CLK_TVE_GATE>,
802 <&clks IMX5_CLK_IPU_DI1_SEL>;
803 clock-names = "tve", "di_sel";
808 remote-endpoint = <&ipu_di1_tve>;
814 compatible = "fsl,imx53-vpu", "cnm,coda7541";
815 reg = <0x63ff4000 0x1000>;
817 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
818 <&clks IMX5_CLK_VPU_GATE>;
819 clock-names = "per", "ahb";
824 sahara: crypto@63ff8000 {
825 compatible = "fsl,imx53-sahara";
826 reg = <0x63ff8000 0x4000>;
827 interrupts = <19 20>;
828 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
829 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
830 clock-names = "ipg", "ahb";
834 ocram: sram@f8000000 {
835 compatible = "mmio-sram";
836 reg = <0xf8000000 0x20000>;
837 clocks = <&clks IMX5_CLK_OCRAM>;