arch/arm/boot/dts/imx51-babbage.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2011 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 /dts-v1/;
   7 #include "imx51.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX51 Babbage Board";
  11         compatible = "fsl,imx51-babbage", "fsl,imx51";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         memory@90000000 {
  18                 device_type = "memory";
  19                 reg = <0x90000000 0x20000000>;
  20         };
  21
  22         ckih1 {
  23                 clock-frequency = <22579200>;
  24         };
  25
  26         clk_osc: clk-osc {
  27                 compatible = "fixed-clock";
  28                 #clock-cells = <0>;
  29                 clock-frequency = <26000000>;
  30         };
  31
  32         clk_osc_gate: clk-osc-gate {
  33                 compatible = "gpio-gate-clock";
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&pinctrl_clk26mhz_osc>;
  36                 clocks = <&clk_osc>;
  37                 #clock-cells = <0>;
  38                 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
  39         };
  40
  41         clk_audio: clk-audio {
  42                 compatible = "gpio-gate-clock";
  43                 pinctrl-names = "default";
  44                 pinctrl-0 = <&pinctrl_clk26mhz_audio>;
  45                 clocks = <&clk_osc_gate>;
  46                 #clock-cells = <0>;
  47                 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  48         };
  49
  50         clk_usb: clk-usb {
  51                 compatible = "gpio-gate-clock";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_clk26mhz_usb>;
  54                 clocks = <&clk_osc_gate>;
  55                 #clock-cells = <0>;
  56                 enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  57         };
  58
  59         display1: disp1 {
  60                 compatible = "fsl,imx-parallel-display";
  61                 interface-pix-fmt = "rgb24";
  62                 pinctrl-names = "default";
  63                 pinctrl-0 = <&pinctrl_ipu_disp1>;
  64                 display-timings {
  65                         native-mode = <&timing0>;
  66                         timing0: dvi {
  67                                 clock-frequency = <65000000>;
  68                                 hactive = <1024>;
  69                                 vactive = <768>;
  70                                 hback-porch = <220>;
  71                                 hfront-porch = <40>;
  72                                 vback-porch = <21>;
  73                                 vfront-porch = <7>;
  74                                 hsync-len = <60>;
  75                                 vsync-len = <10>;
  76                         };
  77                 };
  78
  79                 port {
  80                         display0_in: endpoint {
  81                                 remote-endpoint = <&ipu_di0_disp1>;
  82                         };
  83                 };
  84         };
  85
  86         display2: disp2 {
  87                 compatible = "fsl,imx-parallel-display";
  88                 interface-pix-fmt = "rgb565";
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&pinctrl_ipu_disp2>;
  91                 status = "disabled";
  92                 display-timings {
  93                         native-mode = <&timing1>;
  94                         timing1: claawvga {
  95                                 clock-frequency = <27000000>;
  96                                 hactive = <800>;
  97                                 vactive = <480>;
  98                                 hback-porch = <40>;
  99                                 hfront-porch = <60>;
 100                                 vback-porch = <10>;
 101                                 vfront-porch = <10>;
 102                                 hsync-len = <20>;
 103                                 vsync-len = <10>;
 104                                 hsync-active = <0>;
 105                                 vsync-active = <0>;
 106                                 de-active = <1>;
 107                                 pixelclk-active = <0>;
 108                         };
 109                 };
 110
 111                 port {
 112                         display1_in: endpoint {
 113                                 remote-endpoint = <&ipu_di1_disp2>;
 114                         };
 115                 };
 116         };
 117
 118         gpio-keys {
 119                 compatible = "gpio-keys";
 120                 pinctrl-names = "default";
 121                 pinctrl-0 = <&pinctrl_gpio_keys>;
 122
 123                 power {
 124                         label = "Power Button";
 125                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 126                         linux,code = <KEY_POWER>;
 127                         wakeup-source;
 128                 };
 129         };
 130
 131         leds {
 132                 compatible = "gpio-leds";
 133                 pinctrl-names = "default";
 134                 pinctrl-0 = <&pinctrl_gpio_leds>;
 135
 136                 led-diagnostic {
 137                         label = "diagnostic";
 138                         gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 139                 };
 140         };
 141
 142         regulators {
 143                 compatible = "simple-bus";
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146
 147                 reg_hub_reset: regulator@0 {
 148                         compatible = "regulator-fixed";
 149                         pinctrl-names = "default";
 150                         pinctrl-0 = <&pinctrl_usbotgreg>;
 151                         reg = <0>;
 152                         regulator-name = "hub_reset";
 153                         regulator-min-microvolt = <5000000>;
 154                         regulator-max-microvolt = <5000000>;
 155                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 156                         enable-active-high;
 157                 };
 158         };
 159
 160         sound {
 161                 compatible = "fsl,imx51-babbage-sgtl5000",
 162                              "fsl,imx-audio-sgtl5000";
 163                 model = "imx51-babbage-sgtl5000";
 164                 ssi-controller = <&ssi2>;
 165                 audio-codec = <&sgtl5000>;
 166                 audio-routing =
 167                         "MIC_IN", "Mic Jack",
 168                         "Mic Jack", "Mic Bias",
 169                         "Headphone Jack", "HP_OUT";
 170                 mux-int-port = <2>;
 171                 mux-ext-port = <3>;
 172         };
 173
 174         usbphy1: usbphy1 {
 175                 compatible = "usb-nop-xceiv";
 176                 pinctrl-names = "default";
 177                 pinctrl-0 = <&pinctrl_usbh1reg>;
 178                 clocks = <&clk_usb>;
 179                 clock-names = "main_clk";
 180                 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
 181                 vcc-supply = <&vusb_reg>;
 182                 #phy-cells = <0>;
 183         };
 184 };
 185
 186 &audmux {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_audmux>;
 189         status = "okay";
 190 };
 191
 192 &ecspi1 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&pinctrl_ecspi1>;
 195         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
 196                    <&gpio4 25 GPIO_ACTIVE_LOW>;
 197         status = "okay";
 198
 199         pmic: mc13892@0 {
 200                 compatible = "fsl,mc13892";
 201                 pinctrl-names = "default";
 202                 pinctrl-0 = <&pinctrl_pmic>;
 203                 spi-max-frequency = <6000000>;
 204                 spi-cs-high;
 205                 reg = <0>;
 206                 interrupt-parent = <&gpio1>;
 207                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 208                 fsl,mc13xxx-uses-rtc;
 209
 210                 regulators {
 211                         sw1_reg: sw1 {
 212                                 regulator-min-microvolt = <600000>;
 213                                 regulator-max-microvolt = <1375000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                         };
 217
 218                         sw2_reg: sw2 {
 219                                 regulator-min-microvolt = <900000>;
 220                                 regulator-max-microvolt = <1850000>;
 221                                 regulator-boot-on;
 222                                 regulator-always-on;
 223                         };
 224
 225                         sw3_reg: sw3 {
 226                                 regulator-min-microvolt = <1100000>;
 227                                 regulator-max-microvolt = <1850000>;
 228                                 regulator-boot-on;
 229                                 regulator-always-on;
 230                         };
 231
 232                         sw4_reg: sw4 {
 233                                 regulator-min-microvolt = <1100000>;
 234                                 regulator-max-microvolt = <1850000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                         };
 238
 239                         vpll_reg: vpll {
 240                                 regulator-min-microvolt = <1050000>;
 241                                 regulator-max-microvolt = <1800000>;
 242                                 regulator-boot-on;
 243                                 regulator-always-on;
 244                         };
 245
 246                         vdig_reg: vdig {
 247                                 regulator-min-microvolt = <1650000>;
 248                                 regulator-max-microvolt = <1650000>;
 249                                 regulator-boot-on;
 250                         };
 251
 252                         vsd_reg: vsd {
 253                                 regulator-min-microvolt = <1800000>;
 254                                 regulator-max-microvolt = <3150000>;
 255                         };
 256
 257                         vusb_reg: vusb {
 258                                 regulator-boot-on;
 259                         };
 260
 261                         vusb2_reg: vusb2 {
 262                                 regulator-min-microvolt = <2400000>;
 263                                 regulator-max-microvolt = <2775000>;
 264                                 regulator-boot-on;
 265                                 regulator-always-on;
 266                         };
 267
 268                         vvideo_reg: vvideo {
 269                                 regulator-min-microvolt = <2775000>;
 270                                 regulator-max-microvolt = <2775000>;
 271                         };
 272
 273                         vaudio_reg: vaudio {
 274                                 regulator-min-microvolt = <2300000>;
 275                                 regulator-max-microvolt = <3000000>;
 276                         };
 277
 278                         vcam_reg: vcam {
 279                                 regulator-min-microvolt = <2500000>;
 280                                 regulator-max-microvolt = <3000000>;
 281                         };
 282
 283                         vgen1_reg: vgen1 {
 284                                 regulator-min-microvolt = <1200000>;
 285                                 regulator-max-microvolt = <1200000>;
 286                         };
 287
 288                         vgen2_reg: vgen2 {
 289                                 regulator-min-microvolt = <1200000>;
 290                                 regulator-max-microvolt = <3150000>;
 291                                 regulator-always-on;
 292                         };
 293
 294                         vgen3_reg: vgen3 {
 295                                 regulator-min-microvolt = <1800000>;
 296                                 regulator-max-microvolt = <2900000>;
 297                                 regulator-always-on;
 298                         };
 299                 };
 300         };
 301
 302         flash: at45db321d@1 {
 303                 #address-cells = <1>;
 304                 #size-cells = <1>;
 305                 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
 306                 spi-max-frequency = <25000000>;
 307                 reg = <1>;
 308
 309                 partition@0 {
 310                         label = "U-Boot";
 311                         reg = <0x0 0x40000>;
 312                         read-only;
 313                 };
 314
 315                 partition@40000 {
 316                         label = "Kernel";
 317                         reg = <0x40000 0x3c0000>;
 318                 };
 319         };
 320 };
 321
 322 &esdhc1 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_esdhc1>;
 325         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 326         wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 327         status = "okay";
 328 };
 329
 330 &esdhc2 {
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_esdhc2>;
 333         cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
 334         wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 335         status = "okay";
 336 };
 337
 338 &fec {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_fec>;
 341         phy-mode = "mii";
 342         phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
 343         phy-reset-duration = <1>;
 344         status = "okay";
 345 };
 346
 347 &i2c1 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&pinctrl_i2c1>;
 350         status = "okay";
 351 };
 352
 353 &i2c2 {
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_i2c2>;
 356         status = "okay";
 357
 358         sgtl5000: codec@a {
 359                 compatible = "fsl,sgtl5000";
 360                 reg = <0x0a>;
 361                 #sound-dai-cells = <0>;
 362                 clocks = <&clk_audio>;
 363                 VDDA-supply = <&vdig_reg>;
 364                 VDDIO-supply = <&vvideo_reg>;
 365         };
 366 };
 367
 368 &ipu_di0_disp1 {
 369         remote-endpoint = <&display0_in>;
 370 };
 371
 372 &ipu_di1_disp2 {
 373         remote-endpoint = <&display1_in>;
 374 };
 375
 376 &kpp {
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&pinctrl_kpp>;
 379         linux,keymap = <
 380                 MATRIX_KEY(0, 0, KEY_UP)
 381                 MATRIX_KEY(0, 1, KEY_DOWN)
 382                 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
 383                 MATRIX_KEY(0, 3, KEY_HOME)
 384                 MATRIX_KEY(1, 0, KEY_RIGHT)
 385                 MATRIX_KEY(1, 1, KEY_LEFT)
 386                 MATRIX_KEY(1, 2, KEY_ENTER)
 387                 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
 388                 MATRIX_KEY(2, 0, KEY_F6)
 389                 MATRIX_KEY(2, 1, KEY_F8)
 390                 MATRIX_KEY(2, 2, KEY_F9)
 391                 MATRIX_KEY(2, 3, KEY_F10)
 392                 MATRIX_KEY(3, 0, KEY_F1)
 393                 MATRIX_KEY(3, 1, KEY_F2)
 394                 MATRIX_KEY(3, 2, KEY_F3)
 395                 MATRIX_KEY(3, 3, KEY_POWER)
 396         >;
 397         status = "okay";
 398 };
 399
 400 &pmu {
 401         secure-reg-access;
 402 };
 403
 404 &ssi2 {
 405         status = "okay";
 406 };
 407
 408 &uart1 {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_uart1>;
 411         uart-has-rtscts;
 412         status = "okay";
 413 };
 414
 415 &uart2 {
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&pinctrl_uart2>;
 418         status = "okay";
 419 };
 420
 421 &uart3 {
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&pinctrl_uart3>;
 424         uart-has-rtscts;
 425         status = "okay";
 426 };
 427
 428 &usbh1 {
 429         pinctrl-names = "default";
 430         pinctrl-0 = <&pinctrl_usbh1>;
 431         vbus-supply = <&reg_hub_reset>;
 432         fsl,usbphy = <&usbphy1>;
 433         phy_type = "ulpi";
 434         status = "okay";
 435 };
 436
 437 &usbphy0 {
 438         vcc-supply = <&vusb_reg>;
 439 };
 440
 441 &usbotg {
 442         dr_mode = "otg";
 443         disable-over-current;
 444         phy_type = "utmi_wide";
 445         status = "okay";
 446 };
 447
 448 &iomuxc {
 449         imx51-babbage {
 450                 pinctrl_audmux: audmuxgrp {
 451                         fsl,pins = <
 452                                 MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
 453                                 MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
 454                                 MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
 455                                 MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
 456                         >;
 457                 };
 458
 459                 pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
 460                         fsl,pins = <
 461                                 MX51_PAD_CSPI1_RDY__GPIO4_26            0x85
 462                         >;
 463                 };
 464
 465                 pinctrl_clk26mhz_osc: clk26mhzoscgrp {
 466                         fsl,pins = <
 467                                 MX51_PAD_DI1_PIN12__GPIO3_1             0x85
 468                         >;
 469                 };
 470
 471                 pinctrl_clk26mhz_usb: clk26mhzusbgrp {
 472                         fsl,pins = <
 473                                 MX51_PAD_EIM_D17__GPIO2_1               0x85
 474                         >;
 475                 };
 476
 477                 pinctrl_ecspi1: ecspi1grp {
 478                         fsl,pins = <
 479                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
 480                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
 481                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
 482                                 MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
 483                                 MX51_PAD_CSPI1_SS1__GPIO4_25            0x85 /* CS1 */
 484                         >;
 485                 };
 486
 487                 pinctrl_esdhc1: esdhc1grp {
 488                         fsl,pins = <
 489                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
 490                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
 491                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
 492                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
 493                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
 494                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
 495                                 MX51_PAD_GPIO1_0__GPIO1_0               0x100
 496                                 MX51_PAD_GPIO1_1__GPIO1_1               0x100
 497                         >;
 498                 };
 499
 500                 pinctrl_esdhc2: esdhc2grp {
 501                         fsl,pins = <
 502                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
 503                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
 504                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
 505                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
 506                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
 507                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
 508                                 MX51_PAD_GPIO1_5__GPIO1_5               0x100 /* WP */
 509                                 MX51_PAD_GPIO1_6__GPIO1_6               0x100 /* CD */
 510                         >;
 511                 };
 512
 513                 pinctrl_fec: fecgrp {
 514                         fsl,pins = <
 515                                 MX51_PAD_EIM_EB2__FEC_MDIO              0x000001f5
 516                                 MX51_PAD_EIM_EB3__FEC_RDATA1            0x00000085
 517                                 MX51_PAD_EIM_CS2__FEC_RDATA2            0x00000085
 518                                 MX51_PAD_EIM_CS3__FEC_RDATA3            0x00000085
 519                                 MX51_PAD_EIM_CS4__FEC_RX_ER             0x00000180
 520                                 MX51_PAD_EIM_CS5__FEC_CRS               0x00000180
 521                                 MX51_PAD_NANDF_RB2__FEC_COL             0x00000180
 522                                 MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x00000180
 523                                 MX51_PAD_NANDF_D9__FEC_RDATA0           0x00002180
 524                                 MX51_PAD_NANDF_D8__FEC_TDATA0           0x00002004
 525                                 MX51_PAD_NANDF_CS2__FEC_TX_ER           0x00002004
 526                                 MX51_PAD_NANDF_CS3__FEC_MDC             0x00002004
 527                                 MX51_PAD_NANDF_CS4__FEC_TDATA1          0x00002004
 528                                 MX51_PAD_NANDF_CS5__FEC_TDATA2          0x00002004
 529                                 MX51_PAD_NANDF_CS6__FEC_TDATA3          0x00002004
 530                                 MX51_PAD_NANDF_CS7__FEC_TX_EN           0x00002004
 531                                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x00002180
 532                                 MX51_PAD_NANDF_D11__FEC_RX_DV           0x000020a4
 533                                 MX51_PAD_EIM_A20__GPIO2_14              0x00000085 /* Phy Reset */
 534                         >;
 535                 };
 536
 537                 pinctrl_gpio_keys: gpiokeysgrp {
 538                         fsl,pins = <
 539                                 MX51_PAD_EIM_A27__GPIO2_21              0x5
 540                         >;
 541                 };
 542
 543                 pinctrl_gpio_leds: gpioledsgrp {
 544                         fsl,pins = <
 545                                 MX51_PAD_EIM_D22__GPIO2_6               0x80000000
 546                         >;
 547                 };
 548
 549                 pinctrl_i2c1: i2c1grp {
 550                         fsl,pins = <
 551                                 MX51_PAD_EIM_D19__I2C1_SCL              0x400001ed
 552                                 MX51_PAD_EIM_D16__I2C1_SDA              0x400001ed
 553                         >;
 554                 };
 555
 556                 pinctrl_i2c2: i2c2grp {
 557                         fsl,pins = <
 558                                 MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
 559                                 MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
 560                         >;
 561                 };
 562
 563                 pinctrl_ipu_disp1: ipudisp1grp {
 564                         fsl,pins = <
 565                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
 566                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
 567                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
 568                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
 569                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
 570                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
 571                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
 572                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
 573                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
 574                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
 575                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
 576                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
 577                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
 578                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
 579                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
 580                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
 581                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
 582                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
 583                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
 584                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
 585                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
 586                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
 587                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
 588                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
 589                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
 590                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
 591                         >;
 592                 };
 593
 594                 pinctrl_ipu_disp2: ipudisp2grp {
 595                         fsl,pins = <
 596                                 MX51_PAD_DISP2_DAT0__DISP2_DAT0         0x5
 597                                 MX51_PAD_DISP2_DAT1__DISP2_DAT1         0x5
 598                                 MX51_PAD_DISP2_DAT2__DISP2_DAT2         0x5
 599                                 MX51_PAD_DISP2_DAT3__DISP2_DAT3         0x5
 600                                 MX51_PAD_DISP2_DAT4__DISP2_DAT4         0x5
 601                                 MX51_PAD_DISP2_DAT5__DISP2_DAT5         0x5
 602                                 MX51_PAD_DISP2_DAT6__DISP2_DAT6         0x5
 603                                 MX51_PAD_DISP2_DAT7__DISP2_DAT7         0x5
 604                                 MX51_PAD_DISP2_DAT8__DISP2_DAT8         0x5
 605                                 MX51_PAD_DISP2_DAT9__DISP2_DAT9         0x5
 606                                 MX51_PAD_DISP2_DAT10__DISP2_DAT10       0x5
 607                                 MX51_PAD_DISP2_DAT11__DISP2_DAT11       0x5
 608                                 MX51_PAD_DISP2_DAT12__DISP2_DAT12       0x5
 609                                 MX51_PAD_DISP2_DAT13__DISP2_DAT13       0x5
 610                                 MX51_PAD_DISP2_DAT14__DISP2_DAT14       0x5
 611                                 MX51_PAD_DISP2_DAT15__DISP2_DAT15       0x5
 612                                 MX51_PAD_DI2_PIN2__DI2_PIN2             0x5
 613                                 MX51_PAD_DI2_PIN3__DI2_PIN3             0x5
 614                                 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
 615                                 MX51_PAD_DI_GP4__DI2_PIN15              0x5
 616                         >;
 617                 };
 618
 619                 pinctrl_kpp: kppgrp {
 620                         fsl,pins = <
 621                                 MX51_PAD_KEY_ROW0__KEY_ROW0             0xe0
 622                                 MX51_PAD_KEY_ROW1__KEY_ROW1             0xe0
 623                                 MX51_PAD_KEY_ROW2__KEY_ROW2             0xe0
 624                                 MX51_PAD_KEY_ROW3__KEY_ROW3             0xe0
 625                                 MX51_PAD_KEY_COL0__KEY_COL0             0xe8
 626                                 MX51_PAD_KEY_COL1__KEY_COL1             0xe8
 627                                 MX51_PAD_KEY_COL2__KEY_COL2             0xe8
 628                                 MX51_PAD_KEY_COL3__KEY_COL3             0xe8
 629                         >;
 630                 };
 631
 632                 pinctrl_pmic: pmicgrp {
 633                         fsl,pins = <
 634                                 MX51_PAD_GPIO1_8__GPIO1_8               0xe5 /* IRQ */
 635                         >;
 636                 };
 637
 638                 pinctrl_uart1: uart1grp {
 639                         fsl,pins = <
 640                                 MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
 641                                 MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
 642                                 MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
 643                                 MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
 644                         >;
 645                 };
 646
 647                 pinctrl_uart2: uart2grp {
 648                         fsl,pins = <
 649                                 MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
 650                                 MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
 651                         >;
 652                 };
 653
 654                 pinctrl_uart3: uart3grp {
 655                         fsl,pins = <
 656                                 MX51_PAD_EIM_D25__UART3_RXD             0x1c5
 657                                 MX51_PAD_EIM_D26__UART3_TXD             0x1c5
 658                                 MX51_PAD_EIM_D27__UART3_RTS             0x1c5
 659                                 MX51_PAD_EIM_D24__UART3_CTS             0x1c5
 660                         >;
 661                 };
 662
 663                 pinctrl_usbh1: usbh1grp {
 664                         fsl,pins = <
 665                                 MX51_PAD_USBH1_CLK__USBH1_CLK           0x80000000
 666                                 MX51_PAD_USBH1_DIR__USBH1_DIR           0x80000000
 667                                 MX51_PAD_USBH1_NXT__USBH1_NXT           0x80000000
 668                                 MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x80000000
 669                                 MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x80000000
 670                                 MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x80000000
 671                                 MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x80000000
 672                                 MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x80000000
 673                                 MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x80000000
 674                                 MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x80000000
 675                                 MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x80000000
 676                         >;
 677                 };
 678
 679                 pinctrl_usbh1reg: usbh1reggrp {
 680                         fsl,pins = <
 681                                 MX51_PAD_EIM_D21__GPIO2_5               0x85
 682                         >;
 683                 };
 684
 685                 pinctrl_usbotgreg: usbotgreggrp {
 686                         fsl,pins = <
 687                                 MX51_PAD_GPIO1_7__GPIO1_7               0x85
 688                         >;
 689                 };
 690         };
 691 };